d11f81afd5
The Qualcomm TCSR is some top level glue between multiple IP blocks, both for doing configuration of said IP blocks, some IPC between them (mostly between multiple execution environments - eg trustzone and non-TZ), and interrupt status bits for them. However, for the IPQ4018/IPQ4019, it only is used as a small subset of IP block configuration. As for what it actually gets used as for other Qualcomm chipsets? Well, that'll have to wait. It's a bit of a mess in linux and openwrt. See, every different SoC support branch ends up with some different TCSR code for it. So instead, I'm going to land a single TCSR driver that I'm going to use for the IPQ4018/IPQ4019. When I add the next chipset, I'll figure out how to organise things so there's a single TCSR driver that works for multiple platforms.
241 lines
6.4 KiB
C
241 lines
6.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/gpio.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/qcom_tcsr/qcom_tcsr_var.h>
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#include <dev/qcom_tcsr/qcom_tcsr_reg.h>
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/*
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* The linux-msm branches that support IPQ4018 use "ipq,tcsr".
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* The openwrt addons use qcom,tcsr. So for now support both.
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*
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* Also, it's not quite clear yet (since this is the first port!)
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* whether these options and registers are specific to the QCA IPQ401x
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* part or show up in different linux branches as different registers
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* but with the same driver/naming here. Let's hope that doesn't
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* happen.
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*/
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static struct ofw_compat_data compat_data[] = {
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{ "qcom,tcsr", 1 },
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{ "ipq,tcsr", 1 },
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{ NULL, 0 }
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};
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static int
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qcom_tcsr_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Qualcomm Core Top Control and Status Driver");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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qcom_tcsr_attach(device_t dev)
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{
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struct qcom_tcsr_softc *sc = device_get_softc(dev);
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int rid, ret;
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uint32_t val;
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sc->sc_dev = dev;
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/*
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* Hardware version is stored in the ofw_compat_data table.
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*/
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sc->hw_version =
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ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "ERROR: Could not map memory\n");
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ret = ENXIO;
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goto error;
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}
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/*
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* Parse out the open firmware entries to see which particular
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* configurations we need to set here.
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*/
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/*
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* USB control select.
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*
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* For linux-msm on the IPQ401x, it actually calls into the SCM
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* to make the change. OpenWRT just does a register write.
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* We'll do the register write for now.
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*/
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if (OF_getencprop(ofw_bus_get_node(dev), "qcom,usb-ctrl-select",
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&val, sizeof(val)) > 0) {
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if (bootverbose)
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device_printf(sc->sc_dev,
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"USB control select (val 0x%x)\n",
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val);
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QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_USB_PORT_SEL, val);
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}
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/*
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* USB high speed phy mode select.
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*/
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if (OF_getencprop(ofw_bus_get_node(dev), "qcom,usb-hsphy-mode-select",
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&val, sizeof(val)) > 0) {
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if (bootverbose)
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device_printf(sc->sc_dev,
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"USB high speed PHY mode select (val 0x%x)\n",
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val);
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QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_USB_HSPHY_CONFIG, val);
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}
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/*
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* Ethernet switch subsystem interface type select.
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*/
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if (OF_getencprop(ofw_bus_get_node(dev), "qcom,ess-interface-select",
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&val, sizeof(val)) > 0) {
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uint32_t reg;
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if (bootverbose)
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device_printf(sc->sc_dev,
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"ESS external interface select (val 0x%x)\n",
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val);
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reg = QCOM_TCSR_READ_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET);
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reg &= ~QCOM_TCSR_ESS_INTERFACE_SEL_MASK;
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reg |= (val & QCOM_TCSR_ESS_INTERFACE_SEL_MASK);
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QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET, reg);
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}
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/*
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* WiFi GLB select.
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*/
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if (OF_getencprop(ofw_bus_get_node(dev), "qcom,wifi_glb_cfg",
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&val, sizeof(val)) > 0) {
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if (bootverbose)
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device_printf(sc->sc_dev,
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"WIFI GLB select (val 0x%x)\n",
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val);
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QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_WIFI0_GLB_CFG_OFFSET, val);
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QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_WIFI1_GLB_CFG_OFFSET, val);
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}
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/*
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* WiFi NOC interconnect memory type.
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*/
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if (OF_getencprop(ofw_bus_get_node(dev),
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"qcom,wifi_noc_memtype_m0_m2",
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&val, sizeof(val)) > 0) {
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if (bootverbose)
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device_printf(sc->sc_dev,
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"WiFi NOC memory type (val 0x%x)\n",
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val);
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QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_PNOC_SNOC_MEMTYPE_M0_M2, val);
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}
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return (0);
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error:
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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mtx_destroy(&sc->sc_mtx);
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return (ret);
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}
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static int
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qcom_tcsr_detach(device_t dev)
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{
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struct qcom_tcsr_softc *sc = device_get_softc(dev);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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mtx_destroy(&sc->sc_mtx);
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return (0);
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}
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static device_method_t qcom_tcsr_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, qcom_tcsr_probe),
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DEVMETHOD(device_attach, qcom_tcsr_attach),
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DEVMETHOD(device_detach, qcom_tcsr_detach),
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DEVMETHOD_END
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};
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static driver_t qcom_tcsr_driver = {
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"qcom_tcsr",
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qcom_tcsr_methods,
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sizeof(struct qcom_tcsr_softc),
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};
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static devclass_t qcom_tcsr_devclass;
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/*
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* This has to be run early, before the rest of the hardware is potentially
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* probed/attached.
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*/
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EARLY_DRIVER_MODULE(qcom_tcsr, simplebus, qcom_tcsr_driver,
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qcom_tcsr_devclass, 0, 0,
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BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
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SIMPLEBUS_PNP_INFO(compat_data);
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