859159d164
Because of using more clear and same time more functional codec parser new driver is able to handle more codecs, use them better then before and without most of previous quirks. All of tested codecs itself manage playback, record, input mixing and monitoring quite fine. In all of investigated trouble cases problem was found or in nonstandard codec usage or incorrect codec configuration made by BIOS. Most of that cases could be fixed using device hints, some of which are already included to the driver. New driver supports multiple codecs per HDA bus, multiple audio function groups per codec and multiple logical sound devices per audio function group. So don't worry when you get several PCM devices instead of one, it is normal. It is usual situation with powerful codecs to provide, for example, 3 PCM devices: one for 7.1 playback and main recording, one for headset and one for digital SPDIF I/O. New driver implements Universal Audio Architecture (UAA) much better then previous one. Most information about recommended codec usage now taken from the codec configuration registers initialized by BIOS. User may alter that configuration using device hints to reconfigure logical audio devices to his needs in a very broad range up to the limits of the codec functionality. New driver supports digital PCM playback and AC3 pass-through. I am not sure about completeness of this implementation, but I have several success stories including my own. Vchans subsystem does not support AC3 pass-through so it had to be disabled for that devices at this moment. New driver is ready for multichannel playback, but until our OSS is unable to use this it will just duplicate same stereo stream into all channel pairs. New driver supports suspend/resume. I am unable to really test this part myself, but I have got several success stories. Driver has very informative verbose boot messages. So if you have any questions or problems - enable and read them first. Discussed on: freebsd-multimedia@ Tested by: many
386 lines
12 KiB
C
386 lines
12 KiB
C
/*-
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* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _HDAC_PRIVATE_H_
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#define _HDAC_PRIVATE_H_
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/****************************************************************************
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* Miscellaneous defines
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****************************************************************************/
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#define HDAC_DMA_ALIGNMENT 128
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#define HDAC_CODEC_MAX 16
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#define HDAC_MTX_NAME "hdac driver mutex"
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/****************************************************************************
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* Helper Macros
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****************************************************************************/
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#define HDAC_READ_1(mem, offset) \
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bus_space_read_1((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_READ_2(mem, offset) \
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bus_space_read_2((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_READ_4(mem, offset) \
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bus_space_read_4((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_WRITE_1(mem, offset, value) \
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bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_WRITE_2(mem, offset, value) \
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bus_space_write_2((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_WRITE_4(mem, offset, value) \
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bus_space_write_4((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_ISDCTL(sc, n) (_HDAC_ISDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDCTL(sc, n) (_HDAC_OSDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDCTL(sc, n) (_HDAC_BSDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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/****************************************************************************
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* Custom hdac malloc type
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****************************************************************************/
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MALLOC_DECLARE(M_HDAC);
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/****************************************************************************
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* struct hdac_mem
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*
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* Holds the resources necessary to describe the physical memory associated
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* with the device.
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****************************************************************************/
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struct hdac_mem {
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struct resource *mem_res;
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int mem_rid;
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bus_space_tag_t mem_tag;
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bus_space_handle_t mem_handle;
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};
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/****************************************************************************
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* struct hdac_irq
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*
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* Holds the resources necessary to describe the irq associated with the
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* device.
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****************************************************************************/
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struct hdac_irq {
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struct resource *irq_res;
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int irq_rid;
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void *irq_handle;
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};
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/****************************************************************************
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* struct hdac_dma
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*
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* This structure is used to hold all the information to manage the dma
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* states.
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****************************************************************************/
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struct hdac_dma {
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_addr_t dma_paddr;
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bus_size_t dma_size;
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caddr_t dma_vaddr;
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};
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/****************************************************************************
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* struct hdac_rirb
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*
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* Hold a response from a verb sent to a codec received via the rirb.
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****************************************************************************/
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struct hdac_rirb {
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uint32_t response;
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uint32_t response_ex;
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};
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK 0x0000000f
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET 0
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#define HDAC_RIRB_RESPONSE_EX_UNSOLICITED 0x00000010
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN(response_ex) \
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(((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \
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HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET)
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/****************************************************************************
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* struct hdac_command_list
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*
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* This structure holds the list of verbs that are to be sent to the codec
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* via the corb and the responses received via the rirb. It's allocated by
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* the codec driver and is owned by it.
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****************************************************************************/
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struct hdac_command_list {
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int num_commands;
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uint32_t *verbs;
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uint32_t *responses;
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};
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typedef int nid_t;
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struct hdac_softc;
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struct hdac_bdle {
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volatile uint32_t addrl;
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volatile uint32_t addrh;
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volatile uint32_t len;
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volatile uint32_t ioc;
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} __packed;
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#define HDA_MAX_CONNS 32
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#define HDA_MAX_NAMELEN 32
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struct hdac_widget {
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nid_t nid;
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int type;
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int enable;
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int nconns, selconn;
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int waspin;
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uint32_t pflags;
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int bindas;
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int bindseqmask;
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int ossdev;
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uint32_t ossmask;
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nid_t conns[HDA_MAX_CONNS];
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u_char connsenable[HDA_MAX_CONNS];
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char name[HDA_MAX_NAMELEN];
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struct hdac_devinfo *devinfo;
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struct {
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uint32_t widget_cap;
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uint32_t outamp_cap;
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uint32_t inamp_cap;
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uint32_t supp_stream_formats;
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uint32_t supp_pcm_size_rate;
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uint32_t eapdbtl;
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} param;
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union {
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struct {
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uint32_t config;
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uint32_t cap;
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uint32_t ctrl;
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} pin;
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} wclass;
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};
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struct hdac_audio_ctl {
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struct hdac_widget *widget, *childwidget;
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int enable;
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int index, dir, ndir;
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int mute, step, size, offset;
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int left, right, forcemute;
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uint32_t muted;
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uint32_t ossmask, possmask;
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};
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/* Association is a group of pins bound for some special function. */
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struct hdac_audio_as {
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u_char enable;
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u_char index;
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u_char dir;
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u_char pincnt;
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u_char fakeredir;
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nid_t hpredir;
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nid_t pins[16];
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nid_t dacs[16];
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int chan;
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};
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struct hdac_pcm_devinfo {
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device_t dev;
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struct hdac_devinfo *devinfo;
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int index;
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int registered;
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int play, rec;
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u_char left[SOUND_MIXER_NRDEVICES];
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u_char right[SOUND_MIXER_NRDEVICES];
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int chan_size;
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int chan_blkcnt;
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};
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/****************************************************************************
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* struct hdac_devinfo
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*
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* Holds all the parameters of a given codec function group. This is stored
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* in the ivar of each child of the hdac bus
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****************************************************************************/
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struct hdac_devinfo {
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uint8_t node_type;
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nid_t nid;
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nid_t startnode, endnode;
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int nodecnt;
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struct hdac_codec *codec;
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struct hdac_widget *widget;
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union {
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struct {
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uint32_t outamp_cap;
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uint32_t inamp_cap;
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uint32_t supp_stream_formats;
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uint32_t supp_pcm_size_rate;
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int ctlcnt, ascnt;
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struct hdac_audio_ctl *ctl;
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struct hdac_audio_as *as;
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uint32_t quirks;
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uint32_t gpio;
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int playcnt, reccnt;
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struct hdac_pcm_devinfo *devs;
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int num_devs;
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} audio;
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/* XXX undefined: modem, hdmi. */
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} function;
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};
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#define HDAC_CHN_RUNNING 0x00000001
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#define HDAC_CHN_SUSPEND 0x00000002
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struct hdac_chan {
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struct snd_dbuf *b;
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struct pcm_channel *c;
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struct pcmchan_caps caps;
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struct hdac_devinfo *devinfo;
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struct hdac_pcm_devinfo *pdevinfo;
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struct hdac_dma bdl_dma;
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uint32_t spd, fmt, fmtlist[8], pcmrates[16];
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uint32_t supp_stream_formats, supp_pcm_size_rate;
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uint32_t ptr, prevptr, blkcnt, blksz;
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uint32_t *dmapos;
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uint32_t flags;
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int dir;
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int off;
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int sid;
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int bit16, bit32;
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int as;
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nid_t io[16];
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};
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/****************************************************************************
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* struct hdac_codec
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*
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****************************************************************************/
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struct hdac_codec {
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int verbs_sent;
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int responses_received;
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nid_t cad;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision_id;
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uint8_t stepping_id;
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struct hdac_command_list *commands;
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struct hdac_softc *sc;
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struct hdac_devinfo *fgs;
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int num_fgs;
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};
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/****************************************************************************
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* struct hdac_softc
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*
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* This structure holds the current state of the hdac driver.
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****************************************************************************/
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#define HDAC_F_DMA_NOCACHE 0x00000001
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#define HDAC_F_MSI 0x00000002
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struct hdac_softc {
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device_t dev;
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device_t hdabus;
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struct mtx *lock;
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struct intr_config_hook intrhook;
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struct hdac_mem mem;
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struct hdac_irq irq;
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uint32_t pci_subvendor;
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uint32_t flags;
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struct hdac_chan *chans;
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int num_chans;
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int num_iss;
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int num_oss;
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int num_bss;
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int support_64bit;
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int streamcnt;
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int corb_size;
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struct hdac_dma corb_dma;
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int corb_wp;
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int rirb_size;
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struct hdac_dma rirb_dma;
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int rirb_rp;
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struct hdac_dma pos_dma;
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bus_dma_tag_t chan_dmat;
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/*
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* Polling
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*/
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int polling;
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int poll_ticks;
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int poll_ival;
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struct callout poll_hda;
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struct callout poll_hdac;
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struct callout poll_jack;
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struct task unsolq_task;
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#define HDAC_UNSOLQ_MAX 64
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#define HDAC_UNSOLQ_READY 0
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#define HDAC_UNSOLQ_BUSY 1
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int unsolq_rp;
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int unsolq_wp;
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int unsolq_st;
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uint32_t unsolq[HDAC_UNSOLQ_MAX];
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struct hdac_codec *codecs[HDAC_CODEC_MAX];
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};
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/****************************************************************************
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* struct hdac_command flags
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****************************************************************************/
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#define HDAC_COMMAND_FLAG_WAITOK 0x0000
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#define HDAC_COMMAND_FLAG_NOWAIT 0x0001
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#endif
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