205 lines
6.1 KiB
C
205 lines
6.1 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2004 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_desc.h"
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#include "ar5210/ar5210.h"
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#include "ar5210/ar5210reg.h"
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#include "ar5210/ar5210desc.h"
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/*
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* Return the hardware NextTBTT in TSF
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*/
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uint64_t
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ar5210GetNextTBTT(struct ath_hal *ah)
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{
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#define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10)
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return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
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#undef TU_TO_TSF
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}
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/*
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* Initialize all of the hardware registers used to send beacons.
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*/
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void
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ar5210SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
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{
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OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
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OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
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OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
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OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
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/*
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* Set the Beacon register after setting all timers.
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*/
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OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
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}
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/*
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* Legacy api to Initialize all of the beacon registers.
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*/
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void
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ar5210BeaconInit(struct ath_hal *ah,
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uint32_t next_beacon, uint32_t beacon_period)
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{
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HAL_BEACON_TIMERS bt;
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bt.bt_nexttbtt = next_beacon;
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if (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) {
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bt.bt_nextdba = (next_beacon -
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ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */
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bt.bt_nextswba = (next_beacon -
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ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */
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/*
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* The SWBA interrupt is not used for beacons in ad hoc mode
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* as we don't yet support ATIMs. So since the beacon never
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* changes, the beacon descriptor is set up once and read
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* into a special HW buffer, from which it will be
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* automagically retrieved at each DMA Beacon Alert (DBA).
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*/
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/* Set the ATIM window */
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bt.bt_nextatim = next_beacon + 0; /* NB: no ATIMs */
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} else {
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bt.bt_nextdba = ~0;
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bt.bt_nextswba = ~0;
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bt.bt_nextatim = 1;
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}
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bt.bt_intval = beacon_period &
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(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
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ar5210SetBeaconTimers(ah, &bt);
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}
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void
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ar5210ResetStaBeaconTimers(struct ath_hal *ah)
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{
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uint32_t val;
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OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
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val = OS_REG_READ(ah, AR_STA_ID1);
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val |= AR_STA_ID1_NO_PSPOLL; /* XXX */
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/* tell the h/w that the associated AP is not PCF capable */
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OS_REG_WRITE(ah, AR_STA_ID1,
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val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
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OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
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}
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/*
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* Set all the beacon related bits on the h/w for stations
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* i.e. initializes the corresponding h/w timers;
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* also tells the h/w whether to anticipate PCF beacons
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*
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* dtim_count and cfp_count from the current beacon - their current
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* values aren't necessarily maintained in the device struct
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*/
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void
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ar5210SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
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HALASSERT(bs->bs_intval != 0);
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/* if the AP will do PCF */
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if (bs->bs_cfpmaxduration != 0) {
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/* tell the h/w that the associated AP is PCF capable */
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OS_REG_WRITE(ah, AR_STA_ID1,
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(OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)
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| AR_STA_ID1_PCF);
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/* set CFP_PERIOD(1.024ms) register */
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OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
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/* set CFP_DUR(1.024ms) register to max cfp duration */
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OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
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/* set TIMER2(128us) to anticipated time of next CFP */
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OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
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} else {
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/* tell the h/w that the associated AP is not PCF capable */
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OS_REG_WRITE(ah, AR_STA_ID1,
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OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
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}
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/*
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* Set TIMER0(1.024ms) to the anticipated time of the next beacon.
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*/
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OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
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/*
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* Start the beacon timers by setting the BEACON register
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* to the beacon interval; also write the tim offset which
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* we should know by now. The code, in ar5211WriteAssocid,
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* also sets the tim offset once the AID is known which can
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* be left as such for now.
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*/
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OS_REG_WRITE(ah, AR_BEACON,
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(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
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| SM(bs->bs_intval, AR_BEACON_PERIOD)
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| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
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);
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/*
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* Configure the BMISS interrupt. Note that we
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* assume the caller blocks interrupts while enabling
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* the threshold.
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*/
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/*
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* Interrupt works only on Crete.
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*/
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if (AH_PRIVATE(ah)->ah_macRev < AR_SREV_CRETE)
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return;
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/*
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* Counter is only 3-bits.
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* Count of 0 with BMISS interrupt enabled will hang the system
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* with too many interrupts
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*/
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if (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_CRETE &&
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(bs->bs_bmissthreshold&7) == 0) {
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#ifdef AH_DEBUG
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ath_hal_printf(ah, "%s: invalid beacon miss threshold %u\n",
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__func__, bs->bs_bmissthreshold);
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#endif
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return;
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}
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#define BMISS_MAX (AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S)
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/*
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* Configure the BMISS interrupt. Note that we
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* assume the caller blocks interrupts while enabling
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* the threshold.
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*
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* NB: the beacon miss count field is only 3 bits which
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* is much smaller than what's found on later parts;
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* clamp overflow values as a safeguard.
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*/
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ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
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| SM(bs->bs_bmissthreshold > BMISS_MAX ?
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BMISS_MAX : bs->bs_bmissthreshold,
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AR_RSSI_THR_BM_THR);
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OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
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#undef BMISS_MAX
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}
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