137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2004 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar5210/ar5210.h"
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#include "ar5210/ar5210reg.h"
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/*
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* Return non-zero if an interrupt is pending.
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*/
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HAL_BOOL
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ar5210IsInterruptPending(struct ath_hal *ah)
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{
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return (OS_REG_READ(ah, AR_INTPEND) ? AH_TRUE : AH_FALSE);
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}
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/*
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* Read the Interrupt Status Register value and return
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* an abstracted bitmask of the data found in the ISR.
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* Note that reading the ISR clear pending interrupts.
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*/
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HAL_BOOL
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ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
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{
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#define AR_FATAL_INT \
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(AR_ISR_MCABT_INT | AR_ISR_SSERR_INT | AR_ISR_DPERR_INT | AR_ISR_RXORN_INT)
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struct ath_hal_5210 *ahp = AH5210(ah);
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uint32_t isr;
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isr = OS_REG_READ(ah, AR_ISR);
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if (isr == 0xffffffff) {
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*masked = 0;
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return AH_FALSE;
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}
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/*
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* Mask interrupts that have no device-independent
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* representation; these are added back below. We
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* also masked with the abstracted IMR to insure no
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* status bits leak through that weren't requested
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* (e.g. RXNOFRM) and that might confuse the caller.
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*/
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*masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg;
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if (isr & AR_FATAL_INT)
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*masked |= HAL_INT_FATAL;
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if (isr & (AR_ISR_RXOK_INT | AR_ISR_RXERR_INT))
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*masked |= HAL_INT_RX;
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if (isr & (AR_ISR_TXOK_INT | AR_ISR_TXDESC_INT | AR_ISR_TXERR_INT | AR_ISR_TXEOL_INT))
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*masked |= HAL_INT_TX;
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/*
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* On fatal errors collect ISR state for debugging.
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*/
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if (*masked & HAL_INT_FATAL) {
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AH_PRIVATE(ah)->ah_fatalState[0] = isr;
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}
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return AH_TRUE;
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#undef AR_FATAL_INT
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}
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HAL_INT
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ar5210GetInterrupts(struct ath_hal *ah)
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{
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return AH5210(ah)->ah_maskReg;
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}
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HAL_INT
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ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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uint32_t omask = ahp->ah_maskReg;
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uint32_t mask;
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
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__func__, omask, ints);
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/*
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* Disable interrupts here before reading & modifying
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* the mask so that the ISR does not modify the mask
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* out from under us.
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*/
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if (omask & HAL_INT_GLOBAL) {
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
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OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
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}
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mask = ints & (HAL_INT_COMMON - HAL_INT_BNR);
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if (ints & HAL_INT_RX)
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mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
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if (ints & HAL_INT_TX) {
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if (ahp->ah_txOkInterruptMask)
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mask |= AR_IMR_TXOK_INT;
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if (ahp->ah_txErrInterruptMask)
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mask |= AR_IMR_TXERR_INT;
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if (ahp->ah_txDescInterruptMask)
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mask |= AR_IMR_TXDESC_INT;
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if (ahp->ah_txEolInterruptMask)
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mask |= AR_IMR_TXEOL_INT;
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}
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/* Write the new IMR and store off our SW copy. */
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
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OS_REG_WRITE(ah, AR_IMR, mask);
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ahp->ah_maskReg = ints;
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/* Re-enable interrupts as appropriate. */
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if (ints & HAL_INT_GLOBAL) {
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
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OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
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}
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return omask;
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}
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