511 lines
13 KiB
Plaintext
511 lines
13 KiB
Plaintext
/*
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* Copyright 2015 Vishnu Patekar
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*
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* Vishnu Patekar <vishnupatekar0510@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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};
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cpu@100 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x100>;
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};
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cpu@101 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x101>;
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};
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cpu@102 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x102>;
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};
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cpu@103 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x103>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* TODO: PRCM block has a mux for this. */
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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/*
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* This is called "internal OSC" in some places.
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* It is an internal RC-based oscillator.
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* TODO: Its controls are in the PRCM block.
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*/
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osc16M: osc16M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-output-names = "osc16M";
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};
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osc16Md512: osc16Md512_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <512>;
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clock-mult = <1>;
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clocks = <&osc16M>;
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clock-output-names = "osc16M-d512";
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};
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pll6: clk@01c20028 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-pll4-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6";
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};
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pll6d2: pll6d2_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll6>;
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clock-output-names = "pll6d2";
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};
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ahb1: clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a83t-ahb1-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
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clock-output-names = "ahb1";
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};
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apb1: apb1_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a83t-apb1-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "apb1";
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};
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apb2: clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
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clock-output-names = "apb2";
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};
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ahb2: clk@01c2005c {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-h3-ahb2-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&ahb1>, <&pll6d2>;
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clock-output-names = "ahb2";
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};
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bus_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun8i-a83t-bus-gates-clk";
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reg = <0x01c20060 0x10>;
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clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
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clock-names = "ahb1", "ahb2", "apb1", "apb2";
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clock-indices = <1>, <5>, <6>,
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<8>, <9>, <10>,
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<13>, <14>, <17>,
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<19>, <20>,
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<21>, <24>,
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<26>, <27>,
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<29>, <32>,
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<36>, <37>,
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<40>, <43>,
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<44>, <52>, <53>,
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<54>, <65>,
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<69>, <76>, <77>,
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<78>, <79>, <96>,
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<97>, <98>,
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<112>, <113>,
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<114>, <115>,
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<116>;
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clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
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"bus_mmc0", "bus_mmc1", "bus_mmc2",
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"bus_nand", "bus_sdram", "bus_emac",
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"bus_hstimer", "bus_spi0",
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"bus_spi1", "bus_usb_otg",
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"bus_ehci0", "bus_ehci1",
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"bus_ohci0", "bus_ve",
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"bus_lcd0", "bus_lcd1",
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"bus_csi", "bus_hdmi",
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"bus_de", "bus_gpu", "bus_msgbox",
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"bus_spinlock", "bus_spdif",
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"bus_pio", "bus_i2s0", "bus_i2s1",
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"bus_i2s2", "bus_tdm", "bus_i2c0",
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"bus_i2c1", "bus_i2c2",
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"bus_uart0", "bus_uart1",
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"bus_uart2", "bus_uart3",
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"bus_uart4";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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cpus_clk: clk@01f01400 {
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compatible = "allwinner,sun9i-a80-cpus-clk";
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reg = <0x01f01400 0x4>;
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#clock-cells = <0>;
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clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
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clock-output-names = "cpus";
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};
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ahb0: ahb0_clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&cpus_clk>;
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clock-output-names = "ahb0";
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};
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apb0: clk@01f0140c {
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compatible = "allwinner,sun8i-a23-apb0-clk";
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reg = <0x01f0140c 0x4>;
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#clock-cells = <0>;
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clocks = <&ahb0>;
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clock-output-names = "apb0";
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};
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apb0_gates: clk@01f01428 {
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compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
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reg = <0x01f01428 0x4>;
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#clock-cells = <1>;
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clocks = <&apb0>;
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clock-indices = <0>, <1>,
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<2>, <3>,
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<4>, <6>, <7>;
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clock-output-names = "apb0_pio", "apb0_ir",
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"apb0_timer", "apb0_rsb",
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"apb0_uart", "apb0_i2c0", "apb0_twd";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&bus_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb_reset 8>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&bus_gates 9>,
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<&mmc1_clk 0>,
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<&mmc1_clk 1>,
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<&mmc1_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb_reset 9>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&bus_gates 10>,
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<&mmc2_clk 0>,
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<&mmc2_clk 1>,
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<&mmc2_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb_reset 10>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun8i-a83t-pinctrl";
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x01c20800 0x400>;
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clocks = <&bus_gates 69>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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mmc0_pins_a: mmc0@0 {
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allwinner,pins = "PF0", "PF1", "PF2",
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"PF3", "PF4", "PF5";
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allwinner,function = "mmc0";
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allwinner,drive = <SUN4I_PINCTRL_30_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
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allwinner,pins = "PF6";
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allwinner,function = "gpio_in";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
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};
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PF2", "PF4";
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allwinner,function = "uart0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart0_pins_b: uart0@1 {
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allwinner,pins = "PB9", "PB10";
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allwinner,function = "uart0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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};
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ahb_reset: reset@01c202c0 {
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reg = <0x01c202c0 0xc>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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#reset-cells = <1>;
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};
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apb1_reset: reset@01c202d0 {
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reg = <0x01c202d0 0x4>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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#reset-cells = <1>;
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};
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apb2_reset: reset@01c202d8 {
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reg = <0x01c202d8 0x4>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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#reset-cells = <1>;
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};
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timer@01c20c00 {
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compatible = "allwinner,sun4i-a10-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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watchdog@01c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&bus_gates 112>;
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resets = <&apb2_reset 16>;
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status = "disabled";
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};
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x1000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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apb0_reset: reset@01f014b0 {
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reg = <0x01f014b0 0x4>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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#reset-cells = <1>;
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};
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r_pio: pinctrl@01f02c00 {
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compatible = "allwinner,sun8i-a83t-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 0>;
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resets = <&apb0_reset 0>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
|
|
|
|
r_rsb_pins: r_rsb {
|
|
allwinner,pins = "PL0", "PL1";
|
|
allwinner,function = "s_rsb";
|
|
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
};
|
|
|
|
r_rsb: i2c@01f03400 {
|
|
compatible = "allwinner,sun8i-a23-rsb";
|
|
reg = <0x01f03400 0x400>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 3>;
|
|
clock-frequency = <3000000>;
|
|
resets = <&apb0_reset 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_rsb_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|