806 lines
25 KiB
C
806 lines
25 KiB
C
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/*******************************************************************************
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*
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* Module Name: hwregs - Read/write access functions for the various ACPI
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* control and status registers.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* 1. Copyright Notice
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*
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* Some or all of this work - Copyright (c) 1999 - 2009, Intel Corp.
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* All rights reserved.
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*
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* 2. License
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*
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* 2.1. This is your license from Intel Corp. under its intellectual property
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* rights. You may have additional license terms from the party that provided
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* you this software, covering your right to use that party's intellectual
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* property rights.
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*
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* 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
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* copy of the source code appearing in this file ("Covered Code") an
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* irrevocable, perpetual, worldwide license under Intel's copyrights in the
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* base code distributed originally by Intel ("Original Intel Code") to copy,
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* make derivatives, distribute, use and display any portion of the Covered
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* Code in any form, with the right to sublicense such rights; and
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*
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* 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
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* license (with the right to sublicense), under only those claims of Intel
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* patents that are infringed by the Original Intel Code, to make, use, sell,
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* offer to sell, and import the Covered Code and derivative works thereof
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* solely to the minimum extent necessary to exercise the above copyright
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* license, and in no event shall the patent license extend to any additions
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* to or modifications of the Original Intel Code. No other license or right
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* is granted directly or by implication, estoppel or otherwise;
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*
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* The above copyright and patent license is granted only if the following
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* conditions are met:
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*
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* 3. Conditions
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*
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* 3.1. Redistribution of Source with Rights to Further Distribute Source.
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* Redistribution of source code of any substantial portion of the Covered
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* Code or modification with rights to further distribute source must include
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* the above Copyright Notice, the above License, this list of Conditions,
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* and the following Disclaimer and Export Compliance provision. In addition,
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* Licensee must cause all Covered Code to which Licensee contributes to
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* contain a file documenting the changes Licensee made to create that Covered
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* Code and the date of any change. Licensee must include in that file the
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* documentation of any changes made by any predecessor Licensee. Licensee
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* must include a prominent statement that the modification is derived,
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* directly or indirectly, from Original Intel Code.
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*
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* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
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* Redistribution of source code of any substantial portion of the Covered
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* Code or modification without rights to further distribute source must
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* include the following Disclaimer and Export Compliance provision in the
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* documentation and/or other materials provided with distribution. In
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* addition, Licensee may not authorize further sublicense of source of any
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* portion of the Covered Code, and must include terms to the effect that the
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* license from Licensee to its licensee is limited to the intellectual
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* property embodied in the software Licensee provides to its licensee, and
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* not to intellectual property embodied in modifications its licensee may
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* make.
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*
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* 3.3. Redistribution of Executable. Redistribution in executable form of any
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* substantial portion of the Covered Code or modification must reproduce the
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* above Copyright Notice, and the following Disclaimer and Export Compliance
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* provision in the documentation and/or other materials provided with the
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* distribution.
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*
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* 3.4. Intel retains all right, title, and interest in and to the Original
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* Intel Code.
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*
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* 3.5. Neither the name Intel nor any other trademark owned or controlled by
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* Intel shall be used in advertising or otherwise to promote the sale, use or
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* other dealings in products derived from or relating to the Covered Code
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* without prior written authorization from Intel.
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*
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* 4. Disclaimer and Export Compliance
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*
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* 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
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* HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
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* IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
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* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
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* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
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* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
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* PARTICULAR PURPOSE.
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*
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* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
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* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
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* COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
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* SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
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* CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
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* HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
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* SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
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* LIMITED REMEDY.
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*
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* 4.3. Licensee shall not export, either directly or indirectly, any of this
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* software or system incorporating such software without first obtaining any
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* required license or other approval from the U. S. Department of Commerce or
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* any other agency or department of the United States Government. In the
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* event Licensee exports any such software from the United States or
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* re-exports any such software from a foreign destination, Licensee shall
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* ensure that the distribution and export/re-export of the software is in
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* compliance with all laws, regulations, orders, or other restrictions of the
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* U.S. Export Administration Regulations. Licensee agrees that neither it nor
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* any of its subsidiaries will export/re-export any technical data, process,
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* software, or service, directly or indirectly, to any country for which the
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* United States government or any agency thereof requires an export license,
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* other governmental approval, or letter of assurance, without first obtaining
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* such license, approval or letter.
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*
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*****************************************************************************/
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#define __HWREGS_C__
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#include <contrib/dev/acpica/include/acpi.h>
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#include <contrib/dev/acpica/include/accommon.h>
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#include <contrib/dev/acpica/include/acevents.h>
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#define _COMPONENT ACPI_HARDWARE
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ACPI_MODULE_NAME ("hwregs")
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/* Local Prototypes */
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static ACPI_STATUS
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AcpiHwReadMultiple (
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UINT32 *Value,
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ACPI_GENERIC_ADDRESS *RegisterA,
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ACPI_GENERIC_ADDRESS *RegisterB);
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static ACPI_STATUS
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AcpiHwWriteMultiple (
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UINT32 Value,
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ACPI_GENERIC_ADDRESS *RegisterA,
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ACPI_GENERIC_ADDRESS *RegisterB);
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/******************************************************************************
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*
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* FUNCTION: AcpiHwValidateRegister
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*
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* PARAMETERS: Reg - GAS register structure
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* MaxBitWidth - Max BitWidth supported (32 or 64)
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* Address - Pointer to where the gas->address
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* is returned
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*
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* RETURN: Status
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*
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* DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
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* pointer, Address, SpaceId, BitWidth, and BitOffset.
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*
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******************************************************************************/
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ACPI_STATUS
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AcpiHwValidateRegister (
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ACPI_GENERIC_ADDRESS *Reg,
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UINT8 MaxBitWidth,
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UINT64 *Address)
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{
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/* Must have a valid pointer to a GAS structure */
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if (!Reg)
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{
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return (AE_BAD_PARAMETER);
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}
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/*
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* Copy the target address. This handles possible alignment issues.
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* Address must not be null. A null address also indicates an optional
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* ACPI register that is not supported, so no error message.
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*/
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ACPI_MOVE_64_TO_64 (Address, &Reg->Address);
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if (!(*Address))
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{
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return (AE_BAD_ADDRESS);
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}
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/* Validate the SpaceID */
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if ((Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
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(Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_IO))
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{
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ACPI_ERROR ((AE_INFO,
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"Unsupported address space: 0x%X", Reg->SpaceId));
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return (AE_SUPPORT);
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}
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/* Validate the BitWidth */
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if ((Reg->BitWidth != 8) &&
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(Reg->BitWidth != 16) &&
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(Reg->BitWidth != 32) &&
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(Reg->BitWidth != MaxBitWidth))
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{
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ACPI_ERROR ((AE_INFO,
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"Unsupported register bit width: 0x%X", Reg->BitWidth));
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return (AE_SUPPORT);
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}
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/* Validate the BitOffset. Just a warning for now. */
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if (Reg->BitOffset != 0)
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{
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ACPI_WARNING ((AE_INFO,
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"Unsupported register bit offset: 0x%X", Reg->BitOffset));
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}
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return (AE_OK);
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}
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/******************************************************************************
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*
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* FUNCTION: AcpiHwRead
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*
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* PARAMETERS: Value - Where the value is returned
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* Reg - GAS register structure
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*
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* RETURN: Status
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*
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* DESCRIPTION: Read from either memory or IO space. This is a 32-bit max
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* version of AcpiRead, used internally since the overhead of
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* 64-bit values is not needed.
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*
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* LIMITATIONS: <These limitations also apply to AcpiHwWrite>
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* BitWidth must be exactly 8, 16, or 32.
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* SpaceID must be SystemMemory or SystemIO.
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* BitOffset and AccessWidth are currently ignored, as there has
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* not been a need to implement these.
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*
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******************************************************************************/
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ACPI_STATUS
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AcpiHwRead (
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UINT32 *Value,
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ACPI_GENERIC_ADDRESS *Reg)
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{
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UINT64 Address;
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ACPI_STATUS Status;
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ACPI_FUNCTION_NAME (HwRead);
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/* Validate contents of the GAS register */
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Status = AcpiHwValidateRegister (Reg, 32, &Address);
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if (ACPI_FAILURE (Status))
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{
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return (Status);
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}
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/* Initialize entire 32-bit return value to zero */
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*Value = 0;
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/*
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* Two address spaces supported: Memory or IO. PCI_Config is
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* not supported here because the GAS structure is insufficient
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*/
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if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY)
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{
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Status = AcpiOsReadMemory ((ACPI_PHYSICAL_ADDRESS)
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Address, Value, Reg->BitWidth);
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}
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else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
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{
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Status = AcpiHwReadPort ((ACPI_IO_ADDRESS)
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Address, Value, Reg->BitWidth);
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}
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ACPI_DEBUG_PRINT ((ACPI_DB_IO,
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"Read: %8.8X width %2d from %8.8X%8.8X (%s)\n",
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*Value, Reg->BitWidth, ACPI_FORMAT_UINT64 (Address),
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AcpiUtGetRegionName (Reg->SpaceId)));
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return (Status);
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}
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/******************************************************************************
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*
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* FUNCTION: AcpiHwWrite
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*
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* PARAMETERS: Value - Value to be written
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* Reg - GAS register structure
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*
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* RETURN: Status
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*
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* DESCRIPTION: Write to either memory or IO space. This is a 32-bit max
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* version of AcpiWrite, used internally since the overhead of
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* 64-bit values is not needed.
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*
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******************************************************************************/
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ACPI_STATUS
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AcpiHwWrite (
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UINT32 Value,
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ACPI_GENERIC_ADDRESS *Reg)
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{
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UINT64 Address;
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ACPI_STATUS Status;
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ACPI_FUNCTION_NAME (HwWrite);
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/* Validate contents of the GAS register */
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Status = AcpiHwValidateRegister (Reg, 32, &Address);
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if (ACPI_FAILURE (Status))
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{
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return (Status);
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}
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/*
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* Two address spaces supported: Memory or IO. PCI_Config is
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* not supported here because the GAS structure is insufficient
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*/
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if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY)
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{
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Status = AcpiOsWriteMemory ((ACPI_PHYSICAL_ADDRESS)
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Address, Value, Reg->BitWidth);
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}
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else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
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{
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Status = AcpiHwWritePort ((ACPI_IO_ADDRESS)
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Address, Value, Reg->BitWidth);
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}
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ACPI_DEBUG_PRINT ((ACPI_DB_IO,
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"Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
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Value, Reg->BitWidth, ACPI_FORMAT_UINT64 (Address),
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AcpiUtGetRegionName (Reg->SpaceId)));
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return (Status);
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}
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/*******************************************************************************
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*
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* FUNCTION: AcpiHwClearAcpiStatus
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*
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* PARAMETERS: None
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*
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* RETURN: Status
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*
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* DESCRIPTION: Clears all fixed and general purpose status bits
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*
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******************************************************************************/
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ACPI_STATUS
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AcpiHwClearAcpiStatus (
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void)
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{
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ACPI_STATUS Status;
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ACPI_CPU_FLAGS LockFlags = 0;
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ACPI_FUNCTION_TRACE (HwClearAcpiStatus);
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ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
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ACPI_BITMASK_ALL_FIXED_STATUS,
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ACPI_FORMAT_UINT64 (AcpiGbl_XPm1aStatus.Address)));
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LockFlags = AcpiOsAcquireLock (AcpiGbl_HardwareLock);
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/* Clear the fixed events in PM1 A/B */
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Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_STATUS,
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ACPI_BITMASK_ALL_FIXED_STATUS);
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if (ACPI_FAILURE (Status))
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{
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goto UnlockAndExit;
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}
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/* Clear the GPE Bits in all GPE registers in all GPE blocks */
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Status = AcpiEvWalkGpeList (AcpiHwClearGpeBlock, NULL);
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UnlockAndExit:
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AcpiOsReleaseLock (AcpiGbl_HardwareLock, LockFlags);
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return_ACPI_STATUS (Status);
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}
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/*******************************************************************************
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*
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* FUNCTION: AcpiHwGetRegisterBitMask
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*
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* PARAMETERS: RegisterId - Index of ACPI Register to access
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*
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* RETURN: The bitmask to be used when accessing the register
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*
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* DESCRIPTION: Map RegisterId into a register bitmask.
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*
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******************************************************************************/
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ACPI_BIT_REGISTER_INFO *
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AcpiHwGetBitRegisterInfo (
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UINT32 RegisterId)
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{
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ACPI_FUNCTION_ENTRY ();
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if (RegisterId > ACPI_BITREG_MAX)
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{
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ACPI_ERROR ((AE_INFO, "Invalid BitRegister ID: %X", RegisterId));
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return (NULL);
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}
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return (&AcpiGbl_BitRegisterInfo[RegisterId]);
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}
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/******************************************************************************
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*
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* FUNCTION: AcpiHwWritePm1Control
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*
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* PARAMETERS: Pm1aControl - Value to be written to PM1A control
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* Pm1bControl - Value to be written to PM1B control
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*
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* RETURN: Status
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*
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* DESCRIPTION: Write the PM1 A/B control registers. These registers are
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* different than than the PM1 A/B status and enable registers
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* in that different values can be written to the A/B registers.
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* Most notably, the SLP_TYP bits can be different, as per the
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* values returned from the _Sx predefined methods.
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*
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******************************************************************************/
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ACPI_STATUS
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AcpiHwWritePm1Control (
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UINT32 Pm1aControl,
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UINT32 Pm1bControl)
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{
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ACPI_STATUS Status;
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ACPI_FUNCTION_TRACE (HwWritePm1Control);
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Status = AcpiHwWrite (Pm1aControl, &AcpiGbl_FADT.XPm1aControlBlock);
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if (ACPI_FAILURE (Status))
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{
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return_ACPI_STATUS (Status);
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}
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if (AcpiGbl_FADT.XPm1bControlBlock.Address)
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{
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Status = AcpiHwWrite (Pm1bControl, &AcpiGbl_FADT.XPm1bControlBlock);
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}
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return_ACPI_STATUS (Status);
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}
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/******************************************************************************
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*
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* FUNCTION: AcpiHwRegisterRead
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*
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* PARAMETERS: RegisterId - ACPI Register ID
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* ReturnValue - Where the register value is returned
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*
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* RETURN: Status and the value read.
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*
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* DESCRIPTION: Read from the specified ACPI register
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*
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******************************************************************************/
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ACPI_STATUS
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AcpiHwRegisterRead (
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UINT32 RegisterId,
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UINT32 *ReturnValue)
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{
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UINT32 Value = 0;
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ACPI_STATUS Status;
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ACPI_FUNCTION_TRACE (HwRegisterRead);
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switch (RegisterId)
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{
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case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
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Status = AcpiHwReadMultiple (&Value,
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&AcpiGbl_XPm1aStatus,
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&AcpiGbl_XPm1bStatus);
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break;
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case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
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Status = AcpiHwReadMultiple (&Value,
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&AcpiGbl_XPm1aEnable,
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&AcpiGbl_XPm1bEnable);
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break;
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case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
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Status = AcpiHwReadMultiple (&Value,
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&AcpiGbl_FADT.XPm1aControlBlock,
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&AcpiGbl_FADT.XPm1bControlBlock);
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/*
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* Zero the write-only bits. From the ACPI specification, "Hardware
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* Write-Only Bits": "Upon reads to registers with write-only bits,
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* software masks out all write-only bits."
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*/
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Value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
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break;
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case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
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Status = AcpiHwRead (&Value, &AcpiGbl_FADT.XPm2ControlBlock);
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break;
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case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
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Status = AcpiHwRead (&Value, &AcpiGbl_FADT.XPmTimerBlock);
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break;
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case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
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Status = AcpiHwReadPort (AcpiGbl_FADT.SmiCommand, &Value, 8);
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break;
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|
|
|
|
|
default:
|
|
ACPI_ERROR ((AE_INFO, "Unknown Register ID: %X",
|
|
RegisterId));
|
|
Status = AE_BAD_PARAMETER;
|
|
break;
|
|
}
|
|
|
|
if (ACPI_SUCCESS (Status))
|
|
{
|
|
*ReturnValue = Value;
|
|
}
|
|
|
|
return_ACPI_STATUS (Status);
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: AcpiHwRegisterWrite
|
|
*
|
|
* PARAMETERS: RegisterId - ACPI Register ID
|
|
* Value - The value to write
|
|
*
|
|
* RETURN: Status
|
|
*
|
|
* DESCRIPTION: Write to the specified ACPI register
|
|
*
|
|
* NOTE: In accordance with the ACPI specification, this function automatically
|
|
* preserves the value of the following bits, meaning that these bits cannot be
|
|
* changed via this interface:
|
|
*
|
|
* PM1_CONTROL[0] = SCI_EN
|
|
* PM1_CONTROL[9]
|
|
* PM1_STATUS[11]
|
|
*
|
|
* ACPI References:
|
|
* 1) Hardware Ignored Bits: When software writes to a register with ignored
|
|
* bit fields, it preserves the ignored bit fields
|
|
* 2) SCI_EN: OSPM always preserves this bit position
|
|
*
|
|
******************************************************************************/
|
|
|
|
ACPI_STATUS
|
|
AcpiHwRegisterWrite (
|
|
UINT32 RegisterId,
|
|
UINT32 Value)
|
|
{
|
|
ACPI_STATUS Status;
|
|
UINT32 ReadValue;
|
|
|
|
|
|
ACPI_FUNCTION_TRACE (HwRegisterWrite);
|
|
|
|
|
|
switch (RegisterId)
|
|
{
|
|
case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
|
|
/*
|
|
* Handle the "ignored" bit in PM1 Status. According to the ACPI
|
|
* specification, ignored bits are to be preserved when writing.
|
|
* Normally, this would mean a read/modify/write sequence. However,
|
|
* preserving a bit in the status register is different. Writing a
|
|
* one clears the status, and writing a zero preserves the status.
|
|
* Therefore, we must always write zero to the ignored bit.
|
|
*
|
|
* This behavior is clarified in the ACPI 4.0 specification.
|
|
*/
|
|
Value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
|
|
|
|
Status = AcpiHwWriteMultiple (Value,
|
|
&AcpiGbl_XPm1aStatus,
|
|
&AcpiGbl_XPm1bStatus);
|
|
break;
|
|
|
|
|
|
case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
|
|
|
|
Status = AcpiHwWriteMultiple (Value,
|
|
&AcpiGbl_XPm1aEnable,
|
|
&AcpiGbl_XPm1bEnable);
|
|
break;
|
|
|
|
|
|
case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
|
|
|
|
/*
|
|
* Perform a read first to preserve certain bits (per ACPI spec)
|
|
* Note: This includes SCI_EN, we never want to change this bit
|
|
*/
|
|
Status = AcpiHwReadMultiple (&ReadValue,
|
|
&AcpiGbl_FADT.XPm1aControlBlock,
|
|
&AcpiGbl_FADT.XPm1bControlBlock);
|
|
if (ACPI_FAILURE (Status))
|
|
{
|
|
goto Exit;
|
|
}
|
|
|
|
/* Insert the bits to be preserved */
|
|
|
|
ACPI_INSERT_BITS (Value, ACPI_PM1_CONTROL_PRESERVED_BITS, ReadValue);
|
|
|
|
/* Now we can write the data */
|
|
|
|
Status = AcpiHwWriteMultiple (Value,
|
|
&AcpiGbl_FADT.XPm1aControlBlock,
|
|
&AcpiGbl_FADT.XPm1bControlBlock);
|
|
break;
|
|
|
|
|
|
case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
|
|
|
|
/*
|
|
* For control registers, all reserved bits must be preserved,
|
|
* as per the ACPI spec.
|
|
*/
|
|
Status = AcpiHwRead (&ReadValue, &AcpiGbl_FADT.XPm2ControlBlock);
|
|
if (ACPI_FAILURE (Status))
|
|
{
|
|
goto Exit;
|
|
}
|
|
|
|
/* Insert the bits to be preserved */
|
|
|
|
ACPI_INSERT_BITS (Value, ACPI_PM2_CONTROL_PRESERVED_BITS, ReadValue);
|
|
|
|
Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPm2ControlBlock);
|
|
break;
|
|
|
|
|
|
case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
|
|
|
|
Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPmTimerBlock);
|
|
break;
|
|
|
|
|
|
case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
|
|
|
|
/* SMI_CMD is currently always in IO space */
|
|
|
|
Status = AcpiHwWritePort (AcpiGbl_FADT.SmiCommand, Value, 8);
|
|
break;
|
|
|
|
|
|
default:
|
|
ACPI_ERROR ((AE_INFO, "Unknown Register ID: %X",
|
|
RegisterId));
|
|
Status = AE_BAD_PARAMETER;
|
|
break;
|
|
}
|
|
|
|
Exit:
|
|
return_ACPI_STATUS (Status);
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: AcpiHwReadMultiple
|
|
*
|
|
* PARAMETERS: Value - Where the register value is returned
|
|
* RegisterA - First ACPI register (required)
|
|
* RegisterB - Second ACPI register (optional)
|
|
*
|
|
* RETURN: Status
|
|
*
|
|
* DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
|
|
*
|
|
******************************************************************************/
|
|
|
|
static ACPI_STATUS
|
|
AcpiHwReadMultiple (
|
|
UINT32 *Value,
|
|
ACPI_GENERIC_ADDRESS *RegisterA,
|
|
ACPI_GENERIC_ADDRESS *RegisterB)
|
|
{
|
|
UINT32 ValueA = 0;
|
|
UINT32 ValueB = 0;
|
|
ACPI_STATUS Status;
|
|
|
|
|
|
/* The first register is always required */
|
|
|
|
Status = AcpiHwRead (&ValueA, RegisterA);
|
|
if (ACPI_FAILURE (Status))
|
|
{
|
|
return (Status);
|
|
}
|
|
|
|
/* Second register is optional */
|
|
|
|
if (RegisterB->Address)
|
|
{
|
|
Status = AcpiHwRead (&ValueB, RegisterB);
|
|
if (ACPI_FAILURE (Status))
|
|
{
|
|
return (Status);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* OR the two return values together. No shifting or masking is necessary,
|
|
* because of how the PM1 registers are defined in the ACPI specification:
|
|
*
|
|
* "Although the bits can be split between the two register blocks (each
|
|
* register block has a unique pointer within the FADT), the bit positions
|
|
* are maintained. The register block with unimplemented bits (that is,
|
|
* those implemented in the other register block) always returns zeros,
|
|
* and writes have no side effects"
|
|
*/
|
|
*Value = (ValueA | ValueB);
|
|
return (AE_OK);
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: AcpiHwWriteMultiple
|
|
*
|
|
* PARAMETERS: Value - The value to write
|
|
* RegisterA - First ACPI register (required)
|
|
* RegisterB - Second ACPI register (optional)
|
|
*
|
|
* RETURN: Status
|
|
*
|
|
* DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
|
|
*
|
|
******************************************************************************/
|
|
|
|
static ACPI_STATUS
|
|
AcpiHwWriteMultiple (
|
|
UINT32 Value,
|
|
ACPI_GENERIC_ADDRESS *RegisterA,
|
|
ACPI_GENERIC_ADDRESS *RegisterB)
|
|
{
|
|
ACPI_STATUS Status;
|
|
|
|
|
|
/* The first register is always required */
|
|
|
|
Status = AcpiHwWrite (Value, RegisterA);
|
|
if (ACPI_FAILURE (Status))
|
|
{
|
|
return (Status);
|
|
}
|
|
|
|
/*
|
|
* Second register is optional
|
|
*
|
|
* No bit shifting or clearing is necessary, because of how the PM1
|
|
* registers are defined in the ACPI specification:
|
|
*
|
|
* "Although the bits can be split between the two register blocks (each
|
|
* register block has a unique pointer within the FADT), the bit positions
|
|
* are maintained. The register block with unimplemented bits (that is,
|
|
* those implemented in the other register block) always returns zeros,
|
|
* and writes have no side effects"
|
|
*/
|
|
if (RegisterB->Address)
|
|
{
|
|
Status = AcpiHwWrite (Value, RegisterB);
|
|
}
|
|
|
|
return (Status);
|
|
}
|
|
|