685 lines
25 KiB
C++
685 lines
25 KiB
C++
//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate information gleaned from the
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// target register and register class definitions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_REGISTERS_H
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#define CODEGEN_REGISTERS_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/SetTheory.h"
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#include <cstdlib>
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#include <map>
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#include <set>
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#include <string>
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#include <vector>
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namespace llvm {
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class CodeGenRegBank;
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/// CodeGenSubRegIndex - Represents a sub-register index.
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class CodeGenSubRegIndex {
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Record *const TheDef;
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std::string Name;
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std::string Namespace;
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public:
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uint16_t Size;
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uint16_t Offset;
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const unsigned EnumValue;
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unsigned LaneMask;
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// Are all super-registers containing this SubRegIndex covered by their
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// sub-registers?
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bool AllSuperRegsCovered;
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CodeGenSubRegIndex(Record *R, unsigned Enum);
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CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
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const std::string &getName() const { return Name; }
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const std::string &getNamespace() const { return Namespace; }
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std::string getQualifiedName() const;
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// Order CodeGenSubRegIndex pointers by EnumValue.
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struct Less {
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bool operator()(const CodeGenSubRegIndex *A,
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const CodeGenSubRegIndex *B) const {
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assert(A && B);
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return A->EnumValue < B->EnumValue;
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}
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};
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// Map of composite subreg indices.
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typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
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// Returns the subreg index that results from composing this with Idx.
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// Returns NULL if this and Idx don't compose.
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CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
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CompMap::const_iterator I = Composed.find(Idx);
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return I == Composed.end() ? nullptr : I->second;
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}
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// Add a composite subreg index: this+A = B.
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// Return a conflicting composite, or NULL
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CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
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CodeGenSubRegIndex *B) {
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assert(A && B);
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std::pair<CompMap::iterator, bool> Ins =
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Composed.insert(std::make_pair(A, B));
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// Synthetic subreg indices that aren't contiguous (for instance ARM
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// register tuples) don't have a bit range, so it's OK to let
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// B->Offset == -1. For the other cases, accumulate the offset and set
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// the size here. Only do so if there is no offset yet though.
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if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
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(B->Offset == (uint16_t)-1)) {
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B->Offset = Offset + A->Offset;
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B->Size = A->Size;
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}
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return (Ins.second || Ins.first->second == B) ? nullptr
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: Ins.first->second;
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}
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// Update the composite maps of components specified in 'ComposedOf'.
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void updateComponents(CodeGenRegBank&);
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// Return the map of composites.
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const CompMap &getComposites() const { return Composed; }
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// Compute LaneMask from Composed. Return LaneMask.
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unsigned computeLaneMask();
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private:
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CompMap Composed;
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};
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/// CodeGenRegister - Represents a register definition.
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struct CodeGenRegister {
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Record *TheDef;
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unsigned EnumValue;
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unsigned CostPerUse;
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bool CoveredBySubRegs;
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// Map SubRegIndex -> Register.
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typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
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CodeGenSubRegIndex::Less> SubRegMap;
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CodeGenRegister(Record *R, unsigned Enum);
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const std::string &getName() const;
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// Extract more information from TheDef. This is used to build an object
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// graph after all CodeGenRegister objects have been created.
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void buildObjectGraph(CodeGenRegBank&);
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// Lazily compute a map of all sub-registers.
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// This includes unique entries for all sub-sub-registers.
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const SubRegMap &computeSubRegs(CodeGenRegBank&);
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// Compute extra sub-registers by combining the existing sub-registers.
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void computeSecondarySubRegs(CodeGenRegBank&);
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// Add this as a super-register to all sub-registers after the sub-register
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// graph has been built.
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void computeSuperRegs(CodeGenRegBank&);
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const SubRegMap &getSubRegs() const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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return SubRegs;
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}
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// Add sub-registers to OSet following a pre-order defined by the .td file.
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void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
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CodeGenRegBank&) const;
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// Return the sub-register index naming Reg as a sub-register of this
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// register. Returns NULL if Reg is not a sub-register.
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CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
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return SubReg2Idx.lookup(Reg);
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}
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typedef std::vector<const CodeGenRegister*> SuperRegList;
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// Get the list of super-registers in topological order, small to large.
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// This is valid after computeSubRegs visits all registers during RegBank
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// construction.
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const SuperRegList &getSuperRegs() const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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return SuperRegs;
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}
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// Get the list of ad hoc aliases. The graph is symmetric, so the list
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// contains all registers in 'Aliases', and all registers that mention this
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// register in 'Aliases'.
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ArrayRef<CodeGenRegister*> getExplicitAliases() const {
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return ExplicitAliases;
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}
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// Get the topological signature of this register. This is a small integer
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// less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
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// identical sub-register structure. That is, they support the same set of
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// sub-register indices mapping to the same kind of sub-registers
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// (TopoSig-wise).
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unsigned getTopoSig() const {
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assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
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return TopoSig;
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}
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// List of register units in ascending order.
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typedef SmallVector<unsigned, 16> RegUnitList;
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// How many entries in RegUnitList are native?
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unsigned NumNativeRegUnits;
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// Get the list of register units.
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// This is only valid after computeSubRegs() completes.
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const RegUnitList &getRegUnits() const { return RegUnits; }
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// Get the native register units. This is a prefix of getRegUnits().
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ArrayRef<unsigned> getNativeRegUnits() const {
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return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
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}
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// Inherit register units from subregisters.
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// Return true if the RegUnits changed.
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bool inheritRegUnits(CodeGenRegBank &RegBank);
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// Adopt a register unit for pressure tracking.
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// A unit is adopted iff its unit number is >= NumNativeRegUnits.
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void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
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// Get the sum of this register's register unit weights.
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unsigned getWeight(const CodeGenRegBank &RegBank) const;
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// Order CodeGenRegister pointers by EnumValue.
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struct Less {
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bool operator()(const CodeGenRegister *A,
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const CodeGenRegister *B) const {
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assert(A && B);
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return A->EnumValue < B->EnumValue;
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}
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};
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// Canonically ordered set.
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typedef std::set<const CodeGenRegister*, Less> Set;
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private:
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bool SubRegsComplete;
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bool SuperRegsComplete;
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unsigned TopoSig;
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// The sub-registers explicit in the .td file form a tree.
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SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
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SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
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// Explicit ad hoc aliases, symmetrized to form an undirected graph.
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SmallVector<CodeGenRegister*, 8> ExplicitAliases;
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// Super-registers where this is the first explicit sub-register.
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SuperRegList LeadingSuperRegs;
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SubRegMap SubRegs;
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SuperRegList SuperRegs;
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DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
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RegUnitList RegUnits;
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};
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class CodeGenRegisterClass {
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CodeGenRegister::Set Members;
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// Allocation orders. Order[0] always contains all registers in Members.
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std::vector<SmallVector<Record*, 16> > Orders;
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// Bit mask of sub-classes including this, indexed by their EnumValue.
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BitVector SubClasses;
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// List of super-classes, topologocally ordered to have the larger classes
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// first. This is the same as sorting by EnumValue.
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SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
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Record *TheDef;
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std::string Name;
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// For a synthesized class, inherit missing properties from the nearest
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// super-class.
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void inheritProperties(CodeGenRegBank&);
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// Map SubRegIndex -> sub-class. This is the largest sub-class where all
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// registers have a SubRegIndex sub-register.
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DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
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// Map SubRegIndex -> set of super-reg classes. This is all register
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// classes SuperRC such that:
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//
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// R:SubRegIndex in this RC for all R in SuperRC.
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//
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DenseMap<CodeGenSubRegIndex*,
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SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
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// Bit vector of TopoSigs for the registers in this class. This will be
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// very sparse on regular architectures.
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BitVector TopoSigs;
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public:
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unsigned EnumValue;
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std::string Namespace;
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SmallVector<MVT::SimpleValueType, 4> VTs;
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unsigned SpillSize;
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unsigned SpillAlignment;
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int CopyCost;
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bool Allocatable;
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std::string AltOrderSelect;
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// Return the Record that defined this class, or NULL if the class was
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// created by TableGen.
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Record *getDef() const { return TheDef; }
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const std::string &getName() const { return Name; }
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std::string getQualifiedName() const;
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ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
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unsigned getNumValueTypes() const { return VTs.size(); }
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MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
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if (VTNum < VTs.size())
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return VTs[VTNum];
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llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
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}
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// Return true if this this class contains the register.
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bool contains(const CodeGenRegister*) const;
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// Returns true if RC is a subclass.
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// RC is a sub-class of this class if it is a valid replacement for any
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// instruction operand where a register of this classis required. It must
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// satisfy these conditions:
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//
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// 1. All RC registers are also in this.
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// 2. The RC spill size must not be smaller than our spill size.
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// 3. RC spill alignment must be compatible with ours.
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//
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bool hasSubClass(const CodeGenRegisterClass *RC) const {
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return SubClasses.test(RC->EnumValue);
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}
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// getSubClassWithSubReg - Returns the largest sub-class where all
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// registers have a SubIdx sub-register.
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CodeGenRegisterClass*
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getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
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return SubClassWithSubReg.lookup(SubIdx);
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}
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void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
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CodeGenRegisterClass *SubRC) {
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SubClassWithSubReg[SubIdx] = SubRC;
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}
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// getSuperRegClasses - Returns a bit vector of all register classes
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// containing only SubIdx super-registers of this class.
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void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
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// addSuperRegClass - Add a class containing only SudIdx super-registers.
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void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
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CodeGenRegisterClass *SuperRC) {
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SuperRegClasses[SubIdx].insert(SuperRC);
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}
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// getSubClasses - Returns a constant BitVector of subclasses indexed by
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// EnumValue.
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// The SubClasses vector includes an entry for this class.
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const BitVector &getSubClasses() const { return SubClasses; }
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// getSuperClasses - Returns a list of super classes ordered by EnumValue.
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// The array does not include an entry for this class.
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ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
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return SuperClasses;
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}
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// Returns an ordered list of class members.
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// The order of registers is the same as in the .td file.
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// No = 0 is the default allocation order, No = 1 is the first alternative.
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ArrayRef<Record*> getOrder(unsigned No = 0) const {
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return Orders[No];
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}
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// Return the total number of allocation orders available.
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unsigned getNumOrders() const { return Orders.size(); }
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// Get the set of registers. This set contains the same registers as
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// getOrder(0).
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const CodeGenRegister::Set &getMembers() const { return Members; }
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// Get a bit vector of TopoSigs present in this register class.
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const BitVector &getTopoSigs() const { return TopoSigs; }
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// Populate a unique sorted list of units from a register set.
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void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
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CodeGenRegisterClass(CodeGenRegBank&, Record *R);
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// A key representing the parts of a register class used for forming
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// sub-classes. Note the ordering provided by this key is not the same as
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// the topological order used for the EnumValues.
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struct Key {
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const CodeGenRegister::Set *Members;
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unsigned SpillSize;
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unsigned SpillAlignment;
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Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
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: Members(M), SpillSize(S), SpillAlignment(A) {}
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Key(const CodeGenRegisterClass &RC)
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: Members(&RC.getMembers()),
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SpillSize(RC.SpillSize),
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SpillAlignment(RC.SpillAlignment) {}
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// Lexicographical order of (Members, SpillSize, SpillAlignment).
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bool operator<(const Key&) const;
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};
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// Create a non-user defined register class.
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CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
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// Called by CodeGenRegBank::CodeGenRegBank().
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static void computeSubClasses(CodeGenRegBank&);
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};
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// Register units are used to model interference and register pressure.
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// Every register is assigned one or more register units such that two
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// registers overlap if and only if they have a register unit in common.
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//
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// Normally, one register unit is created per leaf register. Non-leaf
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// registers inherit the units of their sub-registers.
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struct RegUnit {
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// Weight assigned to this RegUnit for estimating register pressure.
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// This is useful when equalizing weights in register classes with mixed
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// register topologies.
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unsigned Weight;
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// Each native RegUnit corresponds to one or two root registers. The full
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// set of registers containing this unit can be computed as the union of
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// these two registers and their super-registers.
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const CodeGenRegister *Roots[2];
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// Index into RegClassUnitSets where we can find the list of UnitSets that
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// contain this unit.
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unsigned RegClassUnitSetsIdx;
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RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
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Roots[0] = Roots[1] = nullptr;
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}
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ArrayRef<const CodeGenRegister*> getRoots() const {
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assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
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return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
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}
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};
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// Each RegUnitSet is a sorted vector with a name.
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struct RegUnitSet {
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typedef std::vector<unsigned>::const_iterator iterator;
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std::string Name;
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std::vector<unsigned> Units;
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unsigned Weight; // Cache the sum of all unit weights.
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unsigned Order; // Cache the sort key.
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RegUnitSet() : Weight(0), Order(0) {}
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};
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// Base vector for identifying TopoSigs. The contents uniquely identify a
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// TopoSig, only computeSuperRegs needs to know how.
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typedef SmallVector<unsigned, 16> TopoSigId;
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// CodeGenRegBank - Represent a target's registers and the relations between
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// them.
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class CodeGenRegBank {
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SetTheory Sets;
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// SubRegIndices.
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std::vector<CodeGenSubRegIndex*> SubRegIndices;
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DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
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CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
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typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
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CodeGenSubRegIndex*> ConcatIdxMap;
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ConcatIdxMap ConcatIdx;
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// Registers.
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std::vector<CodeGenRegister*> Registers;
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StringMap<CodeGenRegister*> RegistersByName;
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DenseMap<Record*, CodeGenRegister*> Def2Reg;
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unsigned NumNativeRegUnits;
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std::map<TopoSigId, unsigned> TopoSigs;
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// Includes native (0..NumNativeRegUnits-1) and adopted register units.
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SmallVector<RegUnit, 8> RegUnits;
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// Register classes.
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std::vector<CodeGenRegisterClass*> RegClasses;
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DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
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typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
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RCKeyMap Key2RC;
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// Remember each unique set of register units. Initially, this contains a
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// unique set for each register class. Simliar sets are coalesced with
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// pruneUnitSets and new supersets are inferred during computeRegUnitSets.
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std::vector<RegUnitSet> RegUnitSets;
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// Map RegisterClass index to the index of the RegUnitSet that contains the
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// class's units and any inferred RegUnit supersets.
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//
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// NOTE: This could grow beyond the number of register classes when we map
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// register units to lists of unit sets. If the list of unit sets does not
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// already exist for a register class, we create a new entry in this vector.
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std::vector<std::vector<unsigned> > RegClassUnitSets;
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// Give each register unit set an order based on sorting criteria.
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std::vector<unsigned> RegUnitSetOrder;
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// Add RC to *2RC maps.
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void addToMaps(CodeGenRegisterClass*);
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// Create a synthetic sub-class if it is missing.
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CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
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const CodeGenRegister::Set *Membs,
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StringRef Name);
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// Infer missing register classes.
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void computeInferredRegisterClasses();
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void inferCommonSubClass(CodeGenRegisterClass *RC);
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void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
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void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
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unsigned FirstSubRegRC = 0);
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// Iteratively prune unit sets.
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void pruneUnitSets();
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// Compute a weight for each register unit created during getSubRegs.
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void computeRegUnitWeights();
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// Create a RegUnitSet for each RegClass and infer superclasses.
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void computeRegUnitSets();
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// Populate the Composite map from sub-register relationships.
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void computeComposites();
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// Compute a lane mask for each sub-register index.
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void computeSubRegIndexLaneMasks();
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public:
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CodeGenRegBank(RecordKeeper&);
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SetTheory &getSets() { return Sets; }
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// Sub-register indices. The first NumNamedIndices are defined by the user
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// in the .td files. The rest are synthesized such that all sub-registers
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// have a unique name.
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ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
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// Find a SubRegIndex form its Record def.
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CodeGenSubRegIndex *getSubRegIdx(Record*);
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// Find or create a sub-register index representing the A+B composition.
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CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
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CodeGenSubRegIndex *B);
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|
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// Find or create a sub-register index representing the concatenation of
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// non-overlapping sibling indices.
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|
CodeGenSubRegIndex *
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getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
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|
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void
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addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
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CodeGenSubRegIndex *Idx) {
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ConcatIdx.insert(std::make_pair(Parts, Idx));
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}
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const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
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const StringMap<CodeGenRegister*> &getRegistersByName() {
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|
return RegistersByName;
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|
}
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|
|
|
// Find a register from its Record def.
|
|
CodeGenRegister *getReg(Record*);
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|
|
|
// Get a Register's index into the Registers array.
|
|
unsigned getRegIndex(const CodeGenRegister *Reg) const {
|
|
return Reg->EnumValue - 1;
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|
}
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|
|
|
// Return the number of allocated TopoSigs. The first TopoSig representing
|
|
// leaf registers is allocated number 0.
|
|
unsigned getNumTopoSigs() const {
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|
return TopoSigs.size();
|
|
}
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|
|
|
// Find or create a TopoSig for the given TopoSigId.
|
|
// This function is only for use by CodeGenRegister::computeSuperRegs().
|
|
// Others should simply use Reg->getTopoSig().
|
|
unsigned getTopoSig(const TopoSigId &Id) {
|
|
return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
|
|
}
|
|
|
|
// Create a native register unit that is associated with one or two root
|
|
// registers.
|
|
unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
|
|
RegUnits.resize(RegUnits.size() + 1);
|
|
RegUnits.back().Roots[0] = R0;
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|
RegUnits.back().Roots[1] = R1;
|
|
return RegUnits.size() - 1;
|
|
}
|
|
|
|
// Create a new non-native register unit that can be adopted by a register
|
|
// to increase its pressure. Note that NumNativeRegUnits is not increased.
|
|
unsigned newRegUnit(unsigned Weight) {
|
|
RegUnits.resize(RegUnits.size() + 1);
|
|
RegUnits.back().Weight = Weight;
|
|
return RegUnits.size() - 1;
|
|
}
|
|
|
|
// Native units are the singular unit of a leaf register. Register aliasing
|
|
// is completely characterized by native units. Adopted units exist to give
|
|
// register additional weight but don't affect aliasing.
|
|
bool isNativeUnit(unsigned RUID) {
|
|
return RUID < NumNativeRegUnits;
|
|
}
|
|
|
|
unsigned getNumNativeRegUnits() const {
|
|
return NumNativeRegUnits;
|
|
}
|
|
|
|
RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
|
|
const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
|
|
|
|
ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
|
|
return RegClasses;
|
|
}
|
|
|
|
// Find a register class from its def.
|
|
CodeGenRegisterClass *getRegClass(Record*);
|
|
|
|
/// getRegisterClassForRegister - Find the register class that contains the
|
|
/// specified physical register. If the register is not in a register
|
|
/// class, return null. If the register is in multiple classes, and the
|
|
/// classes have a superset-subset relationship and the same set of types,
|
|
/// return the superclass. Otherwise return null.
|
|
const CodeGenRegisterClass* getRegClassForRegister(Record *R);
|
|
|
|
// Get the sum of unit weights.
|
|
unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
|
|
unsigned Weight = 0;
|
|
for (std::vector<unsigned>::const_iterator
|
|
I = Units.begin(), E = Units.end(); I != E; ++I)
|
|
Weight += getRegUnit(*I).Weight;
|
|
return Weight;
|
|
}
|
|
|
|
unsigned getRegSetIDAt(unsigned Order) const {
|
|
return RegUnitSetOrder[Order];
|
|
}
|
|
const RegUnitSet &getRegSetAt(unsigned Order) const {
|
|
return RegUnitSets[RegUnitSetOrder[Order]];
|
|
}
|
|
|
|
// Increase a RegUnitWeight.
|
|
void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
|
|
getRegUnit(RUID).Weight += Inc;
|
|
}
|
|
|
|
// Get the number of register pressure dimensions.
|
|
unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
|
|
|
|
// Get a set of register unit IDs for a given dimension of pressure.
|
|
const RegUnitSet &getRegPressureSet(unsigned Idx) const {
|
|
return RegUnitSets[Idx];
|
|
}
|
|
|
|
// The number of pressure set lists may be larget than the number of
|
|
// register classes if some register units appeared in a list of sets that
|
|
// did not correspond to an existing register class.
|
|
unsigned getNumRegClassPressureSetLists() const {
|
|
return RegClassUnitSets.size();
|
|
}
|
|
|
|
// Get a list of pressure set IDs for a register class. Liveness of a
|
|
// register in this class impacts each pressure set in this list by the
|
|
// weight of the register. An exact solution requires all registers in a
|
|
// class to have the same class, but it is not strictly guaranteed.
|
|
ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
|
|
return RegClassUnitSets[RCIdx];
|
|
}
|
|
|
|
// Computed derived records such as missing sub-register indices.
|
|
void computeDerivedInfo();
|
|
|
|
// Compute the set of registers completely covered by the registers in Regs.
|
|
// The returned BitVector will have a bit set for each register in Regs,
|
|
// all sub-registers, and all super-registers that are covered by the
|
|
// registers in Regs.
|
|
//
|
|
// This is used to compute the mask of call-preserved registers from a list
|
|
// of callee-saves.
|
|
BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
|
|
|
|
// Bit mask of lanes that cover their registers. A sub-register index whose
|
|
// LaneMask is contained in CoveringLanes will be completely covered by
|
|
// another sub-register with the same or larger lane mask.
|
|
unsigned CoveringLanes;
|
|
};
|
|
}
|
|
|
|
#endif
|