f6893f09d5
This includes support for pmap_enter(..., psind=1) as described in the commit log message for r321378. The changes are largely modelled after amd64. arm64 has more stringent requirements around superpage creation to avoid the possibility of TLB conflict aborts, and these requirements do not apply to RISC-V, which like amd64 permits simultaneous caching of 4KB and 2MB translations for a given page. RISC-V's PTE format includes only two software bits, and as these are already consumed we do not have an analogue for amd64's PG_PROMOTED. Instead, pmap_remove_l2() always invalidates the entire 2MB address range. pmap_ts_referenced() is modified to clear PTE_A, now that we support both hardware- and software-managed reference and dirty bits. Also fix pmap_fault_fixup() so that it does not set PTE_A or PTE_D on kernel mappings. Reviewed by: kib (earlier version) Discussed with: jhb Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D18863 Differential Revision: https://reviews.freebsd.org/D18864 Differential Revision: https://reviews.freebsd.org/D18865 Differential Revision: https://reviews.freebsd.org/D18866 Differential Revision: https://reviews.freebsd.org/D18867 Differential Revision: https://reviews.freebsd.org/D18868
95 lines
3.3 KiB
C
95 lines
3.3 KiB
C
/*-
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* Copyright (c) 2014 Andrew Turner
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* Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#ifndef LOCORE
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typedef uint64_t pd_entry_t; /* page directory entry */
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typedef uint64_t pt_entry_t; /* page table entry */
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typedef uint64_t pn_t; /* page number */
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#endif
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/* Level 0 table, 512GiB per entry */
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#define L0_SHIFT 39
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/* Level 1 table, 1GiB per entry */
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#define L1_SHIFT 30
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#define L1_SIZE (1 << L1_SHIFT)
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#define L1_OFFSET (L1_SIZE - 1)
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/* Level 2 table, 2MiB per entry */
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#define L2_SHIFT 21
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#define L2_SIZE (1 << L2_SHIFT)
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#define L2_OFFSET (L2_SIZE - 1)
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/* Level 3 table, 4KiB per entry */
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#define L3_SHIFT 12
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#define L3_SIZE (1 << L3_SHIFT)
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#define L3_OFFSET (L3_SIZE - 1)
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#define Ln_ENTRIES_SHIFT 9
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#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
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#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
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/* Bits 9:8 are reserved for software */
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#define PTE_SW_MANAGED (1 << 9)
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#define PTE_SW_WIRED (1 << 8)
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#define PTE_D (1 << 7) /* Dirty */
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#define PTE_A (1 << 6) /* Accessed */
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#define PTE_G (1 << 5) /* Global */
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#define PTE_U (1 << 4) /* User */
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#define PTE_X (1 << 3) /* Execute */
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#define PTE_W (1 << 2) /* Write */
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#define PTE_R (1 << 1) /* Read */
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#define PTE_V (1 << 0) /* Valid */
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#define PTE_RWX (PTE_R | PTE_W | PTE_X)
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#define PTE_RX (PTE_R | PTE_X)
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#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D)
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#define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | PTE_U | \
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PTE_SW_MANAGED | PTE_SW_WIRED)
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#define PTE_PPN0_S 10
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#define PTE_PPN1_S 19
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#define PTE_PPN2_S 28
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#define PTE_PPN3_S 37
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#define PTE_SIZE 8
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#endif /* !_MACHINE_PTE_H_ */
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/* End of pte.h */
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