72143e89bb
This provides an OpenCrypto driver for Intel QuickAssist devices. The driver was initially ported from NetBSD and comes with a few improvements: - support for GMAC/AES-GCM, AES-CTR and AES-XTS, and support for SHA/HMAC-authenticated encryption - support for detaching the driver - various bug fixes - DH895X support Discussed with: jhb MFC after: 3 days Sponsored by: Rubicon Communications, LLC (Netgate) Differential Revision: https://reviews.freebsd.org/D26963
120 lines
4.8 KiB
C
120 lines
4.8 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
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/*
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* Copyright (c) 2019 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright(c) 2014-2020 Intel Corporation.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef _DEV_PCI_QAT_DH895XCCREG_H_
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#define _DEV_PCI_QAT_DH895XCCREG_H_
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/* Max number of accelerators and engines */
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#define MAX_ACCEL_DH895XCC 6
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#define MAX_AE_DH895XCC 12
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/* PCIe BAR index */
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#define BAR_SRAM_ID_DH895XCC 0
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#define BAR_PMISC_ID_DH895XCC 1
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#define BAR_ETR_ID_DH895XCC 2
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/* BAR PMISC sub-regions */
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#define AE_OFFSET_DH895XCC 0x20000
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#define AE_LOCAL_OFFSET_DH895XCC 0x20800
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#define CAP_GLOBAL_OFFSET_DH895XCC 0x30000
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#define SOFTSTRAP_REG_DH895XCC 0x2EC
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#define FUSECTL_SKU_MASK_DH895XCC 0x300000
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#define FUSECTL_SKU_SHIFT_DH895XCC 20
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#define FUSECTL_SKU_1_DH895XCC 0
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#define FUSECTL_SKU_2_DH895XCC 1
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#define FUSECTL_SKU_3_DH895XCC 2
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#define FUSECTL_SKU_4_DH895XCC 3
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#define ACCEL_REG_OFFSET_DH895XCC 13
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#define ACCEL_MASK_DH895XCC 0x3F
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#define AE_MASK_DH895XCC 0xFFF
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#define SMIAPF0_DH895XCC 0x3A028
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#define SMIAPF1_DH895XCC 0x3A030
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#define SMIA0_MASK_DH895XCC 0xFFFFFFFF
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#define SMIA1_MASK_DH895XCC 0x1
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/* Error detection and correction */
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#define AE_CTX_ENABLES_DH895XCC(i) ((i) * 0x1000 + 0x20818)
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#define AE_MISC_CONTROL_DH895XCC(i) ((i) * 0x1000 + 0x20960)
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#define ENABLE_AE_ECC_ERR_DH895XCC __BIT(28)
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#define ENABLE_AE_ECC_PARITY_CORR_DH895XCC (__BIT(24) | __BIT(12))
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#define ERRSSMSH_EN_DH895XCC __BIT(3)
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/* BIT(2) enables the logging of push/pull data errors. */
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#define PPERR_EN_DH895XCC (__BIT(2))
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/* ETR */
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#define ETR_MAX_BANKS_DH895XCC 32
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#define ETR_TX_RX_GAP_DH895XCC 8
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#define ETR_TX_RINGS_MASK_DH895XCC 0xFF
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#define ETR_BUNDLE_SIZE_DH895XCC 0x1000
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/* AE firmware */
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#define AE_FW_PROD_TYPE_DH895XCC 0x00400000
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#define AE_FW_MOF_NAME_DH895XCC "qat_895xcc"
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#define AE_FW_MMP_NAME_DH895XCC "qat_895xcc_mmp"
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#define AE_FW_UOF_NAME_DH895XCC "icp_qat_ae.uof"
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/* Clock frequency */
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#define CLOCK_PER_SEC_DH895XCC (685 * 1000000 / 16)
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#endif
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