351 lines
10 KiB
C
351 lines
10 KiB
C
/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */
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/*-
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* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
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* Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/if_rtwn_ridx.h>
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#include <dev/rtwn/rtl8192c/r92c.h>
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#include <dev/rtwn/rtl8192c/r92c_priv.h>
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#include <dev/rtwn/rtl8192c/r92c_reg.h>
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#include <dev/rtwn/rtl8192c/r92c_var.h>
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static int
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r92c_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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uint8_t chan;
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int group;
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chan = rtwn_chan2centieee(c);
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if (IEEE80211_IS_CHAN_2GHZ(c)) {
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if (chan <= 3) group = 0;
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else if (chan <= 9) group = 1;
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else if (chan <= 14) group = 2;
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else {
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KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
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return (-1);
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}
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} else {
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KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
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return (-1);
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}
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return (group);
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}
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/* XXX recheck */
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void
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r92c_get_txpower(struct rtwn_softc *sc, int chain,
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struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
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{
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struct r92c_softc *rs = sc->sc_priv;
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struct rtwn_r92c_txpwr *rt = rs->rs_txpwr;
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const struct rtwn_r92c_txagc *base = rs->rs_txagc;
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uint8_t ofdmpow, htpow, diff, max;
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int max_mcs, ridx, group;
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/* Determine channel group. */
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group = r92c_get_power_group(sc, c);
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if (group == -1) { /* shouldn't happen */
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device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
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return;
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}
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/* XXX net80211 regulatory */
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max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
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KASSERT(max_mcs <= RTWN_RIDX_COUNT, ("increase ridx limit\n"));
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if (rs->regulatory == 0) {
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for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
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power[ridx] = base[chain].pwr[0][ridx];
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}
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for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_COUNT; ridx++) {
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if (rs->regulatory == 3) {
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power[ridx] = base[chain].pwr[0][ridx];
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/* Apply vendor limits. */
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if (IEEE80211_IS_CHAN_HT40(c))
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max = rt->ht40_max_pwr[chain][group];
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else
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max = rt->ht20_max_pwr[chain][group];
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if (power[ridx] > max)
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power[ridx] = max;
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} else if (rs->regulatory == 1) {
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if (!IEEE80211_IS_CHAN_HT40(c))
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power[ridx] = base[chain].pwr[group][ridx];
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} else if (rs->regulatory != 2)
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power[ridx] = base[chain].pwr[0][ridx];
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}
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/* Compute per-CCK rate Tx power. */
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for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
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power[ridx] += rt->cck_tx_pwr[chain][group];
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htpow = rt->ht40_1s_tx_pwr[chain][group];
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if (sc->ntxchains > 1) {
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/* Apply reduction for 2 spatial streams. */
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diff = rt->ht40_2s_tx_pwr_diff[chain][group];
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htpow = (htpow > diff) ? htpow - diff : 0;
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}
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/* Compute per-OFDM rate Tx power. */
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diff = rt->ofdm_tx_pwr_diff[chain][group];
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ofdmpow = htpow + diff; /* HT->OFDM correction. */
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for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
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power[ridx] += ofdmpow;
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/* Compute per-MCS Tx power. */
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if (!IEEE80211_IS_CHAN_HT40(c)) {
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diff = rt->ht20_tx_pwr_diff[chain][group];
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htpow += diff; /* HT40->HT20 correction. */
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}
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for (ridx = RTWN_RIDX_HT_MCS(0); ridx <= max_mcs; ridx++)
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power[ridx] += htpow;
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/* Apply max limit. */
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for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
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if (power[ridx] > R92C_MAX_TX_PWR)
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power[ridx] = R92C_MAX_TX_PWR;
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}
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}
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void
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r92c_write_txpower(struct rtwn_softc *sc, int chain,
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uint8_t power[RTWN_RIDX_COUNT])
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{
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uint32_t reg;
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/* Write per-CCK rate Tx power. */
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if (chain == 0) {
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reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
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reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]);
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rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
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reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
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reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]);
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reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]);
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reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]);
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rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
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} else {
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reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
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reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]);
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reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]);
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reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]);
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rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
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reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
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reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]);
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rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
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}
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/* Write per-OFDM rate Tx power. */
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rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
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SM(R92C_TXAGC_RATE06, power[RTWN_RIDX_OFDM6]) |
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SM(R92C_TXAGC_RATE09, power[RTWN_RIDX_OFDM9]) |
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SM(R92C_TXAGC_RATE12, power[RTWN_RIDX_OFDM12]) |
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SM(R92C_TXAGC_RATE18, power[RTWN_RIDX_OFDM18]));
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rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
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SM(R92C_TXAGC_RATE24, power[RTWN_RIDX_OFDM24]) |
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SM(R92C_TXAGC_RATE36, power[RTWN_RIDX_OFDM36]) |
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SM(R92C_TXAGC_RATE48, power[RTWN_RIDX_OFDM48]) |
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SM(R92C_TXAGC_RATE54, power[RTWN_RIDX_OFDM54]));
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/* Write per-MCS Tx power. */
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rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
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SM(R92C_TXAGC_MCS00, power[RTWN_RIDX_HT_MCS(0)]) |
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SM(R92C_TXAGC_MCS01, power[RTWN_RIDX_HT_MCS(1)]) |
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SM(R92C_TXAGC_MCS02, power[RTWN_RIDX_HT_MCS(2)]) |
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SM(R92C_TXAGC_MCS03, power[RTWN_RIDX_HT_MCS(3)]));
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rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
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SM(R92C_TXAGC_MCS04, power[RTWN_RIDX_HT_MCS(4)]) |
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SM(R92C_TXAGC_MCS05, power[RTWN_RIDX_HT_MCS(5)]) |
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SM(R92C_TXAGC_MCS06, power[RTWN_RIDX_HT_MCS(6)]) |
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SM(R92C_TXAGC_MCS07, power[RTWN_RIDX_HT_MCS(7)]));
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if (sc->ntxchains >= 2) {
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rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
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SM(R92C_TXAGC_MCS08, power[RTWN_RIDX_HT_MCS(8)]) |
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SM(R92C_TXAGC_MCS09, power[RTWN_RIDX_HT_MCS(9)]) |
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SM(R92C_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) |
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SM(R92C_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)]));
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rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
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SM(R92C_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) |
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SM(R92C_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) |
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SM(R92C_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) |
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SM(R92C_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)]));
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}
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}
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static void
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r92c_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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uint8_t power[RTWN_RIDX_COUNT];
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int i;
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for (i = 0; i < sc->ntxchains; i++) {
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memset(power, 0, sizeof(power));
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/* Compute per-rate Tx power values. */
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rtwn_r92c_get_txpower(sc, i, c, power);
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#ifdef RTWN_DEBUG
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if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
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int max_mcs, ridx;
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max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
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/* Dump per-rate Tx power values. */
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printf("Tx power for chain %d:\n", i);
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for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++)
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printf("Rate %d = %u\n", ridx, power[ridx]);
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}
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#endif
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/* Write per-rate Tx power values to hardware. */
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r92c_write_txpower(sc, i, power);
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}
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}
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static void
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r92c_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo)
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{
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struct r92c_softc *rs = sc->sc_priv;
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rtwn_setbits_1(sc, R92C_BWOPMODE, R92C_BWOPMODE_20MHZ, 0);
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rtwn_setbits_1(sc, R92C_RRSR + 2, 0x6f, (prichlo ? 1 : 2) << 5);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ);
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rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ);
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/* Set CCK side band. */
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rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10,
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(prichlo ? 0 : 1) << 4);
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rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00,
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(prichlo ? 1 : 2) << 10);
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rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
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R92C_FPGA0_ANAPARAM2_CBW20, 0);
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rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
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/* Select 40MHz bandwidth. */
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rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
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(rs->rf_chnlbw[0] & ~0xfff) | chan);
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}
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void
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r92c_set_bw20(struct rtwn_softc *sc, uint8_t chan)
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{
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struct r92c_softc *rs = sc->sc_priv;
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rtwn_setbits_1(sc, R92C_BWOPMODE, 0, R92C_BWOPMODE_20MHZ);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
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rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
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rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 0,
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R92C_FPGA0_ANAPARAM2_CBW20);
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/* Select 20MHz bandwidth. */
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rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
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(rs->rf_chnlbw[0] & ~0xfff) | chan | R92C_RF_CHNLBW_BW20);
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}
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void
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r92c_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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struct r92c_softc *rs = sc->sc_priv;
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u_int chan;
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int i;
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chan = rtwn_chan2centieee(c);
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/* Set Tx power for this new channel. */
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r92c_set_txpower(sc, c);
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for (i = 0; i < sc->nrxchains; i++) {
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rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
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RW(rs->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
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}
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if (IEEE80211_IS_CHAN_HT40(c))
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r92c_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c));
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else
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rtwn_r92c_set_bw20(sc, chan);
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}
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void
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r92c_set_gain(struct rtwn_softc *sc, uint8_t gain)
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{
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rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0),
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R92C_OFDM0_AGCCORE1_GAIN_M, gain);
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rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(1),
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R92C_OFDM0_AGCCORE1_GAIN_M, gain);
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}
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void
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r92c_scan_start(struct ieee80211com *ic)
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{
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struct rtwn_softc *sc = ic->ic_softc;
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struct r92c_softc *rs = sc->sc_priv;
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RTWN_LOCK(sc);
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/* Set gain for scanning. */
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rtwn_r92c_set_gain(sc, 0x20);
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RTWN_UNLOCK(sc);
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rs->rs_scan_start(ic);
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}
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void
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r92c_scan_end(struct ieee80211com *ic)
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{
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struct rtwn_softc *sc = ic->ic_softc;
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struct r92c_softc *rs = sc->sc_priv;
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RTWN_LOCK(sc);
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/* Set gain under link. */
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rtwn_r92c_set_gain(sc, 0x32);
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RTWN_UNLOCK(sc);
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rs->rs_scan_end(ic);
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}
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