b09de0b34a
ARM Coresight is a solution for debug and trace of complex SoC designs. This includes a collection of drivers for ARM Coresight interconnect devices within a small Coresight framework. Supported devices are: o Embedded Trace Macrocell v4 (ETMv4) o Funnel o Dynamic Replicator o Trace Memory Controller (TMC) o CPU debug module Devices are connected to each other internally in SoC and the configuration of each device endpoints is described in FDT. Typical trace flow (as found on Qualcomm Snapdragon 410e): CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM CPU1 -> ETM1 -^ CPU2 -> ETM2 -^ CPU3 -> ETM3 -^ Note that both Embedded Trace FIFO (ETF) and Embedded Trace Router (ETR) are hardware configurations of TMC. This is required for upcoming HWPMC tracing support. This is tested on single-core system only. Reviewed by: andrew (partially) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D14618
67 lines
3.2 KiB
C
67 lines
3.2 KiB
C
/*-
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* Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by BAE Systems, the University of Cambridge
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* Computer Laboratory, and Memorial University under DARPA/AFRL contract
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* FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
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* (TC) research program.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM64_CORESIGHT_CORESIGHT_FUNNEL_H_
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#define _ARM64_CORESIGHT_CORESIGHT_FUNNEL_H_
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#define FUNNEL_FUNCTL 0x000 /* Funnel Control Register */
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#define FUNCTL_HOLDTIME_SHIFT 8
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#define FUNCTL_HOLDTIME_MASK (0xf << FUNCTL_HOLDTIME_SHIFT)
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#define FUNNEL_PRICTL 0x004 /* Priority Control Register */
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#define FUNNEL_ITATBDATA0 0xEEC /* Integration Register, ITATBDATA0 */
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#define FUNNEL_ITATBCTR2 0xEF0 /* Integration Register, ITATBCTR2 */
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#define FUNNEL_ITATBCTR1 0xEF4 /* Integration Register, ITATBCTR1 */
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#define FUNNEL_ITATBCTR0 0xEF8 /* Integration Register, ITATBCTR0 */
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#define FUNNEL_IMCR 0xF00 /* Integration Mode Control Register */
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#define FUNNEL_CTSR 0xFA0 /* Claim Tag Set Register */
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#define FUNNEL_CTCR 0xFA4 /* Claim Tag Clear Register */
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#define FUNNEL_LOCKACCESS 0xFB0 /* Lock Access */
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#define FUNNEL_LOCKSTATUS 0xFB4 /* Lock Status */
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#define FUNNEL_AUTHSTATUS 0xFB8 /* Authentication status */
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#define FUNNEL_DEVICEID 0xFC8 /* Device ID */
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#define FUNNEL_DEVICETYPE 0xFCC /* Device Type Identifier */
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#define FUNNEL_PERIPH4 0xFD0 /* Peripheral ID4 */
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#define FUNNEL_PERIPH5 0xFD4 /* Peripheral ID5 */
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#define FUNNEL_PERIPH6 0xFD8 /* Peripheral ID6 */
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#define FUNNEL_PERIPH7 0xFDC /* Peripheral ID7 */
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#define FUNNEL_PERIPH0 0xFE0 /* Peripheral ID0 */
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#define FUNNEL_PERIPH1 0xFE4 /* Peripheral ID1 */
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#define FUNNEL_PERIPH2 0xFE8 /* Peripheral ID2 */
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#define FUNNEL_PERIPH3 0xFEC /* Peripheral ID3 */
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#define FUNNEL_COMP0 0xFF0 /* Component ID0 */
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#define FUNNEL_COMP1 0xFF4 /* Component ID1 */
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#define FUNNEL_COMP2 0xFF8 /* Component ID2 */
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#define FUNNEL_COMP3 0xFFC /* Component ID3 */
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#endif /* !_ARM64_CORESIGHT_CORESIGHT_FUNNEL_H_ */
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