31188d61c1
on the ASIX AX88140A chip. Update /sys/conf/files, RELNOTES.TXT, /sys/i388/i386/userconfig.c, sysinstall/devices.c, GENERIC and LINT accordingly. For now, the only board that I know of that uses this chip is the Alfa Inc. GFC2204. (Its predecessor, the GFC2202, was a DEC tulip card.) Thanks again to Ulf for obtaining the board for me. If anyone runs across another, please feel free to update the man page and/or the release notes. (The same applies for the other drivers.) FreeBSD should now have support for all of the DEC tulip workalike chipsets currently on the market (Macronix, Lite-On, Winbond, ASIX). And unless I'm mistaken, it should also have support for all PCI fast ethernet chipsets in general (except maybe the SMC FEAST chip, which nobody seems to ever use, including SMC). Now if only we could convince 3Com, Intel or whoever to cough up some documentation for gigabit ethernet hardware. Also updated RELNOTEX.TXT to mention that the SVEC PN102TX is supported by the Macronix driver (assuming you actually have an SVEC PN102TX with a Macronix chip on it; I tried to order a PN102TX once and got a box labeled 'Hawking Technology PN102TX' that had a VIA Rhine board inside it).
561 lines
17 KiB
C
561 lines
17 KiB
C
/*
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: if_axreg.h,v 1.3 1999/01/07 02:59:08 wpaul Exp $
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*/
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/*
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* ASIX register definitions.
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*/
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#define AX_BUSCTL 0x00 /* bus control */
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#define AX_TXSTART 0x08 /* tx start demand */
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#define AX_RXSTART 0x10 /* rx start demand */
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#define AX_RXADDR 0x18 /* rx descriptor list start addr */
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#define AX_TXADDR 0x20 /* tx descriptor list start addr */
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#define AX_ISR 0x28 /* interrupt status register */
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#define AX_NETCFG 0x30 /* network config register */
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#define AX_IMR 0x38 /* interrupt mask */
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#define AX_FRAMESDISCARDED 0x40 /* # of discarded frames */
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#define AX_SIO 0x48 /* MII and ROM/EEPROM access */
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#define AX_RESERVED 0x50
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#define AX_GENTIMER 0x58 /* general timer */
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#define AX_GENPORT 0x60 /* general purpose port */
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#define AX_FILTIDX 0x68 /* RX filter index */
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#define AX_FILTDATA 0x70 /* RX filter data */
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/*
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* Bus control bits.
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*/
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#define AX_BUSCTL_RESET 0x00000001
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#define AX_BUSCTL_ARBITRATION 0x00000002
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#define AX_BUSCTL_BIGENDIAN 0x00000080
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#define AX_BUSCTL_BURSTLEN 0x00003F00
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#define AX_BUSCTL_BUF_BIGENDIAN 0x00100000
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#define AX_BISCTL_READMULTI 0x00200000
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#define AX_BURSTLEN_UNLIMIT 0x00000000
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#define AX_BURSTLEN_1LONG 0x00000100
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#define AX_BURSTLEN_2LONG 0x00000200
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#define AX_BURSTLEN_4LONG 0x00000400
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#define AX_BURSTLEN_8LONG 0x00000800
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#define AX_BURSTLEN_16LONG 0x00001000
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#define AX_BURSTLEN_32LONG 0x00002000
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#define AX_BUSCTL_CONFIG (AX_BUSCTL_ARBITRATION|AX_BURSTLEN_8LONG|AX_BURSTLEN_8LONG)
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/*
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* Interrupt status bits.
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*/
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#define AX_ISR_TX_OK 0x00000001
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#define AX_ISR_TX_IDLE 0x00000002
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#define AX_ISR_TX_NOBUF 0x00000004
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#define AX_ISR_TX_JABBERTIMEO 0x00000008
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#define AX_ISR_TX_UNDERRUN 0x00000020
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#define AX_ISR_RX_OK 0x00000040
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#define AX_ISR_RX_NOBUF 0x00000080
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#define AX_ISR_RX_IDLE 0x00000100
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#define AX_ISR_RX_WATDOGTIMEO 0x00000200
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#define AX_ISR_TX_EARLY 0x00000400
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#define AX_ISR_TIMER_EXPIRED 0x00000800
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#define AX_ISR_BUS_ERR 0x00002000
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#define AX_ISR_ABNORMAL 0x00008000
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#define AX_ISR_NORMAL 0x00010000
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#define AX_ISR_RX_STATE 0x000E0000
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#define AX_ISR_TX_STATE 0x00700000
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#define AX_ISR_BUSERRTYPE 0x03800000
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#define AX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
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#define AX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
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#define AX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
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#define AX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
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#define AX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
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#define AX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
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#define AX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
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#define AX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
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#define AX_TXSTATE_RESET 0x00000000 /* 000 - reset */
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#define AX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
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#define AX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
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#define AX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
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#define AX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
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#define AX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
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#define AX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
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#define AX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
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/*
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* Network config bits.
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*/
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#define AX_NETCFG_LINKSTAT_PCS 0x00000001
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#define AX_NETCFG_RX_ON 0x00000002
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#define AX_NETCFG_RX_BADFRAMES 0x00000008
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#define AX_NETCFG_RX_PROMISC 0x00000040
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#define AX_NETCFG_RX_ALLMULTI 0x00000080
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#define AX_NETCFG_RX_BROAD 0x00000100
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#define AX_NETCFG_FULLDUPLEX 0x00000200
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#define AX_NETCFG_LOOPBACK 0x00000C00
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#define AX_NETCFG_FORCECOLL 0x00001000
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#define AX_NETCFG_TX_ON 0x00002000
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#define AX_NETCFG_TX_THRESH 0x0000C000
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#define AX_NETCFG_PORTSEL 0x00040000 /* 0 == SRL, 1 == MII/SYM */
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#define AX_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */
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#define AX_NETCFG_STORENFWD 0x00200000
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#define AX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
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#define AX_NETCFG_PCS 0x00800000
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#define AX_NETCFG_SCRAMBLER 0x01000000
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#define AX_NETCFG_RX_ALL 0x40000000
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#define AX_OPMODE_NORM 0x00000000
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#define AX_OPMODE_INTLOOP 0x00000400
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#define AX_OPMODE_EXTLOOP 0x00000800
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#define AX_TXTHRESH_72BYTES 0x00000000
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#define AX_TXTHRESH_96BYTES 0x00004000
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#define AX_TXTHRESH_128BYTES 0x00008000
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#define AX_TXTHRESH_160BYTES 0x0000C000
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/*
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* Interrupt mask bits.
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*/
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#define AX_IMR_TX_OK 0x00000001
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#define AX_IMR_TX_IDLE 0x00000002
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#define AX_IMR_TX_NOBUF 0x00000004
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#define AX_IMR_TX_JABBERTIMEO 0x00000008
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#define AX_IMR_TX_UNDERRUN 0x00000020
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#define AX_IMR_RX_OK 0x00000040
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#define AX_IMR_RX_NOBUF 0x00000080
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#define AX_IMR_RX_IDLE 0x00000100
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#define AX_IMR_RX_WATDOGTIMEO 0x00000200
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#define AX_IMR_TX_EARLY 0x00000400
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#define AX_IMR_TIMER_EXPIRED 0x00000800
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#define AX_IMR_BUS_ERR 0x00002000
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#define AX_IMR_RX_EARLY 0x00004000
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#define AX_IMR_ABNORMAL 0x00008000
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#define AX_IMR_NORMAL 0x00010000
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#define AX_INTRS \
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(AX_IMR_RX_OK|AX_IMR_TX_OK|AX_IMR_RX_NOBUF|AX_IMR_RX_WATDOGTIMEO|\
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AX_IMR_TX_NOBUF|AX_IMR_TX_UNDERRUN|AX_IMR_BUS_ERR| \
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AX_IMR_ABNORMAL|AX_IMR_NORMAL|/*AX_IMR_TX_EARLY*/ \
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AX_IMR_TX_IDLE|AX_IMR_RX_IDLE)
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/*
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* Serial I/O (EEPROM/ROM) bits.
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*/
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#define AX_SIO_EE_CS 0x00000001 /* EEPROM chip select */
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#define AX_SIO_EE_CLK 0x00000002 /* EEPROM clock */
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#define AX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
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#define AX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
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#define AX_SIO_EESEL 0x00000800
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#define AX_SIO_ROMSEL 0x00001000
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#define AX_SIO_ROMCTL_WRITE 0x00002000
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#define AX_SIO_ROMCTL_READ 0x00004000
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#define AX_SIO_MII_CLK 0x00010000 /* MDIO clock */
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#define AX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
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#define AX_SIO_MII_DIR 0x00040000 /* MDIO dir */
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#define AX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
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#define AX_EECMD_WRITE 0x140
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#define AX_EECMD_READ 0x180
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#define AX_EECMD_ERASE 0x1c0
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#define AX_EE_NODEADDR_OFFSET 0x70
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#define AX_EE_NODEADDR 10
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/*
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* General purpose timer register
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*/
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#define AX_TIMER_VALUE 0x0000FFFF
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#define AX_TIMER_CONTINUOUS 0x00010000
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/*
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* RX Filter Index Register values
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*/
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#define AX_FILTIDX_PAR0 0x00000000
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#define AX_FILTIDX_PAR1 0x00000001
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#define AX_FILTIDX_MAR0 0x00000002
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#define AX_FILTIDX_MAR1 0x00000003
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/*
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* ASIX TX/RX list structure.
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*/
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struct ax_desc {
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volatile u_int32_t ax_status;
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volatile u_int32_t ax_ctl;
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volatile u_int32_t ax_ptr1;
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volatile u_int32_t ax_ptr2;
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};
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#define ax_data ax_ptr1
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#define ax_next ax_ptr2
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#define AX_RXSTAT_FIFOOFLOW 0x00000001
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#define AX_RXSTAT_CRCERR 0x00000002
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#define AX_RXSTAT_DRIBBLE 0x00000004
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#define AX_RXSTAT_WATCHDOG 0x00000010
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#define AX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
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#define AX_RXSTAT_COLLSEEN 0x00000040
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#define AX_RXSTAT_GIANT 0x00000080
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#define AX_RXSTAT_LASTFRAG 0x00000100
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#define AX_RXSTAT_FIRSTFRAG 0x00000200
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#define AX_RXSTAT_MULTICAST 0x00000400
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#define AX_RXSTAT_RUNT 0x00000800
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#define AX_RXSTAT_RXTYPE 0x00003000
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#define AX_RXSTAT_RXERR 0x00008000
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#define AX_RXSTAT_RXLEN 0x3FFF0000
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#define AX_RXSTAT_OWN 0x80000000
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#define AX_RXBYTES(x) ((x & AX_RXSTAT_RXLEN) >> 16)
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#define AX_RXSTAT (AX_RXSTAT_FIRSTFRAG|AX_RXSTAT_LASTFRAG|AX_RXSTAT_OWN)
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#define AX_RXCTL_BUFLEN1 0x00000FFF
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#define AX_RXCTL_BUFLEN2 0x00FFF000
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#define AX_RXCTL_RLAST 0x02000000
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#define AX_TXSTAT_DEFER 0x00000001
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#define AX_TXSTAT_UNDERRUN 0x00000002
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#define AX_TXSTAT_LINKFAIL 0x00000003
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#define AX_TXSTAT_COLLCNT 0x00000078
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#define AX_TXSTAT_SQE 0x00000080
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#define AX_TXSTAT_EXCESSCOLL 0x00000100
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#define AX_TXSTAT_LATECOLL 0x00000200
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#define AX_TXSTAT_NOCARRIER 0x00000400
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#define AX_TXSTAT_CARRLOST 0x00000800
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#define AX_TXSTAT_JABTIMEO 0x00004000
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#define AX_TXSTAT_ERRSUM 0x00008000
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#define AX_TXSTAT_OWN 0x80000000
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#define AX_TXCTL_BUFLEN1 0x000007FF
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#define AX_TXCTL_BUFLEN2 0x003FF800
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#define AX_TXCTL_PAD 0x00800000
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#define AX_TXCTL_TLAST 0x02000000
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#define AX_TXCTL_NOCRC 0x04000000
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#define AX_TXCTL_FIRSTFRAG 0x20000000
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#define AX_TXCTL_LASTFRAG 0x40000000
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#define AX_TXCTL_FINT 0x80000000
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#define AX_MAXFRAGS 16
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#define AX_RX_LIST_CNT 64
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#define AX_TX_LIST_CNT 64
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#define AX_MIN_FRAMELEN 60
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/*
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* A tx 'super descriptor' is actually 16 regular descriptors
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* back to back.
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*/
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struct ax_txdesc {
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volatile struct ax_desc ax_frag[AX_MAXFRAGS];
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};
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#define AX_TXNEXT(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_next
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#define AX_TXSTATUS(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_status
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#define AX_TXCTL(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_ctl
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#define AX_TXDATA(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_data
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#define AX_TXOWN(x) x->ax_ptr->ax_frag[0].ax_status
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#define AX_UNSENT 0x12341234
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struct ax_list_data {
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volatile struct ax_desc ax_rx_list[AX_RX_LIST_CNT];
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volatile struct ax_txdesc ax_tx_list[AX_TX_LIST_CNT];
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};
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struct ax_chain {
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volatile struct ax_txdesc *ax_ptr;
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struct mbuf *ax_mbuf;
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struct ax_chain *ax_nextdesc;
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u_int8_t ax_lastdesc;
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};
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struct ax_chain_onefrag {
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volatile struct ax_desc *ax_ptr;
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struct mbuf *ax_mbuf;
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struct ax_chain_onefrag *ax_nextdesc;
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};
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struct ax_chain_data {
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u_int8_t ax_pad[AX_MIN_FRAMELEN];
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struct ax_chain_onefrag ax_rx_chain[AX_RX_LIST_CNT];
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struct ax_chain ax_tx_chain[AX_TX_LIST_CNT];
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struct ax_chain_onefrag *ax_rx_head;
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struct ax_chain *ax_tx_head;
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struct ax_chain *ax_tx_tail;
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struct ax_chain *ax_tx_free;
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};
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struct ax_type {
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u_int16_t ax_vid;
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u_int16_t ax_did;
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char *ax_name;
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};
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struct ax_mii_frame {
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u_int8_t mii_stdelim;
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u_int8_t mii_opcode;
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u_int8_t mii_phyaddr;
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u_int8_t mii_regaddr;
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u_int8_t mii_turnaround;
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u_int16_t mii_data;
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};
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/*
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* MII constants
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*/
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#define AX_MII_STARTDELIM 0x01
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#define AX_MII_READOP 0x02
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#define AX_MII_WRITEOP 0x01
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#define AX_MII_TURNAROUND 0x02
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#define AX_FLAG_FORCEDELAY 1
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#define AX_FLAG_SCHEDDELAY 2
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#define AX_FLAG_DELAYTIMEO 3
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struct ax_softc {
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struct arpcom arpcom; /* interface info */
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struct ifmedia ifmedia; /* media info */
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bus_space_handle_t ax_bhandle; /* bus space handle */
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bus_space_tag_t ax_btag; /* bus space tag */
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struct ax_type *ax_info; /* ASIX adapter info */
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struct ax_type *ax_pinfo; /* phy info */
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u_int8_t ax_unit; /* interface number */
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u_int8_t ax_type;
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u_int8_t ax_phy_addr; /* PHY address */
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u_int8_t ax_tx_pend; /* TX pending */
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u_int8_t ax_want_auto;
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u_int8_t ax_autoneg;
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caddr_t ax_ldata_ptr;
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struct ax_list_data *ax_ldata;
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struct ax_chain_data ax_cdata;
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};
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->ax_btag, sc->ax_bhandle, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->ax_btag, sc->ax_bbhandle, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->ax_btag, sc->ax_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->ax_btag, sc->ax_bhandle, reg)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->ax_btag, sc->ax_bhandle, reg)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->ax_btag, sc->ax_bhandle, reg)
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#define AX_TIMEOUT 1000
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/*
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* General constants that are fun to know.
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*
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* ASIX PCI vendor ID
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*/
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#define AX_VENDORID 0x125B
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/*
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* ASIX device IDs.
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*/
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#define AX_DEVICEID_AX88140A 0x1400
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/*
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* Texas Instruments PHY identifiers
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*/
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#define TI_PHY_VENDORID 0x4000
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#define TI_PHY_10BT 0x501F
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#define TI_PHY_100VGPMI 0x502F
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/*
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* These ID values are for the NS DP83840A 10/100 PHY
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*/
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#define NS_PHY_VENDORID 0x2000
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#define NS_PHY_83840A 0x5C0F
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/*
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* Level 1 10/100 PHY
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*/
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#define LEVEL1_PHY_VENDORID 0x7810
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#define LEVEL1_PHY_LXT970 0x000F
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/*
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* Intel 82555 10/100 PHY
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*/
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#define INTEL_PHY_VENDORID 0x0A28
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#define INTEL_PHY_82555 0x015F
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/*
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* SEEQ 80220 10/100 PHY
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*/
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#define SEEQ_PHY_VENDORID 0x0016
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#define SEEQ_PHY_80220 0xF83F
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/*
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* PCI low memory base and low I/O base register, and
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* other PCI registers.
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*/
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#define AX_PCI_VENDOR_ID 0x00
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#define AX_PCI_DEVICE_ID 0x02
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#define AX_PCI_COMMAND 0x04
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#define AX_PCI_STATUS 0x06
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#define AX_PCI_REVID 0x08
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#define AX_PCI_CLASSCODE 0x09
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#define AX_PCI_LATENCY_TIMER 0x0D
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#define AX_PCI_HEADER_TYPE 0x0E
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#define AX_PCI_LOIO 0x10
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#define AX_PCI_LOMEM 0x14
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#define AX_PCI_BIOSROM 0x30
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#define AX_PCI_INTLINE 0x3C
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#define AX_PCI_INTPIN 0x3D
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#define AX_PCI_MINGNT 0x3E
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#define AX_PCI_MINLAT 0x0F
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#define AX_PCI_RESETOPT 0x48
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#define AX_PCI_EEPROM_DATA 0x4C
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/* power management registers */
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#define AX_PCI_CAPID 0xDC /* 8 bits */
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#define AX_PCI_NEXTPTR 0xDD /* 8 bits */
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#define AX_PCI_PWRMGMTCAP 0xDE /* 16 bits */
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#define AX_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
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#define AX_PSTATE_MASK 0x0003
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#define AX_PSTATE_D0 0x0000
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#define AX_PSTATE_D1 0x0001
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#define AX_PSTATE_D2 0x0002
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#define AX_PSTATE_D3 0x0003
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#define AX_PME_EN 0x0010
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#define AX_PME_STATUS 0x8000
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#define PHY_UNKNOWN 6
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#define AX_PHYADDR_MIN 0x00
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#define AX_PHYADDR_MAX 0x1F
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#define PHY_BMCR 0x00
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#define PHY_BMSR 0x01
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#define PHY_VENID 0x02
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#define PHY_DEVID 0x03
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#define PHY_ANAR 0x04
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#define PHY_LPAR 0x05
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#define PHY_ANEXP 0x06
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#define PHY_ANAR_NEXTPAGE 0x8000
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#define PHY_ANAR_RSVD0 0x4000
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#define PHY_ANAR_TLRFLT 0x2000
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#define PHY_ANAR_RSVD1 0x1000
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#define PHY_ANAR_RSVD2 0x0800
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#define PHY_ANAR_RSVD3 0x0400
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#define PHY_ANAR_100BT4 0x0200
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#define PHY_ANAR_100BTXFULL 0x0100
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#define PHY_ANAR_100BTXHALF 0x0080
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#define PHY_ANAR_10BTFULL 0x0040
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#define PHY_ANAR_10BTHALF 0x0020
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#define PHY_ANAR_PROTO4 0x0010
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#define PHY_ANAR_PROTO3 0x0008
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#define PHY_ANAR_PROTO2 0x0004
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#define PHY_ANAR_PROTO1 0x0002
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#define PHY_ANAR_PROTO0 0x0001
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/*
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* These are the register definitions for the PHY (physical layer
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* interface chip).
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*/
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/*
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* PHY BMCR Basic Mode Control Register
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*/
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOPBK 0x4000
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#define PHY_BMCR_SPEEDSEL 0x2000
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#define PHY_BMCR_AUTONEGENBL 0x1000
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#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
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#define PHY_BMCR_ISOLATE 0x0400
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#define PHY_BMCR_AUTONEGRSTR 0x0200
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#define PHY_BMCR_DUPLEX 0x0100
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#define PHY_BMCR_COLLTEST 0x0080
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#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
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#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
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#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
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#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
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#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
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#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
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#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
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/*
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* RESET: 1 == software reset, 0 == normal operation
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* Resets status and control registers to default values.
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* Relatches all hardware config values.
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*
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* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
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*
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* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
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* Link speed is selected byt his bit or if auto-negotiation if bit
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* 12 (AUTONEGENBL) is set (in which case the value of this register
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* is ignored).
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*
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* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
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* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
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* determine speed and mode. Should be cleared and then set if PHY configured
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* for no autoneg on startup.
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*
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* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
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*
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* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
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*
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* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
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*
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* COLLTEST: 1 == collision test enabled, 0 == normal operation
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*/
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/*
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* PHY, BMSR Basic Mode Status Register
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*/
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#define PHY_BMSR_100BT4 0x8000
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#define PHY_BMSR_100BTXFULL 0x4000
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#define PHY_BMSR_100BTXHALF 0x2000
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#define PHY_BMSR_10BTFULL 0x1000
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#define PHY_BMSR_10BTHALF 0x0800
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#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
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#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
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#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
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#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
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#define PHY_BMSR_MFPRESUP 0x0040
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#define PHY_BMSR_AUTONEGCOMP 0x0020
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#define PHY_BMSR_REMFAULT 0x0010
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#define PHY_BMSR_CANAUTONEG 0x0008
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#define PHY_BMSR_LINKSTAT 0x0004
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#define PHY_BMSR_JABBER 0x0002
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#define PHY_BMSR_EXTENDED 0x0001
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