592ffb2175
Revert r338177, r338176, r338175, r338174, r338172 After long consultations with re@, core members and mmacy, revert these changes. Followup changes will be made to mark them as deprecated and prent a message about where to find the up-to-date driver. Followup commits will be made to make this clear in the installer. Followup commits to reduce POLA in ways we're still exploring. It's anticipated that after the freeze, this will be removed in 13-current (with the residual of the drm2 code copied to sys/arm/dev/drm2 for the TEGRA port's use w/o the intel or radeon drivers). Due to the impending freeze, there was no formal core vote for this. I've been talking to different core members all day, as well as Matt Macey and Glen Barber. Nobody is completely happy, all are grudgingly going along with this. Work is in progress to mitigate the negative effects as much as possible. Requested by: re@ (gjb, rgrimes)
260 lines
7.8 KiB
C
260 lines
7.8 KiB
C
/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
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* Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
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*/
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/*-
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* Copyright 2000 Gareth Hughes
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* Copyright 2002 Frank C. Earl
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* Copyright 2002-2003 Leif Delgass
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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* Frank C. Earl <fearl@airmail.net>
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* Leif Delgass <ldelgass@retinalburn.net>
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#ifndef __MACH64_DRM_H__
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#define __MACH64_DRM_H__
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (mach64_sarea.h)
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*/
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#ifndef __MACH64_SAREA_DEFINES__
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#define __MACH64_SAREA_DEFINES__
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/* What needs to be changed for the current vertex buffer?
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* GH: We're going to be pedantic about this. We want the card to do as
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* little as possible, so let's avoid having it fetch a whole bunch of
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* register values that don't change all that often, if at all.
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*/
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#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
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#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
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#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
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#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
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#define MACH64_UPLOAD_DP_FOG_CLR 0x0010
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#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
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#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
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#define MACH64_UPLOAD_SETUP_CNTL 0x0080
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#define MACH64_UPLOAD_MISC 0x0100
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#define MACH64_UPLOAD_TEXTURE 0x0200
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#define MACH64_UPLOAD_TEX0IMAGE 0x0400
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#define MACH64_UPLOAD_TEX1IMAGE 0x0800
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#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
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#define MACH64_UPLOAD_CONTEXT 0x00ff
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#define MACH64_UPLOAD_ALL 0x1fff
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/* DMA buffer size
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*/
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#define MACH64_BUFFER_SIZE 16384
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/* Max number of swaps allowed on the ring
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* before the client must wait
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*/
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#define MACH64_MAX_QUEUED_FRAMES 3U
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/* Byte offsets for host blit buffer data
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*/
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#define MACH64_HOSTDATA_BLIT_OFFSET 104
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/* Keep these small for testing.
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*/
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#define MACH64_NR_SAREA_CLIPRECTS 8
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#define MACH64_CARD_HEAP 0
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#define MACH64_AGP_HEAP 1
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#define MACH64_NR_TEX_HEAPS 2
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#define MACH64_NR_TEX_REGIONS 64
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#define MACH64_LOG_TEX_GRANULARITY 16
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#define MACH64_TEX_MAXLEVELS 1
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#define MACH64_NR_CONTEXT_REGS 15
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#define MACH64_NR_TEXTURE_REGS 4
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#endif /* __MACH64_SAREA_DEFINES__ */
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typedef struct {
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unsigned int dst_off_pitch;
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unsigned int z_off_pitch;
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unsigned int z_cntl;
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unsigned int alpha_tst_cntl;
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unsigned int scale_3d_cntl;
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unsigned int sc_left_right;
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unsigned int sc_top_bottom;
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unsigned int dp_fog_clr;
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unsigned int dp_write_mask;
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unsigned int dp_pix_width;
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unsigned int dp_mix;
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unsigned int dp_src;
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unsigned int clr_cmp_cntl;
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unsigned int gui_traj_cntl;
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unsigned int setup_cntl;
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unsigned int tex_size_pitch;
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unsigned int tex_cntl;
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unsigned int secondary_tex_off;
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unsigned int tex_offset;
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} drm_mach64_context_regs_t;
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typedef struct drm_mach64_sarea {
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/* The channel for communication of state information to the kernel
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* on firing a vertex dma buffer.
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*/
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drm_mach64_context_regs_t context_state;
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unsigned int dirty;
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unsigned int vertsize;
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/* The current cliprects, or a subset thereof.
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*/
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struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS];
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unsigned int nbox;
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/* Counters for client-side throttling of rendering clients.
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*/
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unsigned int frames_queued;
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/* Texture memory LRU.
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*/
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struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
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1];
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unsigned int tex_age[MACH64_NR_TEX_HEAPS];
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int ctx_owner;
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} drm_mach64_sarea_t;
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (mach64_common.h)
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*/
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/* Mach64 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_MACH64_INIT 0x00
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#define DRM_MACH64_IDLE 0x01
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#define DRM_MACH64_RESET 0x02
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#define DRM_MACH64_SWAP 0x03
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#define DRM_MACH64_CLEAR 0x04
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#define DRM_MACH64_VERTEX 0x05
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#define DRM_MACH64_BLIT 0x06
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#define DRM_MACH64_FLUSH 0x07
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#define DRM_MACH64_GETPARAM 0x08
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#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
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#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
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#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
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#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
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#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
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#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
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#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
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#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
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#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
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/* Buffer flags for clears
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*/
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#define MACH64_FRONT 0x1
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#define MACH64_BACK 0x2
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#define MACH64_DEPTH 0x4
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/* Primitive types for vertex buffers
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*/
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#define MACH64_PRIM_POINTS 0x00000000
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#define MACH64_PRIM_LINES 0x00000001
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#define MACH64_PRIM_LINE_LOOP 0x00000002
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#define MACH64_PRIM_LINE_STRIP 0x00000003
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#define MACH64_PRIM_TRIANGLES 0x00000004
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#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
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#define MACH64_PRIM_TRIANGLE_FAN 0x00000006
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#define MACH64_PRIM_QUADS 0x00000007
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#define MACH64_PRIM_QUAD_STRIP 0x00000008
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#define MACH64_PRIM_POLYGON 0x00000009
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typedef enum _drm_mach64_dma_mode_t {
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MACH64_MODE_DMA_ASYNC,
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MACH64_MODE_DMA_SYNC,
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MACH64_MODE_MMIO
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} drm_mach64_dma_mode_t;
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typedef struct drm_mach64_init {
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enum {
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DRM_MACH64_INIT_DMA = 0x01,
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DRM_MACH64_CLEANUP_DMA = 0x02
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} func;
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unsigned long sarea_priv_offset;
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int is_pci;
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drm_mach64_dma_mode_t dma_mode;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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unsigned long fb_offset;
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unsigned long mmio_offset;
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unsigned long ring_offset;
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unsigned long buffers_offset;
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unsigned long agp_textures_offset;
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} drm_mach64_init_t;
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typedef struct drm_mach64_clear {
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unsigned int flags;
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int x, y, w, h;
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unsigned int clear_color;
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unsigned int clear_depth;
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} drm_mach64_clear_t;
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typedef struct drm_mach64_vertex {
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int prim;
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void *buf; /* Address of vertex buffer */
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unsigned long used; /* Number of bytes in buffer */
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int discard; /* Client finished with buffer? */
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} drm_mach64_vertex_t;
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typedef struct drm_mach64_blit {
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void *buf;
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int pitch;
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int offset;
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int format;
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unsigned short x, y;
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unsigned short width, height;
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} drm_mach64_blit_t;
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typedef struct drm_mach64_getparam {
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enum {
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MACH64_PARAM_FRAMES_QUEUED = 0x01,
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MACH64_PARAM_IRQ_NR = 0x02
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} param;
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void *value;
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} drm_mach64_getparam_t;
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#endif
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