fab2d1adf6
or not the OS has to wait for RX_RDY or TX_RDY to be set before the OS sets the control code in the control/status register. Looking at the interface design, it seems that RX_RDY and TX_RDY are probably there to protect access to the data register and have nothing to do with the control/status register. Nevertheless, try to take what I think is the more conservative approach and always wait for the appropriate [TR]X_RDY flag to be set before writing any of the WR_NEXT, WR_END, RD_START, or RD_NEXT control codes to the control/status register.
408 lines
9.7 KiB
C
408 lines
9.7 KiB
C
/*-
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* Copyright (c) 2006 IronPort Systems Inc. <ambrisko@ironport.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/condvar.h>
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#include <sys/eventhandler.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/selinfo.h>
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#include <machine/bus.h>
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#ifdef LOCAL_MODULE
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#include <ipmi.h>
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#include <ipmivars.h>
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#else
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#include <sys/ipmi.h>
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#include <dev/ipmi/ipmivars.h>
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#endif
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static void smic_wait_for_tx_okay(struct ipmi_softc *);
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static void smic_wait_for_rx_okay(struct ipmi_softc *);
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static void smic_wait_for_not_busy(struct ipmi_softc *);
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static void smic_set_busy(struct ipmi_softc *);
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static void
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smic_wait_for_tx_okay(struct ipmi_softc *sc)
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{
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int flags;
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do {
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flags = INB(sc, SMIC_FLAGS);
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} while (!(flags & SMIC_STATUS_TX_RDY));
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}
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static void
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smic_wait_for_rx_okay(struct ipmi_softc *sc)
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{
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int flags;
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do {
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flags = INB(sc, SMIC_FLAGS);
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} while (!(flags & SMIC_STATUS_RX_RDY));
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}
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static void
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smic_wait_for_not_busy(struct ipmi_softc *sc)
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{
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int flags;
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do {
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flags = INB(sc, SMIC_FLAGS);
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} while (flags & SMIC_STATUS_BUSY);
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}
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static void
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smic_set_busy(struct ipmi_softc *sc)
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{
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int flags;
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flags = INB(sc, SMIC_FLAGS);
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flags |= SMIC_STATUS_BUSY;
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flags &= ~SMIC_STATUS_RESERVED;
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OUTB(sc, SMIC_FLAGS, flags);
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}
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/*
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* Start a transfer with a WR_START transaction that sends the NetFn/LUN
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* address.
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*/
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static int
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smic_start_write(struct ipmi_softc *sc, u_char data)
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{
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u_char error, status;
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smic_wait_for_not_busy(sc);
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OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_WR_START);
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OUTB(sc, SMIC_DATA, data);
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smic_set_busy(sc);
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smic_wait_for_not_busy(sc);
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status = INB(sc, SMIC_CTL_STS);
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if (status != SMIC_SC_SMS_WR_START) {
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error = INB(sc, SMIC_DATA);
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device_printf(sc->ipmi_dev, "SMIC: Write did not start %02x\n",
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error);
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return (0);
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}
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return (1);
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}
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/*
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* Write a byte in the middle of the message (either the command or one of
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* the data bytes) using a WR_NEXT transaction.
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*/
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static int
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smic_write_next(struct ipmi_softc *sc, u_char data)
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{
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u_char error, status;
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smic_wait_for_tx_okay(sc);
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OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_WR_NEXT);
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OUTB(sc, SMIC_DATA, data);
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smic_set_busy(sc);
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smic_wait_for_not_busy(sc);
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status = INB(sc, SMIC_CTL_STS);
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if (status != SMIC_SC_SMS_WR_NEXT) {
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error = INB(sc, SMIC_DATA);
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device_printf(sc->ipmi_dev, "SMIC: Write did not next %02x\n",
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error);
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return (0);
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}
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return (1);
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}
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/*
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* Write the last byte of a transfer to end the write phase via a WR_END
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* transaction.
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*/
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static int
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smic_write_last(struct ipmi_softc *sc, u_char data)
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{
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u_char error, status;
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smic_wait_for_tx_okay(sc);
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OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_WR_END);
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OUTB(sc, SMIC_DATA, data);
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smic_set_busy(sc);
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smic_wait_for_not_busy(sc);
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status = INB(sc, SMIC_CTL_STS);
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if (status != SMIC_SC_SMS_WR_END) {
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error = INB(sc, SMIC_DATA);
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device_printf(sc->ipmi_dev, "SMIC: Write did not end %02x\n",
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error);
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return (0);
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}
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return (1);
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}
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/*
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* Start the read phase of a transfer with a RD_START transaction.
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*/
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static int
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smic_start_read(struct ipmi_softc *sc, u_char *data)
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{
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u_char error, status;
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smic_wait_for_not_busy(sc);
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smic_wait_for_rx_okay(sc);
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OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_RD_START);
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smic_set_busy(sc);
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smic_wait_for_not_busy(sc);
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status = INB(sc, SMIC_CTL_STS);
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if (status != SMIC_SC_SMS_RD_START) {
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error = INB(sc, SMIC_DATA);
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device_printf(sc->ipmi_dev, "SMIC: Read did not start %02x\n",
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error);
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return (0);
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}
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*data = INB(sc, SMIC_DATA);
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return (1);
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}
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/*
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* Read a byte via a RD_NEXT transaction. If this was the last byte, return
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* 2 rather than 1.
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*/
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static int
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smic_read_byte(struct ipmi_softc *sc, u_char *data)
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{
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u_char error, status;
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smic_wait_for_rx_okay(sc);
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OUTB(sc, SMIC_CTL_STS, SMIC_SC_SMS_RD_NEXT);
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smic_set_busy(sc);
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smic_wait_for_not_busy(sc);
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status = INB(sc, SMIC_CTL_STS);
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if (status != SMIC_SC_SMS_RD_NEXT &&
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status != SMIC_SC_SMS_RD_END) {
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error = INB(sc, SMIC_DATA);
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device_printf(sc->ipmi_dev, "SMIC: Read did not next %02x\n",
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error);
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return (0);
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}
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*data = INB(sc, SMIC_DATA);
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if (status == SMIC_SC_SMS_RD_NEXT)
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return (1);
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else
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return (2);
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}
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/* Complete a transfer via a RD_END transaction after reading the last byte. */
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static int
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smic_read_end(struct ipmi_softc *sc)
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{
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u_char error, status;
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OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_RD_END);
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smic_set_busy(sc);
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smic_wait_for_not_busy(sc);
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status = INB(sc, SMIC_CTL_STS);
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if (status != SMIC_SC_SMS_RDY) {
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error = INB(sc, SMIC_DATA);
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device_printf(sc->ipmi_dev, "SMIC: Read did not end %02x\n",
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error);
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return (0);
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}
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return (1);
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}
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static int
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smic_polled_request(struct ipmi_softc *sc, struct ipmi_request *req)
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{
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u_char *cp, data;
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int i, state;
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/* First, start the message with the address. */
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if (!smic_start_write(sc, req->ir_addr))
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: WRITE_START address: %02x\n",
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req->ir_addr);
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#endif
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if (req->ir_requestlen == 0) {
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/* Send the command as the last byte. */
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if (!smic_write_last(sc, req->ir_command))
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Wrote command: %02x\n",
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req->ir_command);
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#endif
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} else {
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/* Send the command. */
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if (!smic_write_next(sc, req->ir_command))
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Wrote command: %02x\n",
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req->ir_command);
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#endif
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/* Send the payload. */
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cp = req->ir_request;
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for (i = 0; i < req->ir_requestlen - 1; i++) {
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if (!smic_write_next(sc, *cp++))
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Wrote data: %02x\n",
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cp[-1]);
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#endif
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}
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if (!smic_write_last(sc, *cp))
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Write last data: %02x\n",
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*cp);
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#endif
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}
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/* Start the read phase by reading the NetFn/LUN. */
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if (smic_start_read(sc, &data) != 1)
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Read address: %02x\n", data);
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#endif
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if (data != IPMI_REPLY_ADDR(req->ir_addr)) {
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device_printf(sc->ipmi_dev, "SMIC: Reply address mismatch\n");
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return (0);
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}
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/* Read the command. */
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if (smic_read_byte(sc, &data) != 1)
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Read command: %02x\n", data);
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#endif
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if (data != req->ir_command) {
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device_printf(sc->ipmi_dev, "SMIC: Command mismatch\n");
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return (0);
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}
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/* Read the completion code. */
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state = smic_read_byte(sc, &req->ir_compcode);
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if (state == 0)
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return (0);
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Read completion code: %02x\n",
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req->ir_compcode);
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#endif
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/* Finally, read the reply from the BMC. */
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i = 0;
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while (state == 1) {
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state = smic_read_byte(sc, &data);
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if (state == 0)
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return (0);
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if (i < req->ir_replybuflen) {
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req->ir_reply[i] = data;
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: Read data: %02x\n",
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data);
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} else {
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device_printf(sc->ipmi_dev,
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"SMIC: Read short %02x byte %d\n", data, i + 1);
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#endif
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}
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i++;
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}
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/* Terminate the transfer. */
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if (!smic_read_end(sc))
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return (0);
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req->ir_replylen = i;
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: READ finished (%d bytes)\n", i);
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if (req->ir_replybuflen < i)
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#else
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if (req->ir_replybuflen < i && req->ir_replybuflen != 0)
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#endif
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device_printf(sc->ipmi_dev,
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"SMIC: Read short: %zd buffer, %d actual\n",
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req->ir_replybuflen, i);
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return (1);
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}
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static void
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smic_loop(void *arg)
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{
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struct ipmi_softc *sc = arg;
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struct ipmi_request *req;
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int i, ok;
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IPMI_LOCK(sc);
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while ((req = ipmi_dequeue_request(sc)) != NULL) {
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ok = 0;
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for (i = 0; i < 3 && !ok; i++)
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ok = smic_polled_request(sc, req);
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if (ok)
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req->ir_error = 0;
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else
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req->ir_error = EIO;
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ipmi_complete_request(sc, req);
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}
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IPMI_UNLOCK(sc);
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kthread_exit(0);
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}
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static int
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smic_startup(struct ipmi_softc *sc)
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{
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return (kthread_create(smic_loop, sc, &sc->ipmi_kthread, 0, 0,
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"%s: smic", device_get_nameunit(sc->ipmi_dev)));
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}
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int
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ipmi_smic_attach(struct ipmi_softc *sc)
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{
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int flags;
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/* Setup function pointers. */
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sc->ipmi_startup = smic_startup;
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sc->ipmi_enqueue_request = ipmi_polled_enqueue_request;
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/* See if we can talk to the controller. */
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flags = INB(sc, SMIC_FLAGS);
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if (flags == 0xff) {
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device_printf(sc->ipmi_dev, "couldn't find it\n");
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return (ENXIO);
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}
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#ifdef SMIC_DEBUG
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device_printf(sc->ipmi_dev, "SMIC: initial state: %02x\n", flags);
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#endif
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return (0);
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}
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