655 lines
20 KiB
C++
655 lines
20 KiB
C++
//===- ResourcePriorityQueue.cpp - A DFA-oriented priority queue -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ResourcePriorityQueue class, which is a
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// SchedulingPriorityQueue that prioritizes instructions using DFA state to
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// reduce the length of the critical path through the basic block
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// on VLIW platforms.
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// The scheduler is basically a top-down adaptable list scheduler with DFA
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// resource tracking added to the cost function.
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// DFA is queried as a state machine to model "packets/bundles" during
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// schedule. Currently packets/bundles are discarded at the end of
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// scheduling, affecting only order of instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "scheduler"
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#include "llvm/CodeGen/ResourcePriorityQueue.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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static cl::opt<bool> DisableDFASched("disable-dfa-sched", cl::Hidden,
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cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable use of DFA during scheduling"));
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static cl::opt<signed> RegPressureThreshold(
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"dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5),
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cl::desc("Track reg pressure and switch priority to in-depth"));
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ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) :
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Picker(this),
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InstrItins(IS->getTargetLowering()->getTargetMachine().getInstrItineraryData())
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{
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TII = IS->getTargetLowering()->getTargetMachine().getInstrInfo();
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TRI = IS->getTargetLowering()->getTargetMachine().getRegisterInfo();
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TLI = IS->getTargetLowering();
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const TargetMachine &tm = (*IS->MF).getTarget();
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ResourcesModel = tm.getInstrInfo()->CreateTargetScheduleState(&tm,NULL);
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// This hard requirement could be relaxed, but for now
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// do not let it procede.
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assert (ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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unsigned NumRC = TRI->getNumRegClasses();
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RegLimit.resize(NumRC);
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RegPressure.resize(NumRC);
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std::fill(RegLimit.begin(), RegLimit.end(), 0);
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std::fill(RegPressure.begin(), RegPressure.end(), 0);
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I)
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RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, *IS->MF);
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ParallelLiveRanges = 0;
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HorizontalVerticalBalance = 0;
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}
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unsigned
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ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
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unsigned NumberDeps = 0;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl())
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continue;
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SUnit *PredSU = I->getSUnit();
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const SDNode *ScegN = PredSU->getNode();
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if (!ScegN)
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continue;
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// If value is passed to CopyToReg, it is probably
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// live outside BB.
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switch (ScegN->getOpcode()) {
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default: break;
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case ISD::TokenFactor: break;
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case ISD::CopyFromReg: NumberDeps++; break;
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case ISD::CopyToReg: break;
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case ISD::INLINEASM: break;
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}
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if (!ScegN->isMachineOpcode())
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continue;
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for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
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MVT VT = ScegN->getSimpleValueType(i);
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if (TLI->isTypeLegal(VT)
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&& (TLI->getRegClassFor(VT)->getID() == RCId)) {
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NumberDeps++;
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break;
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}
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}
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}
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return NumberDeps;
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}
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unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
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unsigned RCId) {
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unsigned NumberDeps = 0;
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isCtrl())
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continue;
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SUnit *SuccSU = I->getSUnit();
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const SDNode *ScegN = SuccSU->getNode();
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if (!ScegN)
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continue;
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// If value is passed to CopyToReg, it is probably
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// live outside BB.
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switch (ScegN->getOpcode()) {
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default: break;
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case ISD::TokenFactor: break;
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case ISD::CopyFromReg: break;
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case ISD::CopyToReg: NumberDeps++; break;
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case ISD::INLINEASM: break;
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}
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if (!ScegN->isMachineOpcode())
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continue;
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for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
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const SDValue &Op = ScegN->getOperand(i);
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MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
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if (TLI->isTypeLegal(VT)
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&& (TLI->getRegClassFor(VT)->getID() == RCId)) {
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NumberDeps++;
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break;
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}
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}
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}
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return NumberDeps;
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}
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static unsigned numberCtrlDepsInSU(SUnit *SU) {
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unsigned NumberDeps = 0;
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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if (I->isCtrl())
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NumberDeps++;
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return NumberDeps;
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}
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static unsigned numberCtrlPredInSU(SUnit *SU) {
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unsigned NumberDeps = 0;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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if (I->isCtrl())
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NumberDeps++;
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return NumberDeps;
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}
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///
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/// Initialize nodes.
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///
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void ResourcePriorityQueue::initNodes(std::vector<SUnit> &sunits) {
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SUnits = &sunits;
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NumNodesSolelyBlocking.resize(SUnits->size(), 0);
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for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
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SUnit *SU = &(*SUnits)[i];
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initNumRegDefsLeft(SU);
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SU->NodeQueueId = 0;
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}
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}
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/// This heuristic is used if DFA scheduling is not desired
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/// for some VLIW platform.
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bool resource_sort::operator()(const SUnit *LHS, const SUnit *RHS) const {
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// The isScheduleHigh flag allows nodes with wraparound dependencies that
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// cannot easily be modeled as edges with latencies to be scheduled as
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// soon as possible in a top-down schedule.
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if (LHS->isScheduleHigh && !RHS->isScheduleHigh)
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return false;
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if (!LHS->isScheduleHigh && RHS->isScheduleHigh)
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return true;
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unsigned LHSNum = LHS->NodeNum;
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unsigned RHSNum = RHS->NodeNum;
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// The most important heuristic is scheduling the critical path.
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unsigned LHSLatency = PQ->getLatency(LHSNum);
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unsigned RHSLatency = PQ->getLatency(RHSNum);
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if (LHSLatency < RHSLatency) return true;
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if (LHSLatency > RHSLatency) return false;
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// After that, if two nodes have identical latencies, look to see if one will
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// unblock more other nodes than the other.
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unsigned LHSBlocked = PQ->getNumSolelyBlockNodes(LHSNum);
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unsigned RHSBlocked = PQ->getNumSolelyBlockNodes(RHSNum);
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if (LHSBlocked < RHSBlocked) return true;
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if (LHSBlocked > RHSBlocked) return false;
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// Finally, just to provide a stable ordering, use the node number as a
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// deciding factor.
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return LHSNum < RHSNum;
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}
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/// getSingleUnscheduledPred - If there is exactly one unscheduled predecessor
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/// of SU, return it, otherwise return null.
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SUnit *ResourcePriorityQueue::getSingleUnscheduledPred(SUnit *SU) {
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SUnit *OnlyAvailablePred = 0;
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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SUnit &Pred = *I->getSUnit();
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if (!Pred.isScheduled) {
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// We found an available, but not scheduled, predecessor. If it's the
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// only one we have found, keep track of it... otherwise give up.
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if (OnlyAvailablePred && OnlyAvailablePred != &Pred)
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return 0;
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OnlyAvailablePred = &Pred;
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}
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}
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return OnlyAvailablePred;
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}
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void ResourcePriorityQueue::push(SUnit *SU) {
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// Look at all of the successors of this node. Count the number of nodes that
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// this node is the sole unscheduled node for.
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unsigned NumNodesBlocking = 0;
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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if (getSingleUnscheduledPred(I->getSUnit()) == SU)
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++NumNodesBlocking;
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NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
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Queue.push_back(SU);
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}
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/// Check if scheduling of this SU is possible
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/// in the current packet.
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bool ResourcePriorityQueue::isResourceAvailable(SUnit *SU) {
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if (!SU || !SU->getNode())
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return false;
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// If this is a compound instruction,
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// it is likely to be a call. Do not delay it.
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if (SU->getNode()->getGluedNode())
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return true;
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// First see if the pipeline could receive this instruction
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// in the current cycle.
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if (SU->getNode()->isMachineOpcode())
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switch (SU->getNode()->getMachineOpcode()) {
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default:
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if (!ResourcesModel->canReserveResources(&TII->get(
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SU->getNode()->getMachineOpcode())))
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return false;
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case TargetOpcode::EXTRACT_SUBREG:
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case TargetOpcode::INSERT_SUBREG:
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case TargetOpcode::SUBREG_TO_REG:
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case TargetOpcode::REG_SEQUENCE:
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case TargetOpcode::IMPLICIT_DEF:
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break;
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}
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// Now see if there are no other dependencies
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// to instructions alredy in the packet.
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for (unsigned i = 0, e = Packet.size(); i != e; ++i)
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for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(),
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E = Packet[i]->Succs.end(); I != E; ++I) {
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// Since we do not add pseudos to packets, might as well
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// ignor order deps.
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if (I->isCtrl())
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continue;
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if (I->getSUnit() == SU)
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return false;
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}
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return true;
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}
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/// Keep track of available resources.
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void ResourcePriorityQueue::reserveResources(SUnit *SU) {
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// If this SU does not fit in the packet
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// start a new one.
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if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) {
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ResourcesModel->clearResources();
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Packet.clear();
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}
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if (SU->getNode() && SU->getNode()->isMachineOpcode()) {
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switch (SU->getNode()->getMachineOpcode()) {
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default:
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ResourcesModel->reserveResources(&TII->get(
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SU->getNode()->getMachineOpcode()));
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break;
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case TargetOpcode::EXTRACT_SUBREG:
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case TargetOpcode::INSERT_SUBREG:
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case TargetOpcode::SUBREG_TO_REG:
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case TargetOpcode::REG_SEQUENCE:
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case TargetOpcode::IMPLICIT_DEF:
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break;
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}
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Packet.push_back(SU);
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}
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// Forcefully end packet for PseudoOps.
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else {
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ResourcesModel->clearResources();
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Packet.clear();
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}
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// If packet is now full, reset the state so in the next cycle
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// we start fresh.
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if (Packet.size() >= InstrItins->SchedModel->IssueWidth) {
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ResourcesModel->clearResources();
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Packet.clear();
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}
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}
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signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
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signed RegBalance = 0;
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if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
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return RegBalance;
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// Gen estimate.
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for (unsigned i = 0, e = SU->getNode()->getNumValues(); i != e; ++i) {
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MVT VT = SU->getNode()->getSimpleValueType(i);
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if (TLI->isTypeLegal(VT)
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&& TLI->getRegClassFor(VT)
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&& TLI->getRegClassFor(VT)->getID() == RCId)
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RegBalance += numberRCValSuccInSU(SU, RCId);
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}
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// Kill estimate.
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for (unsigned i = 0, e = SU->getNode()->getNumOperands(); i != e; ++i) {
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const SDValue &Op = SU->getNode()->getOperand(i);
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MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
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if (isa<ConstantSDNode>(Op.getNode()))
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continue;
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if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT)
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&& TLI->getRegClassFor(VT)->getID() == RCId)
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RegBalance -= numberRCValPredInSU(SU, RCId);
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}
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return RegBalance;
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}
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/// Estimates change in reg pressure from this SU.
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/// It is achieved by trivial tracking of defined
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/// and used vregs in dependent instructions.
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/// The RawPressure flag makes this function to ignore
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/// existing reg file sizes, and report raw def/use
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/// balance.
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signed ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {
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signed RegBalance = 0;
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if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
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return RegBalance;
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if (RawPressure) {
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I) {
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const TargetRegisterClass *RC = *I;
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RegBalance += rawRegPressureDelta(SU, RC->getID());
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}
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}
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else {
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I) {
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const TargetRegisterClass *RC = *I;
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if ((RegPressure[RC->getID()] +
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rawRegPressureDelta(SU, RC->getID()) > 0) &&
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(RegPressure[RC->getID()] +
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rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()]))
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RegBalance += rawRegPressureDelta(SU, RC->getID());
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}
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}
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return RegBalance;
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}
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// Constants used to denote relative importance of
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// heuristic components for cost computation.
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static const unsigned PriorityOne = 200;
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static const unsigned PriorityTwo = 50;
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static const unsigned PriorityThree = 15;
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static const unsigned PriorityFour = 5;
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static const unsigned ScaleOne = 20;
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static const unsigned ScaleTwo = 10;
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static const unsigned ScaleThree = 5;
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static const unsigned FactorOne = 2;
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/// Returns single number reflecting benefit of scheduling SU
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/// in the current cycle.
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signed ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {
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// Initial trivial priority.
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signed ResCount = 1;
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// Do not waste time on a node that is already scheduled.
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if (SU->isScheduled)
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return ResCount;
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// Forced priority is high.
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if (SU->isScheduleHigh)
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ResCount += PriorityOne;
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// Adaptable scheduling
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// A small, but very parallel
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// region, where reg pressure is an issue.
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if (HorizontalVerticalBalance > RegPressureThreshold) {
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// Critical path first
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ResCount += (SU->getHeight() * ScaleTwo);
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// If resources are available for it, multiply the
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// chance of scheduling.
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if (isResourceAvailable(SU))
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ResCount <<= FactorOne;
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// Consider change to reg pressure from scheduling
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// this SU.
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ResCount -= (regPressureDelta(SU,true) * ScaleOne);
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}
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// Default heuristic, greeady and
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// critical path driven.
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else {
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// Critical path first.
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ResCount += (SU->getHeight() * ScaleTwo);
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// Now see how many instructions is blocked by this SU.
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ResCount += (NumNodesSolelyBlocking[SU->NodeNum] * ScaleTwo);
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// If resources are available for it, multiply the
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// chance of scheduling.
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if (isResourceAvailable(SU))
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ResCount <<= FactorOne;
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ResCount -= (regPressureDelta(SU) * ScaleTwo);
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}
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// These are platform specific things.
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// Will need to go into the back end
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// and accessed from here via a hook.
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for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
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if (N->isMachineOpcode()) {
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const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
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if (TID.isCall())
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ResCount += (PriorityTwo + (ScaleThree*N->getNumValues()));
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}
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else
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switch (N->getOpcode()) {
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default: break;
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case ISD::TokenFactor:
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case ISD::CopyFromReg:
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case ISD::CopyToReg:
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ResCount += PriorityFour;
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break;
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case ISD::INLINEASM:
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ResCount += PriorityThree;
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break;
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}
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}
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return ResCount;
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}
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/// Main resource tracking point.
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void ResourcePriorityQueue::scheduledNode(SUnit *SU) {
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// Use NULL entry as an event marker to reset
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// the DFA state.
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if (!SU) {
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ResourcesModel->clearResources();
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Packet.clear();
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return;
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}
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const SDNode *ScegN = SU->getNode();
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// Update reg pressure tracking.
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// First update current node.
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if (ScegN->isMachineOpcode()) {
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// Estimate generated regs.
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for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
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MVT VT = ScegN->getSimpleValueType(i);
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if (TLI->isTypeLegal(VT)) {
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const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
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if (RC)
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RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID());
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}
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}
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// Estimate killed regs.
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for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
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const SDValue &Op = ScegN->getOperand(i);
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MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
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if (TLI->isTypeLegal(VT)) {
|
|
const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
|
|
if (RC) {
|
|
if (RegPressure[RC->getID()] >
|
|
(numberRCValPredInSU(SU, RC->getID())))
|
|
RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID());
|
|
else RegPressure[RC->getID()] = 0;
|
|
}
|
|
}
|
|
}
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl() || (I->getSUnit()->NumRegDefsLeft == 0))
|
|
continue;
|
|
--I->getSUnit()->NumRegDefsLeft;
|
|
}
|
|
}
|
|
|
|
// Reserve resources for this SU.
|
|
reserveResources(SU);
|
|
|
|
// Adjust number of parallel live ranges.
|
|
// Heuristic is simple - node with no data successors reduces
|
|
// number of live ranges. All others, increase it.
|
|
unsigned NumberNonControlDeps = 0;
|
|
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
adjustPriorityOfUnscheduledPreds(I->getSUnit());
|
|
if (!I->isCtrl())
|
|
NumberNonControlDeps++;
|
|
}
|
|
|
|
if (!NumberNonControlDeps) {
|
|
if (ParallelLiveRanges >= SU->NumPreds)
|
|
ParallelLiveRanges -= SU->NumPreds;
|
|
else
|
|
ParallelLiveRanges = 0;
|
|
|
|
}
|
|
else
|
|
ParallelLiveRanges += SU->NumRegDefsLeft;
|
|
|
|
// Track parallel live chains.
|
|
HorizontalVerticalBalance += (SU->Succs.size() - numberCtrlDepsInSU(SU));
|
|
HorizontalVerticalBalance -= (SU->Preds.size() - numberCtrlPredInSU(SU));
|
|
}
|
|
|
|
void ResourcePriorityQueue::initNumRegDefsLeft(SUnit *SU) {
|
|
unsigned NodeNumDefs = 0;
|
|
for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
|
|
if (N->isMachineOpcode()) {
|
|
const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
|
|
// No register need be allocated for this.
|
|
if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
|
|
NodeNumDefs = 0;
|
|
break;
|
|
}
|
|
NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs());
|
|
}
|
|
else
|
|
switch(N->getOpcode()) {
|
|
default: break;
|
|
case ISD::CopyFromReg:
|
|
NodeNumDefs++;
|
|
break;
|
|
case ISD::INLINEASM:
|
|
NodeNumDefs++;
|
|
break;
|
|
}
|
|
|
|
SU->NumRegDefsLeft = NodeNumDefs;
|
|
}
|
|
|
|
/// adjustPriorityOfUnscheduledPreds - One of the predecessors of SU was just
|
|
/// scheduled. If SU is not itself available, then there is at least one
|
|
/// predecessor node that has not been scheduled yet. If SU has exactly ONE
|
|
/// unscheduled predecessor, we want to increase its priority: it getting
|
|
/// scheduled will make this node available, so it is better than some other
|
|
/// node of the same priority that will not make a node available.
|
|
void ResourcePriorityQueue::adjustPriorityOfUnscheduledPreds(SUnit *SU) {
|
|
if (SU->isAvailable) return; // All preds scheduled.
|
|
|
|
SUnit *OnlyAvailablePred = getSingleUnscheduledPred(SU);
|
|
if (OnlyAvailablePred == 0 || !OnlyAvailablePred->isAvailable)
|
|
return;
|
|
|
|
// Okay, we found a single predecessor that is available, but not scheduled.
|
|
// Since it is available, it must be in the priority queue. First remove it.
|
|
remove(OnlyAvailablePred);
|
|
|
|
// Reinsert the node into the priority queue, which recomputes its
|
|
// NumNodesSolelyBlocking value.
|
|
push(OnlyAvailablePred);
|
|
}
|
|
|
|
|
|
/// Main access point - returns next instructions
|
|
/// to be placed in scheduling sequence.
|
|
SUnit *ResourcePriorityQueue::pop() {
|
|
if (empty())
|
|
return 0;
|
|
|
|
std::vector<SUnit *>::iterator Best = Queue.begin();
|
|
if (!DisableDFASched) {
|
|
signed BestCost = SUSchedulingCost(*Best);
|
|
for (std::vector<SUnit *>::iterator I = llvm::next(Queue.begin()),
|
|
E = Queue.end(); I != E; ++I) {
|
|
|
|
if (SUSchedulingCost(*I) > BestCost) {
|
|
BestCost = SUSchedulingCost(*I);
|
|
Best = I;
|
|
}
|
|
}
|
|
}
|
|
// Use default TD scheduling mechanism.
|
|
else {
|
|
for (std::vector<SUnit *>::iterator I = llvm::next(Queue.begin()),
|
|
E = Queue.end(); I != E; ++I)
|
|
if (Picker(*Best, *I))
|
|
Best = I;
|
|
}
|
|
|
|
SUnit *V = *Best;
|
|
if (Best != prior(Queue.end()))
|
|
std::swap(*Best, Queue.back());
|
|
|
|
Queue.pop_back();
|
|
|
|
return V;
|
|
}
|
|
|
|
|
|
void ResourcePriorityQueue::remove(SUnit *SU) {
|
|
assert(!Queue.empty() && "Queue is empty!");
|
|
std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(), SU);
|
|
if (I != prior(Queue.end()))
|
|
std::swap(*I, Queue.back());
|
|
|
|
Queue.pop_back();
|
|
}
|
|
|
|
|
|
#ifdef NDEBUG
|
|
void ResourcePriorityQueue::dump(ScheduleDAG *DAG) const {}
|
|
#else
|
|
void ResourcePriorityQueue::dump(ScheduleDAG *DAG) const {
|
|
ResourcePriorityQueue q = *this;
|
|
while (!q.empty()) {
|
|
SUnit *su = q.pop();
|
|
dbgs() << "Height " << su->getHeight() << ": ";
|
|
su->dump(DAG);
|
|
}
|
|
}
|
|
#endif
|