348 lines
7.9 KiB
C
348 lines
7.9 KiB
C
/*-
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* Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <arm64/coresight/coresight.h>
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#include <arm64/coresight/coresight_tmc.h>
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#include "coresight_if.h"
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#define TMC_DEBUG
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#undef TMC_DEBUG
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#ifdef TMC_DEBUG
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#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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static struct resource_spec tmc_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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tmc_start(device_t dev)
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{
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struct tmc_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN)
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return (-1);
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/* Enable TMC */
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bus_write_4(sc->res, TMC_CTL, CTL_TRACECAPTEN);
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if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)
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panic("Not enabled\n");
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do {
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reg = bus_read_4(sc->res, TMC_STS);
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} while ((reg & STS_TMCREADY) == 1);
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if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)
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panic("Not enabled\n");
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return (0);
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}
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static int
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tmc_stop(device_t dev)
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{
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struct tmc_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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reg = bus_read_4(sc->res, TMC_CTL);
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reg &= ~CTL_TRACECAPTEN;
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bus_write_4(sc->res, TMC_CTL, reg);
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do {
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reg = bus_read_4(sc->res, TMC_STS);
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} while ((reg & STS_TMCREADY) == 1);
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return (0);
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}
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static int
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tmc_configure_etf(device_t dev)
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{
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struct tmc_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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do {
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reg = bus_read_4(sc->res, TMC_STS);
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} while ((reg & STS_TMCREADY) == 0);
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bus_write_4(sc->res, TMC_MODE, MODE_HW_FIFO);
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bus_write_4(sc->res, TMC_FFCR, FFCR_EN_FMT | FFCR_EN_TI);
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tmc_start(dev);
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dprintf("%s: STS %x, CTL %x, RSZ %x, RRP %x, RWP %x, "
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"LBUFLEVEL %x, CBUFLEVEL %x\n", __func__,
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bus_read_4(sc->res, TMC_STS),
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bus_read_4(sc->res, TMC_CTL),
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bus_read_4(sc->res, TMC_RSZ),
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bus_read_4(sc->res, TMC_RRP),
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bus_read_4(sc->res, TMC_RWP),
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bus_read_4(sc->res, TMC_CBUFLEVEL),
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bus_read_4(sc->res, TMC_LBUFLEVEL));
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return (0);
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}
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static int
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tmc_configure_etr(device_t dev, struct endpoint *endp,
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struct coresight_event *event)
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{
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struct tmc_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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tmc_stop(dev);
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do {
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reg = bus_read_4(sc->res, TMC_STS);
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} while ((reg & STS_TMCREADY) == 0);
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/* Configure TMC */
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bus_write_4(sc->res, TMC_MODE, MODE_CIRCULAR_BUFFER);
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reg = AXICTL_PROT_CTRL_BIT1;
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reg |= AXICTL_WRBURSTLEN_16;
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/*
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* SG operation is broken on DragonBoard 410c
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* reg |= AXICTL_SG_MODE;
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*/
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reg |= AXICTL_AXCACHE_OS;
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bus_write_4(sc->res, TMC_AXICTL, reg);
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reg = FFCR_EN_FMT | FFCR_EN_TI | FFCR_FON_FLIN |
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FFCR_FON_TRIG_EVT | FFCR_TRIGON_TRIGIN;
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bus_write_4(sc->res, TMC_FFCR, reg);
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bus_write_4(sc->res, TMC_TRG, 8);
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bus_write_4(sc->res, TMC_DBALO, event->etr.low);
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bus_write_4(sc->res, TMC_DBAHI, event->etr.high);
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bus_write_4(sc->res, TMC_RSZ, event->etr.bufsize / 4);
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bus_write_4(sc->res, TMC_RRP, event->etr.low);
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bus_write_4(sc->res, TMC_RWP, event->etr.low);
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reg = bus_read_4(sc->res, TMC_STS);
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reg &= ~STS_FULL;
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bus_write_4(sc->res, TMC_STS, reg);
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tmc_start(dev);
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return (0);
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}
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static int
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tmc_init(device_t dev)
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{
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struct tmc_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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/* Unlock Coresight */
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bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
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/* Unlock TMC */
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bus_write_4(sc->res, TMC_LAR, CORESIGHT_UNLOCK);
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reg = bus_read_4(sc->res, TMC_DEVID);
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reg &= DEVID_CONFIGTYPE_M;
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switch (reg) {
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case DEVID_CONFIGTYPE_ETR:
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sc->dev_type = CORESIGHT_ETR;
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dprintf(dev, "ETR configuration found\n");
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break;
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case DEVID_CONFIGTYPE_ETF:
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sc->dev_type = CORESIGHT_ETF;
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dprintf(dev, "ETF configuration found\n");
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if (sc->etf_configured == false) {
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tmc_configure_etf(dev);
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sc->etf_configured = true;
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}
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break;
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default:
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sc->dev_type = CORESIGHT_UNKNOWN;
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break;
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}
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return (0);
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}
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static int
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tmc_enable(device_t dev, struct endpoint *endp,
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struct coresight_event *event)
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{
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struct tmc_softc *sc;
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uint32_t nev;
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sc = device_get_softc(dev);
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if (sc->dev_type == CORESIGHT_ETF)
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return (0);
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KASSERT(sc->dev_type == CORESIGHT_ETR,
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("Wrong dev_type"));
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/*
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* Multiple CPUs can call this same time.
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* We allow only one running configuration.
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*/
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if (event->etr.flags & ETR_FLAG_ALLOCATE) {
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event->etr.flags &= ~ETR_FLAG_ALLOCATE;
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nev = atomic_fetchadd_int(&sc->nev, 1);
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if (nev == 0) {
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sc->event = event;
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tmc_stop(dev);
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tmc_configure_etr(dev, endp, event);
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tmc_start(dev);
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}
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}
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return (0);
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}
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static void
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tmc_disable(device_t dev, struct endpoint *endp,
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struct coresight_event *event)
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{
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struct tmc_softc *sc;
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uint32_t nev;
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sc = device_get_softc(dev);
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/* ETF configuration is static */
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if (sc->dev_type == CORESIGHT_ETF)
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return;
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KASSERT(sc->dev_type == CORESIGHT_ETR, ("Wrong dev_type"));
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if (event->etr.flags & ETR_FLAG_RELEASE) {
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event->etr.flags &= ~ETR_FLAG_RELEASE;
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nev = atomic_fetchadd_int(&sc->nev, -1);
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if (nev == 1) {
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tmc_stop(dev);
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sc->event = NULL;
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}
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}
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}
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static int
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tmc_read(device_t dev, struct endpoint *endp,
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struct coresight_event *event)
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{
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struct tmc_softc *sc;
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uint32_t cur_ptr;
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sc = device_get_softc(dev);
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if (sc->dev_type == CORESIGHT_ETF)
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return (0);
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/*
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* Ensure the event we are reading information for
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* is currently configured one.
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*/
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if (sc->event != event)
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return (0);
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if (bus_read_4(sc->res, TMC_STS) & STS_FULL) {
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event->etr.offset = 0;
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event->etr.cycle++;
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tmc_stop(dev);
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tmc_start(dev);
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} else {
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cur_ptr = bus_read_4(sc->res, TMC_RWP);
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event->etr.offset = (cur_ptr - event->etr.low);
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}
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return (0);
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}
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int
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tmc_attach(device_t dev)
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{
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struct coresight_desc desc;
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struct tmc_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, tmc_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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desc.pdata = sc->pdata;
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desc.dev = dev;
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desc.dev_type = CORESIGHT_TMC;
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coresight_register(&desc);
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return (0);
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}
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static device_method_t tmc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_attach, tmc_attach),
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/* Coresight interface */
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DEVMETHOD(coresight_init, tmc_init),
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DEVMETHOD(coresight_enable, tmc_enable),
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DEVMETHOD(coresight_disable, tmc_disable),
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DEVMETHOD(coresight_read, tmc_read),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(tmc, tmc_driver, tmc_methods, sizeof(struct tmc_softc));
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