264 lines
7.5 KiB
C
264 lines
7.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/fdt/simple_mfd.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/extres/syscon/syscon.h>
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#include <dev/extres/phy/phy.h>
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#include <contrib/device-tree/include/dt-bindings/phy/phy.h>
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#include "syscon_if.h"
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#include "phydev_if.h"
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#include "phynode_if.h"
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#define GRF_PCIE30PHY_CON1 0x04
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#define GRF_PCIE30PHY_CON4 0x10
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#define GRF_PCIE30PHY_CON5 0x14
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#define GRF_PCIE30PHY_CON6 0x18
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#define GRF_BIFURCATION_LANE_1 0
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#define GRF_BIFURCATION_LANE_2 1
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#define GRF_PCIE30PHY_WR_EN (0xf << 16)
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#define GRF_PCIE30PHY_CON9 0x24
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#define GRF_PCIE30PHY_DA_OCM_MASK (1 << (15 + 16))
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#define GRF_PCIE30PHY_DA_OCM ((1 << 15) | GRF_PCIE30PHY_DA_OCM_MASK)
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#define GRF_PCIE30PHY_STATUS0 0x80
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#define SRAM_INIT_DONE (1 << 14)
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static struct ofw_compat_data compat_data[] = {
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{"rockchip,rk3568-pcie3-phy", 1},
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{NULL, 0}
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};
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struct rk3568_pciephy_softc {
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device_t dev;
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phandle_t node;
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struct resource *mem;
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struct phynode *phynode;
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struct syscon *phy_grf;
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clk_t refclk_m;
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clk_t refclk_n;
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clk_t pclk;
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hwreset_t phy_reset;
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};
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static void
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rk3568_pciephy_bifurcate(device_t dev, int control, uint32_t lane)
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{
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struct rk3568_pciephy_softc *sc = device_get_softc(dev);
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switch (lane) {
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case 0:
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SYSCON_WRITE_4(sc->phy_grf, control, GRF_PCIE30PHY_WR_EN);
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return;
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case 1:
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SYSCON_WRITE_4(sc->phy_grf, control,
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GRF_PCIE30PHY_WR_EN | GRF_BIFURCATION_LANE_1);
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break;
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case 2:
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SYSCON_WRITE_4(sc->phy_grf, control,
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GRF_PCIE30PHY_WR_EN | GRF_BIFURCATION_LANE_2);
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break;
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default:
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device_printf(dev, "Illegal lane %d\n", lane);
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return;
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}
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if (bootverbose)
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device_printf(dev, "lane %d @ pcie3x%d\n", lane,
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(control == GRF_PCIE30PHY_CON5) ? 1 : 2);
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}
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/* PHY class and methods */
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static int
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rk3568_pciephy_enable(struct phynode *phynode, bool enable)
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{
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device_t dev = phynode_get_device(phynode);
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struct rk3568_pciephy_softc *sc = device_get_softc(dev);
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int count;
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if (enable) {
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/* Pull PHY out of reset */
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hwreset_deassert(sc->phy_reset);
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/* Poll for SRAM loaded and ready */
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for (count = 100; count; count--) {
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if (SYSCON_READ_4(sc->phy_grf, GRF_PCIE30PHY_STATUS0) &
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SRAM_INIT_DONE)
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break;
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DELAY(10000);
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if (count == 0) {
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device_printf(dev, "SRAM init timeout!\n");
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return (ENXIO);
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}
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}
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}
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return (0);
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}
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static phynode_method_t rk3568_pciephy_phynode_methods[] = {
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PHYNODEMETHOD(phynode_enable, rk3568_pciephy_enable),
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PHYNODEMETHOD_END
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};
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DEFINE_CLASS_1(rk3568_pciephy_phynode, rk3568_pciephy_phynode_class,
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rk3568_pciephy_phynode_methods, 0, phynode_class);
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/* Device class and methods */
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static int
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rk3568_pciephy_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "RockChip PCIe PHY");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rk3568_pciephy_attach(device_t dev)
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{
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struct rk3568_pciephy_softc *sc = device_get_softc(dev);
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struct phynode_init_def phy_init;
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struct phynode *phynode;
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uint32_t data_lanes[2] = { 0, 0 };
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int rid = 0;
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sc->dev = dev;
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sc->node = ofw_bus_get_node(dev);
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/* Get memory resource */
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if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE))) {
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device_printf(dev, "Cannot allocate memory resources\n");
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return (ENXIO);
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}
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/* Get syncons handle */
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if (OF_hasprop(sc->node, "rockchip,phy-grf") &&
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syscon_get_by_ofw_property(dev, sc->node, "rockchip,phy-grf",
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&sc->phy_grf))
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return (ENXIO);
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/* Get & enable clocks */
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if (clk_get_by_ofw_name(dev, 0, "refclk_m", &sc->refclk_m)) {
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device_printf(dev, "getting refclk_m failed\n");
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return (ENXIO);
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}
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if (clk_enable(sc->refclk_m))
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device_printf(dev, "enable refclk_m failed\n");
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if (clk_get_by_ofw_name(dev, 0, "refclk_n", &sc->refclk_n)) {
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device_printf(dev, "getting refclk_n failed\n");
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return (ENXIO);
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}
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if (clk_enable(sc->refclk_n))
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device_printf(dev, "enable refclk_n failed\n");
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if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk)) {
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device_printf(dev, "getting pclk failed\n");
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return (ENXIO);
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}
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if (clk_enable(sc->pclk))
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device_printf(dev, "enable pclk failed\n");
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/* Get & assert reset */
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if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) {
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device_printf(dev, "Cannot get reset\n");
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} else
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hwreset_assert(sc->phy_reset);
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/* Set RC/EP mode not implemented yet (RC mode only) */
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/* Set bifurcation according to "data-lanes" entry */
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if (OF_hasprop(sc->node, "data-lanes")) {
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OF_getencprop(sc->node, "data-lanes", data_lanes,
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sizeof(data_lanes));
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} else
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if (bootverbose)
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device_printf(dev, "lane 1 & 2 @pcie3x2\n");
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/* Deassert PCIe PMA output clamp mode */
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SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
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/* Configure PHY HW accordingly */
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rk3568_pciephy_bifurcate(dev, GRF_PCIE30PHY_CON5, data_lanes[0]);
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rk3568_pciephy_bifurcate(dev, GRF_PCIE30PHY_CON6, data_lanes[1]);
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if (data_lanes[0] || data_lanes[1])
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SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1,
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GRF_PCIE30PHY_DA_OCM);
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else
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SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1,
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GRF_PCIE30PHY_DA_OCM_MASK);
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bzero(&phy_init, sizeof(phy_init));
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phy_init.id = PHY_NONE;
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phy_init.ofw_node = sc->node;
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if (!(phynode = phynode_create(dev, &rk3568_pciephy_phynode_class,
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&phy_init))) {
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device_printf(dev, "failed to create pciephy PHY\n");
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return (ENXIO);
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}
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if (!phynode_register(phynode)) {
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device_printf(dev, "failed to register pciephy PHY\n");
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return (ENXIO);
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}
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sc->phynode = phynode;
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return (0);
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}
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static device_method_t rk3568_pciephy_methods[] = {
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DEVMETHOD(device_probe, rk3568_pciephy_probe),
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DEVMETHOD(device_attach, rk3568_pciephy_attach),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(rk3568_pciephy, rk3568_pciephy_driver, rk3568_pciephy_methods,
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sizeof(struct simple_mfd_softc), simple_mfd_driver);
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EARLY_DRIVER_MODULE(rk3568_pciephy, simplebus, rk3568_pciephy_driver,
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0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);
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