399 lines
10 KiB
C
399 lines
10 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
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* Copyright (c) 2019 Brandon Bergren <git@bdragon.rtk0.net>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/resource.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include "pwmbus_if.h"
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/* Register offsets. */
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#define RK_PWM_COUNTER 0x00
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#define RK_PWM_PERIOD 0x04
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#define RK_PWM_DUTY 0x08
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#define RK_PWM_CTRL 0x0c
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#define SET(reg,mask,val) reg = ((reg & ~mask) | val)
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#define RK_PWM_CTRL_ENABLE_MASK (1 << 0)
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#define RK_PWM_CTRL_ENABLED (1 << 0)
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#define RK_PWM_CTRL_DISABLED (0)
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#define RK_PWM_CTRL_MODE_MASK (3 << 1)
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#define RK_PWM_CTRL_MODE_ONESHOT (0)
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#define RK_PWM_CTRL_MODE_CONTINUOUS (1 << 1)
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#define RK_PWM_CTRL_MODE_CAPTURE (1 << 2)
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#define RK_PWM_CTRL_DUTY_MASK (1 << 3)
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#define RK_PWM_CTRL_DUTY_POSITIVE (1 << 3)
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#define RK_PWM_CTRL_DUTY_NEGATIVE (0)
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#define RK_PWM_CTRL_INACTIVE_MASK (1 << 4)
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#define RK_PWM_CTRL_INACTIVE_POSITIVE (1 << 4)
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#define RK_PWM_CTRL_INACTIVE_NEGATIVE (0)
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/* PWM Output Alignment */
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#define RK_PWM_CTRL_ALIGN_MASK (1 << 5)
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#define RK_PWM_CTRL_ALIGN_CENTER (1 << 5)
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#define RK_PWM_CTRL_ALIGN_LEFT (0)
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/* Low power mode: disable prescaler when inactive */
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#define RK_PWM_CTRL_LP_MASK (1 << 8)
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#define RK_PWM_CTRL_LP_ENABLE (1 << 8)
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#define RK_PWM_CTRL_LP_DISABLE (0)
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/* Clock source: bypass the scaler or not */
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#define RK_PWM_CTRL_CLOCKSRC_MASK (1 << 9)
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#define RK_PWM_CTRL_CLOCKSRC_NONSCALED (0)
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#define RK_PWM_CTRL_CLOCKSRC_SCALED (1 << 9)
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#define RK_PWM_CTRL_PRESCALE_MASK (7 << 12)
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#define RK_PWM_CTRL_PRESCALE_SHIFT 12
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#define RK_PWM_CTRL_SCALE_MASK (0xFF << 16)
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#define RK_PWM_CTRL_SCALE_SHIFT 16
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#define RK_PWM_CTRL_REPEAT_MASK (0xFF << 24)
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#define RK_PWM_CTRL_REPEAT_SHIFT 24
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#define NS_PER_SEC 1000000000
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static struct ofw_compat_data compat_data[] = {
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{ "rockchip,rk3288-pwm", 1 },
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{ "rockchip,rk3399-pwm", 1 },
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{ NULL, 0 }
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};
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static struct resource_spec rk_pwm_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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struct rk_pwm_softc {
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device_t dev;
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device_t busdev;
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clk_t clk;
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struct resource *res;
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uint64_t clk_freq;
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unsigned int period;
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unsigned int duty;
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uint32_t flags;
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uint8_t prescaler;
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uint8_t scaler;
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bool using_scaler;
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bool enabled;
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};
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#define RK_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))
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#define RK_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
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static int rk_pwm_probe(device_t dev);
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static int rk_pwm_attach(device_t dev);
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static int rk_pwm_detach(device_t dev);
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static int
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rk_pwm_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Rockchip PWM");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rk_pwm_attach(device_t dev)
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{
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struct rk_pwm_softc *sc;
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phandle_t node;
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uint64_t clk_freq;
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uint32_t reg;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
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if (error != 0) {
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device_printf(dev, "cannot get clock\n");
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goto fail;
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}
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error = clk_enable(sc->clk);
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if (error != 0) {
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device_printf(dev, "cannot enable clock\n");
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goto fail;
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}
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error = clk_get_freq(sc->clk, &sc->clk_freq);
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if (error != 0) {
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device_printf(dev, "cannot get base frequency\n");
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goto fail;
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}
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if (bus_alloc_resources(dev, rk_pwm_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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error = ENXIO;
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goto fail;
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}
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/* Read the configuration left by U-Boot */
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reg = RK_PWM_READ(sc, RK_PWM_CTRL);
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if ((reg & RK_PWM_CTRL_ENABLE_MASK) == RK_PWM_CTRL_ENABLED)
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sc->enabled = true;
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reg = RK_PWM_READ(sc, RK_PWM_CTRL);
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reg &= RK_PWM_CTRL_PRESCALE_MASK;
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sc->prescaler = reg >> RK_PWM_CTRL_PRESCALE_SHIFT;
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reg = RK_PWM_READ(sc, RK_PWM_CTRL);
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reg &= RK_PWM_CTRL_SCALE_MASK;
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sc->scaler = reg >> RK_PWM_CTRL_SCALE_SHIFT;
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reg = RK_PWM_READ(sc, RK_PWM_CTRL);
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if ((reg & RK_PWM_CTRL_CLOCKSRC_MASK) == RK_PWM_CTRL_CLOCKSRC_SCALED)
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sc->using_scaler = true;
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else
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sc->using_scaler = false;
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clk_freq = sc->clk_freq / (2 ^ sc->prescaler);
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if (sc->using_scaler) {
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if (sc->scaler == 0)
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clk_freq /= 512;
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else
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clk_freq /= (sc->scaler * 2);
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}
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reg = RK_PWM_READ(sc, RK_PWM_PERIOD);
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sc->period = NS_PER_SEC /
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(clk_freq / reg);
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reg = RK_PWM_READ(sc, RK_PWM_DUTY);
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sc->duty = NS_PER_SEC /
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(clk_freq / reg);
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node = ofw_bus_get_node(dev);
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OF_device_register_xref(OF_xref_from_node(node), dev);
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sc->busdev = device_add_child(dev, "pwmbus", -1);
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return (bus_generic_attach(dev));
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fail:
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rk_pwm_detach(dev);
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return (error);
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}
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static int
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rk_pwm_detach(device_t dev)
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{
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struct rk_pwm_softc *sc;
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sc = device_get_softc(dev);
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bus_generic_detach(sc->dev);
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bus_release_resources(dev, rk_pwm_spec, &sc->res);
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return (0);
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}
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static phandle_t
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aw_pwm_get_node(device_t bus, device_t dev)
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{
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/*
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* Share our controller node with our pwmbus child; it instantiates
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* devices by walking the children contained within our node.
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*/
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return ofw_bus_get_node(bus);
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}
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static int
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rk_pwm_channel_count(device_t dev, u_int *nchannel)
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{
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/* The device supports 4 channels, but attaches multiple times in the
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* device tree. This interferes with advanced usage though, as
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* the interrupt capability and channel 3 FIFO register offsets
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* don't work right in this situation.
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* But since we don't support those yet, pretend we are singlechannel.
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*/
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*nchannel = 1;
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return (0);
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}
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static int
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rk_pwm_channel_config(device_t dev, u_int channel, u_int period, u_int duty)
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{
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struct rk_pwm_softc *sc;
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uint64_t period_freq, duty_freq;
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uint32_t reg;
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uint32_t period_out;
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uint32_t duty_out;
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uint8_t prescaler;
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uint8_t scaler;
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bool using_scaler;
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sc = device_get_softc(dev);
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period_freq = NS_PER_SEC / period;
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/* Datasheet doesn't define, so use Nyquist frequency. */
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if (period_freq > (sc->clk_freq / 2))
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return (EINVAL);
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duty_freq = NS_PER_SEC / duty;
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if (duty_freq < period_freq) {
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device_printf(sc->dev, "duty < period\n");
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return (EINVAL);
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}
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/* Assuming 24 MHz reference, we should never actually have
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to use the divider due to pwm API limitations. */
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prescaler = 0;
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scaler = 0;
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using_scaler = false;
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/* XXX Expand API to allow for 64 bit period/duty. */
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period_out = (sc->clk_freq * period) / NS_PER_SEC;
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duty_out = (sc->clk_freq * duty) / NS_PER_SEC;
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reg = RK_PWM_READ(sc, RK_PWM_CTRL);
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if ((reg & RK_PWM_CTRL_MODE_MASK) != RK_PWM_CTRL_MODE_CONTINUOUS) {
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/* Switching modes, disable just in case. */
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SET(reg, RK_PWM_CTRL_ENABLE_MASK, RK_PWM_CTRL_DISABLED);
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RK_PWM_WRITE(sc, RK_PWM_CTRL, reg);
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}
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RK_PWM_WRITE(sc, RK_PWM_PERIOD, period_out);
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RK_PWM_WRITE(sc, RK_PWM_DUTY, duty_out);
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SET(reg, RK_PWM_CTRL_ENABLE_MASK, RK_PWM_CTRL_ENABLED);
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SET(reg, RK_PWM_CTRL_MODE_MASK, RK_PWM_CTRL_MODE_CONTINUOUS);
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SET(reg, RK_PWM_CTRL_ALIGN_MASK, RK_PWM_CTRL_ALIGN_LEFT);
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SET(reg, RK_PWM_CTRL_CLOCKSRC_MASK, using_scaler);
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SET(reg, RK_PWM_CTRL_PRESCALE_MASK,
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prescaler << RK_PWM_CTRL_PRESCALE_SHIFT);
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SET(reg, RK_PWM_CTRL_SCALE_MASK,
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scaler << RK_PWM_CTRL_SCALE_SHIFT);
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RK_PWM_WRITE(sc, RK_PWM_CTRL, reg);
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sc->period = period;
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sc->duty = duty;
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return (0);
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}
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static int
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rk_pwm_channel_get_config(device_t dev, u_int channel, u_int *period, u_int *duty)
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{
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struct rk_pwm_softc *sc;
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sc = device_get_softc(dev);
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*period = sc->period;
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*duty = sc->duty;
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return (0);
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}
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static int
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rk_pwm_channel_enable(device_t dev, u_int channel, bool enable)
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{
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struct rk_pwm_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (enable && sc->enabled)
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return (0);
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reg = RK_PWM_READ(sc, RK_PWM_CTRL);
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SET(reg, RK_PWM_CTRL_ENABLE_MASK, enable);
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RK_PWM_WRITE(sc, RK_PWM_CTRL, reg);
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sc->enabled = enable;
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return (0);
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}
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static int
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rk_pwm_channel_is_enabled(device_t dev, u_int channel, bool *enabled)
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{
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struct rk_pwm_softc *sc;
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sc = device_get_softc(dev);
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*enabled = sc->enabled;
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return (0);
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}
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static device_method_t rk_pwm_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, rk_pwm_probe),
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DEVMETHOD(device_attach, rk_pwm_attach),
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DEVMETHOD(device_detach, rk_pwm_detach),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, aw_pwm_get_node),
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/* pwm interface */
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DEVMETHOD(pwmbus_channel_count, rk_pwm_channel_count),
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DEVMETHOD(pwmbus_channel_config, rk_pwm_channel_config),
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DEVMETHOD(pwmbus_channel_get_config, rk_pwm_channel_get_config),
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DEVMETHOD(pwmbus_channel_enable, rk_pwm_channel_enable),
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DEVMETHOD(pwmbus_channel_is_enabled, rk_pwm_channel_is_enabled),
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DEVMETHOD_END
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};
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static driver_t rk_pwm_driver = {
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"pwm",
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rk_pwm_methods,
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sizeof(struct rk_pwm_softc),
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};
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DRIVER_MODULE(rk_pwm, simplebus, rk_pwm_driver, 0, 0);
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SIMPLEBUS_PNP_INFO(compat_data);
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