594 lines
16 KiB
C
594 lines
16 KiB
C
/*-
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* Copyright (c) 2003-2005 Nate Lawson (SDG)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include "opt_acpi.h"
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/power.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/sbuf.h>
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#include <sys/pcpu.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include "cpufreq_if.h"
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/*
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* Support for ACPI processor performance states (Px) according to
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* section 8.3.3 of the ACPI 2.0c specification.
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*/
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struct acpi_px {
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uint32_t core_freq;
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uint32_t power;
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uint32_t trans_lat;
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uint32_t bm_lat;
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uint32_t ctrl_val;
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uint32_t sts_val;
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};
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/* Offsets in struct cf_setting array for storing driver-specific values. */
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#define PX_SPEC_CONTROL 0
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#define PX_SPEC_STATUS 1
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#define MAX_PX_STATES 16
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struct acpi_perf_softc {
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device_t dev;
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ACPI_HANDLE handle;
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struct resource *perf_ctrl; /* Set new performance state. */
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int perf_ctrl_type; /* Resource type for perf_ctrl. */
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struct resource *perf_status; /* Check that transition succeeded. */
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int perf_sts_type; /* Resource type for perf_status. */
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struct acpi_px *px_states; /* ACPI perf states. */
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uint32_t px_count; /* Total number of perf states. */
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uint32_t px_max_avail; /* Lowest index state available. */
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int px_curr_state; /* Active state index. */
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int px_rid;
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int info_only; /* Can we set new states? */
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};
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#define PX_GET_REG(reg) \
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(bus_space_read_4(rman_get_bustag((reg)), \
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rman_get_bushandle((reg)), 0))
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#define PX_SET_REG(reg, val) \
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(bus_space_write_4(rman_get_bustag((reg)), \
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rman_get_bushandle((reg)), 0, (val)))
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#define ACPI_NOTIFY_PERF_STATES 0x80 /* _PSS changed. */
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static void acpi_perf_identify(driver_t *driver, device_t parent);
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static int acpi_perf_probe(device_t dev);
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static int acpi_perf_attach(device_t dev);
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static int acpi_perf_detach(device_t dev);
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static int acpi_perf_evaluate(device_t dev);
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static int acpi_px_to_set(device_t dev, struct acpi_px *px,
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struct cf_setting *set);
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static void acpi_px_available(struct acpi_perf_softc *sc);
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static void acpi_px_startup(void *arg);
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static void acpi_px_notify(ACPI_HANDLE h, UINT32 notify, void *context);
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static int acpi_px_settings(device_t dev, struct cf_setting *sets,
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int *count);
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static int acpi_px_set(device_t dev, const struct cf_setting *set);
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static int acpi_px_get(device_t dev, struct cf_setting *set);
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static int acpi_px_type(device_t dev, int *type);
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static device_method_t acpi_perf_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, acpi_perf_identify),
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DEVMETHOD(device_probe, acpi_perf_probe),
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DEVMETHOD(device_attach, acpi_perf_attach),
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DEVMETHOD(device_detach, acpi_perf_detach),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, acpi_px_set),
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DEVMETHOD(cpufreq_drv_get, acpi_px_get),
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DEVMETHOD(cpufreq_drv_type, acpi_px_type),
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DEVMETHOD(cpufreq_drv_settings, acpi_px_settings),
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DEVMETHOD_END
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};
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static driver_t acpi_perf_driver = {
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"acpi_perf",
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acpi_perf_methods,
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sizeof(struct acpi_perf_softc),
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};
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DRIVER_MODULE(acpi_perf, cpu, acpi_perf_driver, 0, 0);
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MODULE_DEPEND(acpi_perf, acpi, 1, 1, 1);
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static MALLOC_DEFINE(M_ACPIPERF, "acpi_perf", "ACPI Performance states");
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static void
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acpi_perf_identify(driver_t *driver, device_t parent)
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{
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ACPI_HANDLE handle;
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device_t dev;
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/* Make sure we're not being doubly invoked. */
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if (device_find_child(parent, "acpi_perf", -1) != NULL)
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return;
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/* Get the handle for the Processor object and check for perf states. */
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handle = acpi_get_handle(parent);
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if (handle == NULL)
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return;
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if (ACPI_FAILURE(AcpiEvaluateObject(handle, "_PSS", NULL, NULL)))
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return;
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/*
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* Add a child to every CPU that has the right methods. In future
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* versions of the ACPI spec, CPUs can have different settings.
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* We probe this child now so that other devices that depend
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* on it (i.e., for info about supported states) will see it.
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*/
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if ((dev = BUS_ADD_CHILD(parent, 0, "acpi_perf",
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device_get_unit(parent))) != NULL)
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device_probe_and_attach(dev);
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else
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device_printf(parent, "add acpi_perf child failed\n");
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}
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static int
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acpi_perf_probe(device_t dev)
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{
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ACPI_HANDLE handle;
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ACPI_OBJECT *pkg;
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struct resource *res;
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ACPI_BUFFER buf;
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int error, rid, type;
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if (resource_disabled("acpi_perf", 0))
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return (ENXIO);
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/*
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* Check the performance state registers. If they are of type
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* "functional fixed hardware", we attach quietly since we will
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* only be providing information on settings to other drivers.
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*/
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error = ENXIO;
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handle = acpi_get_handle(dev);
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buf.Pointer = NULL;
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buf.Length = ACPI_ALLOCATE_BUFFER;
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if (ACPI_FAILURE(AcpiEvaluateObject(handle, "_PCT", NULL, &buf)))
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return (error);
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pkg = (ACPI_OBJECT *)buf.Pointer;
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if (ACPI_PKG_VALID(pkg, 2)) {
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rid = 0;
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error = acpi_PkgGas(dev, pkg, 0, &type, &rid, &res, 0);
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switch (error) {
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case 0:
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bus_release_resource(dev, type, rid, res);
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bus_delete_resource(dev, type, rid);
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device_set_desc(dev, "ACPI CPU Frequency Control");
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break;
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case EOPNOTSUPP:
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device_quiet(dev);
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error = 0;
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break;
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}
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}
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AcpiOsFree(buf.Pointer);
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return (error);
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}
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static int
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acpi_perf_attach(device_t dev)
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{
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struct acpi_perf_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->handle = acpi_get_handle(dev);
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sc->px_max_avail = 0;
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sc->px_curr_state = CPUFREQ_VAL_UNKNOWN;
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if (acpi_perf_evaluate(dev) != 0)
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return (ENXIO);
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AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_px_startup, NULL);
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if (!sc->info_only)
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cpufreq_register(dev);
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return (0);
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}
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static int
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acpi_perf_detach(device_t dev)
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{
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/* TODO: teardown registers, remove notify handler. */
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return (ENXIO);
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}
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/* Probe and setup any valid performance states (Px). */
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static int
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acpi_perf_evaluate(device_t dev)
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{
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struct acpi_perf_softc *sc;
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ACPI_BUFFER buf;
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ACPI_OBJECT *pkg, *res;
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ACPI_STATUS status;
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int count, error, i, j;
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static int once = 1;
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uint32_t *p;
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/* Get the control values and parameters for each state. */
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error = ENXIO;
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sc = device_get_softc(dev);
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buf.Pointer = NULL;
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buf.Length = ACPI_ALLOCATE_BUFFER;
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status = AcpiEvaluateObject(sc->handle, "_PSS", NULL, &buf);
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if (ACPI_FAILURE(status))
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return (ENXIO);
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pkg = (ACPI_OBJECT *)buf.Pointer;
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if (!ACPI_PKG_VALID(pkg, 1)) {
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device_printf(dev, "invalid top level _PSS package\n");
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goto out;
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}
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sc->px_count = pkg->Package.Count;
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sc->px_states = malloc(sc->px_count * sizeof(struct acpi_px),
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M_ACPIPERF, M_WAITOK | M_ZERO);
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/*
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* Each state is a package of {CoreFreq, Power, TransitionLatency,
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* BusMasterLatency, ControlVal, StatusVal}, sorted from highest
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* performance to lowest.
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*/
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count = 0;
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for (i = 0; i < sc->px_count; i++) {
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res = &pkg->Package.Elements[i];
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if (!ACPI_PKG_VALID(res, 6)) {
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if (once) {
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once = 0;
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device_printf(dev, "invalid _PSS package\n");
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}
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continue;
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}
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/* Parse the rest of the package into the struct. */
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p = &sc->px_states[count].core_freq;
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for (j = 0; j < 6; j++, p++)
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acpi_PkgInt32(res, j, p);
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/*
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* Check for some impossible frequencies that some systems
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* use to indicate they don't actually support this Px state.
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*/
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if (sc->px_states[count].core_freq == 0 ||
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sc->px_states[count].core_freq == 9999 ||
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sc->px_states[count].core_freq == 0x9999 ||
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sc->px_states[count].core_freq >= 0xffff)
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continue;
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/* Check for duplicate entries */
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if (count > 0 &&
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sc->px_states[count - 1].core_freq ==
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sc->px_states[count].core_freq)
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continue;
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count++;
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}
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sc->px_count = count;
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/* No valid Px state found so give up. */
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if (count == 0)
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goto out;
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AcpiOsFree(buf.Pointer);
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/* Get the control and status registers (one of each). */
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buf.Pointer = NULL;
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buf.Length = ACPI_ALLOCATE_BUFFER;
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status = AcpiEvaluateObject(sc->handle, "_PCT", NULL, &buf);
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if (ACPI_FAILURE(status))
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goto out;
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/* Check the package of two registers, each a Buffer in GAS format. */
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pkg = (ACPI_OBJECT *)buf.Pointer;
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if (!ACPI_PKG_VALID(pkg, 2)) {
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device_printf(dev, "invalid perf register package\n");
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goto out;
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}
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error = acpi_PkgGas(sc->dev, pkg, 0, &sc->perf_ctrl_type, &sc->px_rid,
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&sc->perf_ctrl, 0);
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if (error) {
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/*
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* If the register is of type FFixedHW, we can only return
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* info, we can't get or set new settings.
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*/
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if (error == EOPNOTSUPP) {
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sc->info_only = TRUE;
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error = 0;
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} else
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device_printf(dev, "failed in PERF_CTL attach\n");
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goto out;
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}
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sc->px_rid++;
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error = acpi_PkgGas(sc->dev, pkg, 1, &sc->perf_sts_type, &sc->px_rid,
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&sc->perf_status, 0);
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if (error) {
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if (error == EOPNOTSUPP) {
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sc->info_only = TRUE;
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error = 0;
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} else
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device_printf(dev, "failed in PERF_STATUS attach\n");
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goto out;
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}
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sc->px_rid++;
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/* Get our current limit and register for notifies. */
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acpi_px_available(sc);
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AcpiInstallNotifyHandler(sc->handle, ACPI_DEVICE_NOTIFY,
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acpi_px_notify, sc);
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error = 0;
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out:
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if (error) {
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if (sc->px_states) {
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free(sc->px_states, M_ACPIPERF);
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sc->px_states = NULL;
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}
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if (sc->perf_ctrl) {
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bus_release_resource(sc->dev, sc->perf_ctrl_type, 0,
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sc->perf_ctrl);
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bus_delete_resource(sc->dev, sc->perf_ctrl_type, 0);
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sc->perf_ctrl = NULL;
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}
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if (sc->perf_status) {
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bus_release_resource(sc->dev, sc->perf_sts_type, 1,
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sc->perf_status);
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bus_delete_resource(sc->dev, sc->perf_sts_type, 1);
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sc->perf_status = NULL;
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}
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sc->px_rid = 0;
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sc->px_count = 0;
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}
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if (buf.Pointer)
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AcpiOsFree(buf.Pointer);
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return (error);
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}
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static void
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acpi_px_startup(void *arg)
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{
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/* Signal to the platform that we are taking over CPU control. */
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if (AcpiGbl_FADT.PstateControl == 0)
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return;
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ACPI_LOCK(acpi);
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AcpiOsWritePort(AcpiGbl_FADT.SmiCommand, AcpiGbl_FADT.PstateControl, 8);
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ACPI_UNLOCK(acpi);
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}
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static void
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acpi_px_notify(ACPI_HANDLE h, UINT32 notify, void *context)
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{
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struct acpi_perf_softc *sc;
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sc = context;
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if (notify != ACPI_NOTIFY_PERF_STATES)
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return;
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acpi_px_available(sc);
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/* TODO: Implement notification when frequency changes. */
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}
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/*
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* Find the highest currently-supported performance state.
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* This can be called at runtime (e.g., due to a docking event) at
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* the request of a Notify on the processor object.
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*/
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static void
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acpi_px_available(struct acpi_perf_softc *sc)
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{
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ACPI_STATUS status;
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struct cf_setting set;
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status = acpi_GetInteger(sc->handle, "_PPC", &sc->px_max_avail);
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/* If the old state is too high, set current state to the new max. */
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if (ACPI_SUCCESS(status)) {
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if (sc->px_curr_state != CPUFREQ_VAL_UNKNOWN &&
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sc->px_curr_state > sc->px_max_avail) {
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acpi_px_to_set(sc->dev,
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&sc->px_states[sc->px_max_avail], &set);
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acpi_px_set(sc->dev, &set);
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}
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} else
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sc->px_max_avail = 0;
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}
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static int
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acpi_px_to_set(device_t dev, struct acpi_px *px, struct cf_setting *set)
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{
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if (px == NULL || set == NULL)
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return (EINVAL);
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set->freq = px->core_freq;
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set->power = px->power;
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/* XXX Include BM latency too? */
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set->lat = px->trans_lat;
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set->volts = CPUFREQ_VAL_UNKNOWN;
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set->dev = dev;
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set->spec[PX_SPEC_CONTROL] = px->ctrl_val;
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set->spec[PX_SPEC_STATUS] = px->sts_val;
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return (0);
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}
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static int
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acpi_px_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct acpi_perf_softc *sc;
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int x, y;
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sc = device_get_softc(dev);
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if (sets == NULL || count == NULL)
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return (EINVAL);
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if (*count < sc->px_count - sc->px_max_avail)
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return (E2BIG);
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/* Return a list of settings that are currently valid. */
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y = 0;
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for (x = sc->px_max_avail; x < sc->px_count; x++, y++)
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acpi_px_to_set(dev, &sc->px_states[x], &sets[y]);
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*count = sc->px_count - sc->px_max_avail;
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return (0);
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}
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static int
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acpi_px_set(device_t dev, const struct cf_setting *set)
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{
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struct acpi_perf_softc *sc;
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int i, status, sts_val, tries;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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/* If we can't set new states, return immediately. */
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if (sc->info_only)
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return (ENXIO);
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/* Look up appropriate state, based on frequency. */
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for (i = sc->px_max_avail; i < sc->px_count; i++) {
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if (CPUFREQ_CMP(set->freq, sc->px_states[i].core_freq))
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break;
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}
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if (i == sc->px_count)
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return (EINVAL);
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/* Write the appropriate value to the register. */
|
|
PX_SET_REG(sc->perf_ctrl, sc->px_states[i].ctrl_val);
|
|
|
|
/*
|
|
* Try for up to 10 ms to verify the desired state was selected.
|
|
* This is longer than the standard says (1 ms) but in some modes,
|
|
* systems may take longer to respond.
|
|
*/
|
|
sts_val = sc->px_states[i].sts_val;
|
|
for (tries = 0; tries < 1000; tries++) {
|
|
status = PX_GET_REG(sc->perf_status);
|
|
|
|
/*
|
|
* If we match the status or the desired status is 8 bits
|
|
* and matches the relevant bits, assume we succeeded. It
|
|
* appears some systems (IBM R32) expect byte-wide access
|
|
* even though the standard says the register is 32-bit.
|
|
*/
|
|
if (status == sts_val ||
|
|
((sts_val & ~0xff) == 0 && (status & 0xff) == sts_val))
|
|
break;
|
|
DELAY(10);
|
|
}
|
|
if (tries == 1000) {
|
|
device_printf(dev, "Px transition to %d failed\n",
|
|
sc->px_states[i].core_freq);
|
|
return (ENXIO);
|
|
}
|
|
sc->px_curr_state = i;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
acpi_px_get(device_t dev, struct cf_setting *set)
|
|
{
|
|
struct acpi_perf_softc *sc;
|
|
uint64_t rate;
|
|
int i;
|
|
struct pcpu *pc;
|
|
|
|
if (set == NULL)
|
|
return (EINVAL);
|
|
sc = device_get_softc(dev);
|
|
|
|
/* If we can't get new states, return immediately. */
|
|
if (sc->info_only)
|
|
return (ENXIO);
|
|
|
|
/* If we've set the rate before, use the cached value. */
|
|
if (sc->px_curr_state != CPUFREQ_VAL_UNKNOWN) {
|
|
acpi_px_to_set(dev, &sc->px_states[sc->px_curr_state], set);
|
|
return (0);
|
|
}
|
|
|
|
/* Otherwise, estimate and try to match against our settings. */
|
|
pc = cpu_get_pcpu(dev);
|
|
if (pc == NULL)
|
|
return (ENXIO);
|
|
cpu_est_clockrate(pc->pc_cpuid, &rate);
|
|
rate /= 1000000;
|
|
for (i = 0; i < sc->px_count; i++) {
|
|
if (CPUFREQ_CMP(sc->px_states[i].core_freq, rate)) {
|
|
sc->px_curr_state = i;
|
|
acpi_px_to_set(dev, &sc->px_states[i], set);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* No match, give up. */
|
|
if (i == sc->px_count) {
|
|
sc->px_curr_state = CPUFREQ_VAL_UNKNOWN;
|
|
set->freq = CPUFREQ_VAL_UNKNOWN;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
acpi_px_type(device_t dev, int *type)
|
|
{
|
|
struct acpi_perf_softc *sc;
|
|
|
|
if (type == NULL)
|
|
return (EINVAL);
|
|
sc = device_get_softc(dev);
|
|
|
|
*type = CPUFREQ_TYPE_ABSOLUTE;
|
|
if (sc->info_only)
|
|
*type |= CPUFREQ_FLAG_INFO_ONLY;
|
|
return (0);
|
|
}
|