512 lines
13 KiB
C
512 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <dev/agp/agppriv.h>
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#include <dev/agp/agpreg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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/* XXX */
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extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
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extern uint32_t pci_cfgregread(int, int, int, int, int);
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static void agp_amd64_apbase_fixup(device_t);
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static void agp_amd64_uli_init(device_t);
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static int agp_amd64_uli_set_aperture(device_t, uint32_t);
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static int agp_amd64_nvidia_match(uint16_t);
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static void agp_amd64_nvidia_init(device_t);
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static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
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static int agp_amd64_via_match(void);
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static void agp_amd64_via_init(device_t);
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static int agp_amd64_via_set_aperture(device_t, uint32_t);
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MALLOC_DECLARE(M_AGP);
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#define AMD64_MAX_MCTRL 8
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struct agp_amd64_softc {
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struct agp_softc agp;
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uint32_t initial_aperture;
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struct agp_gatt *gatt;
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uint32_t apbase;
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int mctrl[AMD64_MAX_MCTRL];
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int n_mctrl;
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int via_agp;
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};
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static const char*
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agp_amd64_match(device_t dev)
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{
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if (pci_get_class(dev) != PCIC_BRIDGE ||
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pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
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agp_find_caps(dev) == 0)
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return (NULL);
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switch (pci_get_devid(dev)) {
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case 0x74541022:
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return ("AMD 8151 AGP graphics tunnel");
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case 0x07551039:
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return ("SiS 755 host to AGP bridge");
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case 0x07601039:
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return ("SiS 760 host to AGP bridge");
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case 0x168910b9:
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return ("ULi M1689 AGP Controller");
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case 0x00d110de:
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if (agp_amd64_nvidia_match(0x00d2))
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return (NULL);
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return ("NVIDIA nForce3 AGP Controller");
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case 0x00e110de:
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if (agp_amd64_nvidia_match(0x00e2))
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return (NULL);
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return ("NVIDIA nForce3-250 AGP Controller");
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case 0x02041106:
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return ("VIA 8380 host to PCI bridge");
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case 0x02381106:
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return ("VIA 3238 host to PCI bridge");
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case 0x02821106:
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return ("VIA K8T800Pro host to PCI bridge");
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case 0x31881106:
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return ("VIA 8385 host to PCI bridge");
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}
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return (NULL);
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}
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static int
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agp_amd64_nvidia_match(uint16_t devid)
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{
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/* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
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if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
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pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
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pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
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pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
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return (ENXIO);
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return (0);
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}
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static int
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agp_amd64_via_match(void)
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{
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/* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
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if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
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pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
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pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
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pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
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(pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
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return (0);
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return (1);
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}
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static int
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agp_amd64_probe(device_t dev)
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{
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const char *desc;
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if (resource_disabled("agp", device_get_unit(dev)))
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return (ENXIO);
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if ((desc = agp_amd64_match(dev))) {
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device_set_desc(dev, desc);
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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agp_amd64_attach(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt;
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uint32_t devid;
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int i, n, error;
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for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
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devid = pci_cfgregread(0, i, 3, 0, 4);
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if (devid == 0x11031022 || devid == 0x12031022) {
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sc->mctrl[n] = i;
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n++;
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}
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}
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if (n == 0)
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return (ENXIO);
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sc->n_mctrl = n;
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if (bootverbose)
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device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
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sc->n_mctrl);
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if ((error = agp_generic_attach(dev)))
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return (error);
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sc->initial_aperture = AGP_GET_APERTURE(dev);
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for (;;) {
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gatt = agp_alloc_gatt(dev);
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if (gatt)
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break;
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/*
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* Probably contigmalloc failure. Try reducing the
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* aperture so that the gatt size reduces.
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*/
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if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
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agp_generic_detach(dev);
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return (ENOMEM);
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}
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}
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sc->gatt = gatt;
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switch (pci_get_vendor(dev)) {
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case 0x10b9: /* ULi */
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agp_amd64_uli_init(dev);
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if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
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return (ENXIO);
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break;
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case 0x10de: /* nVidia */
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agp_amd64_nvidia_init(dev);
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if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
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return (ENXIO);
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break;
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case 0x1106: /* VIA */
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sc->via_agp = agp_amd64_via_match();
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if (sc->via_agp) {
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agp_amd64_via_init(dev);
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if (agp_amd64_via_set_aperture(dev,
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sc->initial_aperture))
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return (ENXIO);
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}
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break;
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}
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/* Install the gatt and enable aperture. */
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for (i = 0; i < sc->n_mctrl; i++) {
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
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(uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
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4);
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
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(pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
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AGP_AMD64_APCTRL_GARTEN) &
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~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
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4);
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}
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return (0);
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}
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static int
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agp_amd64_detach(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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int i;
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agp_free_cdev(dev);
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for (i = 0; i < sc->n_mctrl; i++)
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
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pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
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~AGP_AMD64_APCTRL_GARTEN, 4);
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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agp_free_res(dev);
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return (0);
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}
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static uint32_t agp_amd64_table[] = {
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0x02000000, /* 32 MB */
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0x04000000, /* 64 MB */
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0x08000000, /* 128 MB */
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0x10000000, /* 256 MB */
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0x20000000, /* 512 MB */
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0x40000000, /* 1024 MB */
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0x80000000, /* 2048 MB */
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};
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#define AGP_AMD64_TABLE_SIZE nitems(agp_amd64_table)
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static uint32_t
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agp_amd64_get_aperture(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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uint32_t i;
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i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
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AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
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if (i >= AGP_AMD64_TABLE_SIZE)
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return (0);
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return (agp_amd64_table[i]);
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}
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static int
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agp_amd64_set_aperture(device_t dev, uint32_t aperture)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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uint32_t i;
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int j;
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for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
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if (agp_amd64_table[i] == aperture)
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break;
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if (i >= AGP_AMD64_TABLE_SIZE)
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return (EINVAL);
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for (j = 0; j < sc->n_mctrl; j++)
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pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
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(pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
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~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
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switch (pci_get_vendor(dev)) {
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case 0x10b9: /* ULi */
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return (agp_amd64_uli_set_aperture(dev, aperture));
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break;
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case 0x10de: /* nVidia */
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return (agp_amd64_nvidia_set_aperture(dev, aperture));
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break;
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case 0x1106: /* VIA */
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if (sc->via_agp)
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return (agp_amd64_via_set_aperture(dev, aperture));
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break;
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}
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return (0);
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}
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static int
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agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return (EINVAL);
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
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(physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
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return (0);
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}
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static int
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agp_amd64_unbind_page(device_t dev, vm_offset_t offset)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return (EINVAL);
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
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return (0);
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}
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static void
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agp_amd64_flush_tlb(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->n_mctrl; i++)
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
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pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
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AGP_AMD64_CACHECTRL_INVGART, 4);
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}
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static void
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agp_amd64_apbase_fixup(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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uint32_t apbase;
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int i;
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sc->apbase = rman_get_start(sc->agp.as_aperture);
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apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
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for (i = 0; i < sc->n_mctrl; i++)
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pci_cfgregwrite(0, sc->mctrl[i], 3,
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AGP_AMD64_APBASE, apbase, 4);
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}
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static void
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agp_amd64_uli_init(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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agp_amd64_apbase_fixup(dev);
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pci_write_config(dev, AGP_AMD64_ULI_APBASE,
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(pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
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sc->apbase, 4);
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pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
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}
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static int
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agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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switch (aperture) {
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case 0x02000000: /* 32 MB */
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case 0x04000000: /* 64 MB */
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case 0x08000000: /* 128 MB */
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case 0x10000000: /* 256 MB */
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break;
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default:
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return (EINVAL);
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}
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pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
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sc->apbase + aperture - 1, 4);
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return (0);
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}
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static void
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agp_amd64_nvidia_init(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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agp_amd64_apbase_fixup(dev);
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pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
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(pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
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sc->apbase, 4);
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pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
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pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
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}
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static int
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agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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uint32_t apsize;
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switch (aperture) {
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case 0x02000000: apsize = 0x0f; break; /* 32 MB */
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case 0x04000000: apsize = 0x0e; break; /* 64 MB */
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case 0x08000000: apsize = 0x0c; break; /* 128 MB */
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case 0x10000000: apsize = 0x08; break; /* 256 MB */
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case 0x20000000: apsize = 0x00; break; /* 512 MB */
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default:
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return (EINVAL);
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}
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pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
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(pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
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0xfffffff0) | apsize, 4);
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pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
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sc->apbase + aperture - 1, 4);
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pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
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sc->apbase + aperture - 1, 4);
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return (0);
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}
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static void
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agp_amd64_via_init(device_t dev)
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{
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struct agp_amd64_softc *sc = device_get_softc(dev);
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agp_amd64_apbase_fixup(dev);
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pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
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pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
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pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
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}
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static int
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agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
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{
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uint32_t apsize;
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apsize = ((aperture - 1) >> 20) ^ 0xff;
|
|
if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
|
|
return (EINVAL);
|
|
pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t agp_amd64_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, agp_amd64_probe),
|
|
DEVMETHOD(device_attach, agp_amd64_attach),
|
|
DEVMETHOD(device_detach, agp_amd64_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* AGP interface */
|
|
DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
|
|
DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
|
|
DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
|
|
DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
|
|
DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
|
|
DEVMETHOD(agp_enable, agp_generic_enable),
|
|
DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
|
|
DEVMETHOD(agp_free_memory, agp_generic_free_memory),
|
|
DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
|
|
DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t agp_amd64_driver = {
|
|
"agp",
|
|
agp_amd64_methods,
|
|
sizeof(struct agp_amd64_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, 0, 0);
|
|
MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
|
|
MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
|