876 lines
24 KiB
C
876 lines
24 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org>
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* Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org>
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* Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org>
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* All rights reserved.
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* Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for the AMD CPU on-die thermal sensors.
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* Initially based on the k8temp Linux driver.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <machine/cpufunc.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include <dev/pci/pcivar.h>
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#include <x86/pci_cfgreg.h>
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#include <dev/amdsmn/amdsmn.h>
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typedef enum {
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CORE0_SENSOR0,
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CORE0_SENSOR1,
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CORE1_SENSOR0,
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CORE1_SENSOR1,
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CORE0,
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CORE1,
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CCD1,
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CCD_BASE = CCD1,
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CCD2,
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CCD3,
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CCD4,
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CCD5,
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CCD6,
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CCD7,
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CCD8,
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CCD_MAX = CCD8,
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NUM_CCDS = CCD_MAX - CCD_BASE + 1,
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} amdsensor_t;
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struct amdtemp_softc {
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int sc_ncores;
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int sc_ntemps;
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int sc_flags;
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#define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */
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#define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */
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#define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */
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int32_t sc_offset;
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int32_t sc_temp_base;
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int32_t (*sc_gettemp)(device_t, amdsensor_t);
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struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
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struct intr_config_hook sc_ich;
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device_t sc_smn;
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struct mtx sc_lock;
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};
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/*
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* N.B. The numbers in macro names below are significant and represent CPU
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* family and model numbers. Do not make up fictitious family or model numbers
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* when adding support for new devices.
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*/
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#define VENDORID_AMD 0x1022
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#define DEVICEID_AMD_MISC0F 0x1103
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#define DEVICEID_AMD_MISC10 0x1203
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#define DEVICEID_AMD_MISC11 0x1303
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#define DEVICEID_AMD_MISC14 0x1703
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#define DEVICEID_AMD_MISC15 0x1603
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#define DEVICEID_AMD_MISC15_M10H 0x1403
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#define DEVICEID_AMD_MISC15_M30H 0x141d
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#define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576
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#define DEVICEID_AMD_MISC16 0x1533
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#define DEVICEID_AMD_MISC16_M30H 0x1583
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#define DEVICEID_AMD_HOSTB17H_ROOT 0x1450
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#define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0
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#define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
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#define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630
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#define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8
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static const struct amdtemp_product {
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uint16_t amdtemp_vendorid;
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uint16_t amdtemp_deviceid;
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/*
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* 0xFC register is only valid on the D18F3 PCI device; SMN temp
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* drivers do not attach to that device.
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*/
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bool amdtemp_has_cpuid;
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} amdtemp_products[] = {
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{ VENDORID_AMD, DEVICEID_AMD_MISC0F, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC10, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC11, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC14, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC15, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false },
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{ VENDORID_AMD, DEVICEID_AMD_MISC16, true },
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{ VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true },
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{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false },
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{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
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{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
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{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false },
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{ VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false },
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};
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/*
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* Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
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*/
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#define AMDTEMP_REPTMP_CTRL 0xa4
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#define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff
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#define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21
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#define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3
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#define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16
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/*
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* Reported Temperature, Family 15h, M60+
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*
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* Same register bit definitions as other Family 15h CPUs, but access is
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* indirect via SMN, like Family 17h.
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*/
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#define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4
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/*
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* Reported Temperature, Family 17h
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*
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* According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
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* provide the current temp. bit 19, when clear, means the temp is reported in
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* a range 0.."225C" (probable typo for 255C), and when set changes the range
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* to -49..206C.
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*/
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#define AMDTEMP_17H_CUR_TMP 0x59800
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#define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19)
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/*
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* Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the
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* 49 degree offset should apply as well. This was revealed in a Linux
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* patch from an AMD employee.
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*/
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#define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16))
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/*
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* The following register set was discovered experimentally by Ondrej Čerman
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* and collaborators, but is not (yet) documented in a PPR/OSRR (other than
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* the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
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* SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
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*/
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#define AMDTEMP_17H_CCD_TMP_BASE 0x59954
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#define AMDTEMP_17H_CCD_TMP_VALID (1u << 11)
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#define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08
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/*
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* AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius).
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*/
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#define AMDTEMP_CURTMP_RANGE_ADJUST 490
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/*
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* Thermaltrip Status Register (Family 0Fh only)
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*/
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#define AMDTEMP_THERMTP_STAT 0xe4
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#define AMDTEMP_TTSR_SELCORE 0x04
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#define AMDTEMP_TTSR_SELSENSOR 0x40
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/*
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* DRAM Configuration High Register
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*/
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#define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */
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#define AMDTEMP_DRAM_MODE_DDR3 0x0100
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/*
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* CPU Family/Model Register
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*/
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#define AMDTEMP_CPUID 0xfc
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/*
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* Device methods.
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*/
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static void amdtemp_identify(driver_t *driver, device_t parent);
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static int amdtemp_probe(device_t dev);
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static int amdtemp_attach(device_t dev);
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static void amdtemp_intrhook(void *arg);
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static int amdtemp_detach(device_t dev);
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static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
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static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor);
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static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor);
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static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor);
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static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model);
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static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model);
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static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
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static device_method_t amdtemp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, amdtemp_identify),
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DEVMETHOD(device_probe, amdtemp_probe),
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DEVMETHOD(device_attach, amdtemp_attach),
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DEVMETHOD(device_detach, amdtemp_detach),
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DEVMETHOD_END
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};
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static driver_t amdtemp_driver = {
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"amdtemp",
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amdtemp_methods,
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sizeof(struct amdtemp_softc),
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};
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DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL);
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MODULE_VERSION(amdtemp, 1);
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MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1);
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MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products,
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nitems(amdtemp_products));
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static bool
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amdtemp_match(device_t dev, const struct amdtemp_product **product_out)
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{
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int i;
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uint16_t vendor, devid;
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vendor = pci_get_vendor(dev);
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devid = pci_get_device(dev);
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for (i = 0; i < nitems(amdtemp_products); i++) {
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if (vendor == amdtemp_products[i].amdtemp_vendorid &&
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devid == amdtemp_products[i].amdtemp_deviceid) {
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if (product_out != NULL)
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*product_out = &amdtemp_products[i];
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return (true);
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}
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}
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return (false);
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}
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static void
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amdtemp_identify(driver_t *driver, device_t parent)
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{
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device_t child;
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/* Make sure we're not being doubly invoked. */
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if (device_find_child(parent, "amdtemp", -1) != NULL)
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return;
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if (amdtemp_match(parent, NULL)) {
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child = device_add_child(parent, "amdtemp", -1);
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if (child == NULL)
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device_printf(parent, "add amdtemp child failed\n");
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}
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}
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static int
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amdtemp_probe(device_t dev)
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{
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uint32_t family, model;
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if (resource_disabled("amdtemp", 0))
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return (ENXIO);
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if (!amdtemp_match(device_get_parent(dev), NULL))
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return (ENXIO);
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family = CPUID_TO_FAMILY(cpu_id);
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model = CPUID_TO_MODEL(cpu_id);
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switch (family) {
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case 0x0f:
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if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
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(model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
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return (ENXIO);
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break;
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case 0x10:
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case 0x11:
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case 0x12:
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x19:
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break;
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default:
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return (ENXIO);
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}
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device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
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return (BUS_PROBE_GENERIC);
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}
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static int
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amdtemp_attach(device_t dev)
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{
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char tn[32];
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u_int regs[4];
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const struct amdtemp_product *product;
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struct amdtemp_softc *sc;
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struct sysctl_ctx_list *sysctlctx;
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struct sysctl_oid *sysctlnode;
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uint32_t cpuid, family, model;
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u_int bid;
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int erratum319, unit;
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bool needsmn;
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sc = device_get_softc(dev);
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erratum319 = 0;
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needsmn = false;
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if (!amdtemp_match(device_get_parent(dev), &product))
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return (ENXIO);
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cpuid = cpu_id;
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family = CPUID_TO_FAMILY(cpuid);
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model = CPUID_TO_MODEL(cpuid);
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/*
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* This checks for the byzantine condition of running a heterogenous
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* revision multi-socket system where the attach thread is potentially
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* probing a remote socket's PCI device.
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*
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* Currently, such scenarios are unsupported on models using the SMN
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* (because on those models, amdtemp(4) attaches to a different PCI
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* device than the one that contains AMDTEMP_CPUID).
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*
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* The ancient 0x0F family of devices only supports this register from
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* models 40h+.
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*/
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if (product->amdtemp_has_cpuid && (family > 0x0f ||
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(family == 0x0f && model >= 0x40))) {
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cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID,
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4);
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family = CPUID_TO_FAMILY(cpuid);
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model = CPUID_TO_MODEL(cpuid);
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}
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switch (family) {
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case 0x0f:
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/*
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* Thermaltrip Status Register
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*
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* - ThermSenseCoreSel
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*
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* Revision F & G: 0 - Core1, 1 - Core0
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* Other: 0 - Core0, 1 - Core1
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*
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* - CurTmp
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*
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* Revision G: bits 23-14
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* Other: bits 23-16
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*
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* XXX According to the BKDG, CurTmp, ThermSenseSel and
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* ThermSenseCoreSel bits were introduced in Revision F
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* but CurTmp seems working fine as early as Revision C.
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* However, it is not clear whether ThermSenseSel and/or
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* ThermSenseCoreSel work in undocumented cases as well.
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* In fact, the Linux driver suggests it may not work but
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* we just assume it does until we find otherwise.
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*
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* XXX According to Linux, CurTmp starts at -28C on
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* Socket AM2 Revision G processors, which is not
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* documented anywhere.
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*/
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if (model >= 0x40)
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sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
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if (model >= 0x60 && model != 0xc1) {
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do_cpuid(0x80000001, regs);
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bid = (regs[1] >> 9) & 0x1f;
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switch (model) {
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case 0x68: /* Socket S1g1 */
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case 0x6c:
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case 0x7c:
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break;
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case 0x6b: /* Socket AM2 and ASB1 (2 cores) */
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if (bid != 0x0b && bid != 0x0c)
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sc->sc_flags |=
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AMDTEMP_FLAG_ALT_OFFSET;
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break;
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case 0x6f: /* Socket AM2 and ASB1 (1 core) */
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case 0x7f:
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if (bid != 0x07 && bid != 0x09 &&
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bid != 0x0c)
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sc->sc_flags |=
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AMDTEMP_FLAG_ALT_OFFSET;
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break;
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default:
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sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET;
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}
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sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
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}
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/*
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* There are two sensors per core.
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*/
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sc->sc_ntemps = 2;
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sc->sc_gettemp = amdtemp_gettemp0f;
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break;
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case 0x10:
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/*
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* Erratum 319 Inaccurate Temperature Measurement
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*
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* http://support.amd.com/us/Processor_TechDocs/41322.pdf
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*/
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do_cpuid(0x80000001, regs);
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switch ((regs[1] >> 28) & 0xf) {
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case 0: /* Socket F */
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erratum319 = 1;
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break;
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case 1: /* Socket AM2+ or AM3 */
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if ((pci_cfgregread(pci_get_bus(dev),
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pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) &
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AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
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(model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
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break;
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/* XXX 00100F42h (RB-C2) exists in both formats. */
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erratum319 = 1;
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break;
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}
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/* FALLTHROUGH */
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case 0x11:
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case 0x12:
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case 0x14:
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case 0x15:
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case 0x16:
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sc->sc_ntemps = 1;
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/*
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* Some later (60h+) models of family 15h use a similar SMN
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* network as family 17h. (However, the register index differs
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* from 17h and the decoding matches other 10h-15h models,
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* which differ from 17h.)
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*/
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if (family == 0x15 && model >= 0x60) {
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sc->sc_gettemp = amdtemp_gettemp15hm60h;
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needsmn = true;
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} else
|
|
sc->sc_gettemp = amdtemp_gettemp;
|
|
break;
|
|
case 0x17:
|
|
case 0x19:
|
|
sc->sc_ntemps = 1;
|
|
sc->sc_gettemp = amdtemp_gettemp17h;
|
|
needsmn = true;
|
|
break;
|
|
default:
|
|
device_printf(dev, "Bogus family 0x%x\n", family);
|
|
return (ENXIO);
|
|
}
|
|
|
|
if (needsmn) {
|
|
sc->sc_smn = device_find_child(
|
|
device_get_parent(dev), "amdsmn", -1);
|
|
if (sc->sc_smn == NULL) {
|
|
if (bootverbose)
|
|
device_printf(dev, "No SMN device found\n");
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
/* Find number of cores per package. */
|
|
sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
|
|
(cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
|
|
if (sc->sc_ncores > MAXCPU)
|
|
return (ENXIO);
|
|
|
|
mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF);
|
|
if (erratum319)
|
|
device_printf(dev,
|
|
"Erratum 319: temperature measurement may be inaccurate\n");
|
|
if (bootverbose)
|
|
device_printf(dev, "Found %d cores and %d sensors.\n",
|
|
sc->sc_ncores,
|
|
sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
|
|
|
|
/*
|
|
* dev.amdtemp.N tree.
|
|
*/
|
|
unit = device_get_unit(dev);
|
|
snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit);
|
|
TUNABLE_INT_FETCH(tn, &sc->sc_offset);
|
|
|
|
sysctlctx = device_get_sysctl_ctx(dev);
|
|
SYSCTL_ADD_INT(sysctlctx,
|
|
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
|
|
"sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,
|
|
"Temperature sensor offset");
|
|
sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
|
|
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
|
|
"core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0");
|
|
|
|
SYSCTL_ADD_PROC(sysctlctx,
|
|
SYSCTL_CHILDREN(sysctlnode),
|
|
OID_AUTO, "sensor0",
|
|
CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
dev, CORE0_SENSOR0, amdtemp_sysctl, "IK",
|
|
"Core 0 / Sensor 0 temperature");
|
|
|
|
sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE;
|
|
|
|
if (family == 0x17)
|
|
amdtemp_probe_ccd_sensors17h(dev, model);
|
|
else if (family == 0x19)
|
|
amdtemp_probe_ccd_sensors19h(dev, model);
|
|
else if (sc->sc_ntemps > 1) {
|
|
SYSCTL_ADD_PROC(sysctlctx,
|
|
SYSCTL_CHILDREN(sysctlnode),
|
|
OID_AUTO, "sensor1",
|
|
CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
dev, CORE0_SENSOR1, amdtemp_sysctl, "IK",
|
|
"Core 0 / Sensor 1 temperature");
|
|
|
|
if (sc->sc_ncores > 1) {
|
|
sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
|
|
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
|
|
OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
0, "Core 1");
|
|
|
|
SYSCTL_ADD_PROC(sysctlctx,
|
|
SYSCTL_CHILDREN(sysctlnode),
|
|
OID_AUTO, "sensor0",
|
|
CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
dev, CORE1_SENSOR0, amdtemp_sysctl, "IK",
|
|
"Core 1 / Sensor 0 temperature");
|
|
|
|
SYSCTL_ADD_PROC(sysctlctx,
|
|
SYSCTL_CHILDREN(sysctlnode),
|
|
OID_AUTO, "sensor1",
|
|
CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
dev, CORE1_SENSOR1, amdtemp_sysctl, "IK",
|
|
"Core 1 / Sensor 1 temperature");
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Try to create dev.cpu sysctl entries and setup intrhook function.
|
|
* This is needed because the cpu driver may be loaded late on boot,
|
|
* after us.
|
|
*/
|
|
amdtemp_intrhook(dev);
|
|
sc->sc_ich.ich_func = amdtemp_intrhook;
|
|
sc->sc_ich.ich_arg = dev;
|
|
if (config_intrhook_establish(&sc->sc_ich) != 0) {
|
|
device_printf(dev, "config_intrhook_establish failed!\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
amdtemp_intrhook(void *arg)
|
|
{
|
|
struct amdtemp_softc *sc;
|
|
struct sysctl_ctx_list *sysctlctx;
|
|
device_t dev = (device_t)arg;
|
|
device_t acpi, cpu, nexus;
|
|
amdsensor_t sensor;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/*
|
|
* dev.cpu.N.temperature.
|
|
*/
|
|
nexus = device_find_child(root_bus, "nexus", 0);
|
|
acpi = device_find_child(nexus, "acpi", 0);
|
|
|
|
for (i = 0; i < sc->sc_ncores; i++) {
|
|
if (sc->sc_sysctl_cpu[i] != NULL)
|
|
continue;
|
|
cpu = device_find_child(acpi, "cpu",
|
|
device_get_unit(dev) * sc->sc_ncores + i);
|
|
if (cpu != NULL) {
|
|
sysctlctx = device_get_sysctl_ctx(cpu);
|
|
|
|
sensor = sc->sc_ntemps > 1 ?
|
|
(i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;
|
|
sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
|
|
SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
|
|
OID_AUTO, "temperature",
|
|
CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
dev, sensor, amdtemp_sysctl, "IK",
|
|
"Current temparature");
|
|
}
|
|
}
|
|
if (sc->sc_ich.ich_arg != NULL)
|
|
config_intrhook_disestablish(&sc->sc_ich);
|
|
}
|
|
|
|
int
|
|
amdtemp_detach(device_t dev)
|
|
{
|
|
struct amdtemp_softc *sc = device_get_softc(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < sc->sc_ncores; i++)
|
|
if (sc->sc_sysctl_cpu[i] != NULL)
|
|
sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
|
|
|
|
/* NewBus removes the dev.amdtemp.N tree by itself. */
|
|
|
|
mtx_destroy(&sc->sc_lock);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
device_t dev = (device_t)arg1;
|
|
struct amdtemp_softc *sc = device_get_softc(dev);
|
|
amdsensor_t sensor = (amdsensor_t)arg2;
|
|
int32_t auxtemp[2], temp;
|
|
int error;
|
|
|
|
switch (sensor) {
|
|
case CORE0:
|
|
auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);
|
|
auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1);
|
|
temp = imax(auxtemp[0], auxtemp[1]);
|
|
break;
|
|
case CORE1:
|
|
auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);
|
|
auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1);
|
|
temp = imax(auxtemp[0], auxtemp[1]);
|
|
break;
|
|
default:
|
|
temp = sc->sc_gettemp(dev, sensor);
|
|
break;
|
|
}
|
|
error = sysctl_handle_int(oidp, &temp, 0, req);
|
|
|
|
return (error);
|
|
}
|
|
|
|
#define AMDTEMP_ZERO_C_TO_K 2731
|
|
|
|
static int32_t
|
|
amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
|
|
{
|
|
struct amdtemp_softc *sc = device_get_softc(dev);
|
|
uint32_t mask, offset, temp;
|
|
|
|
mtx_lock(&sc->sc_lock);
|
|
|
|
/* Set Sensor/Core selector. */
|
|
temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
|
|
temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR);
|
|
switch (sensor) {
|
|
case CORE0_SENSOR1:
|
|
temp |= AMDTEMP_TTSR_SELSENSOR;
|
|
/* FALLTHROUGH */
|
|
case CORE0_SENSOR0:
|
|
case CORE0:
|
|
if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
|
|
temp |= AMDTEMP_TTSR_SELCORE;
|
|
break;
|
|
case CORE1_SENSOR1:
|
|
temp |= AMDTEMP_TTSR_SELSENSOR;
|
|
/* FALLTHROUGH */
|
|
case CORE1_SENSOR0:
|
|
case CORE1:
|
|
if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
|
|
temp |= AMDTEMP_TTSR_SELCORE;
|
|
break;
|
|
default:
|
|
__assert_unreachable();
|
|
}
|
|
pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1);
|
|
|
|
mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
|
|
offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;
|
|
temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
|
|
temp = ((temp >> 14) & mask) * 5 / 2;
|
|
temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10;
|
|
|
|
mtx_unlock(&sc->sc_lock);
|
|
return (temp);
|
|
}
|
|
|
|
static uint32_t
|
|
amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49)
|
|
{
|
|
uint32_t temp;
|
|
|
|
/* Convert raw register subfield units (0.125C) to units of 0.1C. */
|
|
temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4;
|
|
|
|
if (minus49)
|
|
temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
|
|
|
|
temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10;
|
|
return (temp);
|
|
}
|
|
|
|
static uint32_t
|
|
amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val)
|
|
{
|
|
bool minus49;
|
|
|
|
/*
|
|
* On Family 15h and higher, if CurTmpTjSel is 11b, the range is
|
|
* adjusted down by 49.0 degrees Celsius. (This adjustment is not
|
|
* documented in BKDGs prior to family 15h model 00h.)
|
|
*/
|
|
minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&
|
|
((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) &
|
|
AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3);
|
|
|
|
return (amdtemp_decode_fam10h_to_17h(sc_offset,
|
|
val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
|
|
}
|
|
|
|
static uint32_t
|
|
amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val)
|
|
{
|
|
bool minus49;
|
|
|
|
minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
|
|
|| ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL);
|
|
return (amdtemp_decode_fam10h_to_17h(sc_offset,
|
|
val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
|
|
}
|
|
|
|
static int32_t
|
|
amdtemp_gettemp(device_t dev, amdsensor_t sensor)
|
|
{
|
|
struct amdtemp_softc *sc = device_get_softc(dev);
|
|
uint32_t temp;
|
|
|
|
temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
|
|
return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp));
|
|
}
|
|
|
|
static int32_t
|
|
amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor)
|
|
{
|
|
struct amdtemp_softc *sc = device_get_softc(dev);
|
|
uint32_t val;
|
|
int error __diagused;
|
|
|
|
error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val);
|
|
KASSERT(error == 0, ("amdsmn_read"));
|
|
return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val));
|
|
}
|
|
|
|
static int32_t
|
|
amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
|
|
{
|
|
struct amdtemp_softc *sc = device_get_softc(dev);
|
|
uint32_t val;
|
|
int error __diagused;
|
|
|
|
switch (sensor) {
|
|
case CORE0_SENSOR0:
|
|
/* Tctl */
|
|
error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
|
|
KASSERT(error == 0, ("amdsmn_read"));
|
|
return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val));
|
|
case CCD_BASE ... CCD_MAX:
|
|
/* Tccd<N> */
|
|
error = amdsmn_read(sc->sc_smn, sc->sc_temp_base +
|
|
(((int)sensor - CCD_BASE) * sizeof(val)), &val);
|
|
KASSERT(error == 0, ("amdsmn_read2"));
|
|
KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0,
|
|
("sensor %d: not valid", (int)sensor));
|
|
return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true));
|
|
default:
|
|
__assert_unreachable();
|
|
}
|
|
}
|
|
|
|
static void
|
|
amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg)
|
|
{
|
|
char sensor_name[16], sensor_descr[32];
|
|
struct amdtemp_softc *sc;
|
|
uint32_t i, val;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < maxreg; i++) {
|
|
error = amdsmn_read(sc->sc_smn, sc->sc_temp_base +
|
|
(i * sizeof(val)), &val);
|
|
if (error != 0)
|
|
continue;
|
|
if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0)
|
|
continue;
|
|
|
|
snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i);
|
|
snprintf(sensor_descr, sizeof(sensor_descr),
|
|
"CCD %u temperature (Tccd%u)", i, i);
|
|
|
|
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
|
|
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
|
|
sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr);
|
|
}
|
|
}
|
|
|
|
static void
|
|
amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model)
|
|
{
|
|
uint32_t maxreg;
|
|
|
|
switch (model) {
|
|
case 0x00 ... 0x2f: /* Zen1, Zen+ */
|
|
maxreg = 4;
|
|
break;
|
|
case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
|
|
case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
|
|
case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
|
|
maxreg = 8;
|
|
_Static_assert((int)NUM_CCDS >= 8, "");
|
|
break;
|
|
default:
|
|
device_printf(dev,
|
|
"Unrecognized Family 17h Model: %02xh\n", model);
|
|
return;
|
|
}
|
|
|
|
amdtemp_probe_ccd_sensors(dev, maxreg);
|
|
}
|
|
|
|
static void
|
|
amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model)
|
|
{
|
|
struct amdtemp_softc *sc = device_get_softc(dev);
|
|
uint32_t maxreg;
|
|
|
|
switch (model) {
|
|
case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
|
|
case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
|
|
maxreg = 8;
|
|
_Static_assert((int)NUM_CCDS >= 8, "");
|
|
break;
|
|
case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
|
|
sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE;
|
|
maxreg = 8;
|
|
_Static_assert((int)NUM_CCDS >= 8, "");
|
|
break;
|
|
default:
|
|
device_printf(dev,
|
|
"Unrecognized Family 19h Model: %02xh\n", model);
|
|
return;
|
|
}
|
|
|
|
amdtemp_probe_ccd_sensors(dev, maxreg);
|
|
}
|