707 lines
18 KiB
C
707 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2007 The DragonFly Project. All rights reserved.
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*
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* This code is derived from software contributed to The DragonFly Project
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* by Sepherosa Ziehau <sepherosa@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of The DragonFly Project nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific, prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.14 2008/02/15 11:15:38 sephe Exp $
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*/
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#ifndef _IF_BWIVAR_H
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#define _IF_BWIVAR_H
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#define BWI_ALIGN 0x1000
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#define BWI_RING_ALIGN BWI_ALIGN
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#define BWI_BUS_SPACE_MAXADDR 0x3fffffff
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#define BWI_TX_NRING 6
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#define BWI_TXRX_NRING 6
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#define BWI_TX_NDESC 128
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#define BWI_RX_NDESC 64
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#define BWI_TXSTATS_NDESC 64
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#define BWI_TX_NSPRDESC 2
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#define BWI_TX_DATA_RING 1
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/* XXX Onoe/Sample/AMRR probably need different configuration */
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#define BWI_SHRETRY 7
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#define BWI_LGRETRY 4
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#define BWI_SHRETRY_FB 3
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#define BWI_LGRETRY_FB 2
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#define BWI_LED_EVENT_NONE -1
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#define BWI_LED_EVENT_POLL 0
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#define BWI_LED_EVENT_TX 1
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#define BWI_LED_EVENT_RX 2
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#define BWI_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2)
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enum bwi_txpwrcb_type {
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BWI_TXPWR_INIT = 0,
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BWI_TXPWR_FORCE = 1,
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BWI_TXPWR_CALIB = 2
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};
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#define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */
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#define BWI_FRAME_MIN_LEN(hdr) \
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((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
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#define CSR_SETBITS_4(sc, reg, bits) \
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CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
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#define CSR_SETBITS_2(sc, reg, bits) \
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CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
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#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
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CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
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#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
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CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
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#define CSR_CLRBITS_4(sc, reg, bits) \
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CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
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#define CSR_CLRBITS_2(sc, reg, bits) \
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CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
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#ifdef BWI_DEBUG
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#define DPRINTF(sc, dbg, fmt, ...) \
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do { \
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if ((sc)->sc_debug & (dbg)) \
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device_printf((sc)->sc_dev, fmt, __VA_ARGS__); \
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} while (0)
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#define _DPRINTF(sc, dbg, fmt, ...) \
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do { \
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if ((sc)->sc_debug & (dbg)) \
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printf(fmt, __VA_ARGS__); \
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} while (0)
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#else /* !BWI_DEBUG */
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#define DPRINTF(sc, dbg, fmt, ...) ((void)0)
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#define _DPRINTF(sc, dbg, fmt, ...) ((void)0)
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#endif /* BWI_DEBUG */
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struct bwi_desc32 {
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/* Little endian */
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uint32_t ctrl;
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uint32_t addr; /* BWI_DESC32_A_ */
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} __packed;
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#define BWI_DESC32_A_FUNC_TXRX 0x1
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#define BWI_DESC32_A_FUNC_MASK __BITS(31, 30)
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#define BWI_DESC32_A_ADDR_MASK __BITS(29, 0)
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#define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0)
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#define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16)
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#define BWI_DESC32_C_EOR __BIT(28)
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#define BWI_DESC32_C_INTR __BIT(29)
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#define BWI_DESC32_C_FRAME_END __BIT(30)
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#define BWI_DESC32_C_FRAME_START __BIT(31)
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struct bwi_desc64 {
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/* Little endian */
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uint32_t ctrl0;
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uint32_t ctrl1;
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uint32_t addr_lo;
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uint32_t addr_hi;
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} __packed;
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struct bwi_rxbuf_hdr {
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/* Little endian */
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uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */
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uint8_t rxh_pad1[2];
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uint16_t rxh_flags1; /* BWI_RXH_F1_ */
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uint8_t rxh_rssi;
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uint8_t rxh_sq;
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uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */
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uint16_t rxh_flags3; /* BWI_RXH_F3_ */
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uint16_t rxh_flags2; /* BWI_RXH_F2_ */
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uint16_t rxh_tsf;
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uint8_t rxh_pad3[14]; /* Padded to 30bytes */
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} __packed;
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#define BWI_RXH_F1_BCM2053_RSSI __BIT(14)
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#define BWI_RXH_F1_SHPREAMBLE __BIT(7)
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#define BWI_RXH_F1_OFDM __BIT(0)
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#define BWI_RXH_F2_TYPE2FRAME __BIT(2)
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#define BWI_RXH_F3_BCM2050_RSSI __BIT(10)
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#define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14)
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struct bwi_txbuf_hdr {
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/* Little endian */
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uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */
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uint8_t txh_fc[2];
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uint16_t txh_unknown1;
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uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */
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uint8_t txh_ivs[16];
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uint8_t txh_addr1[IEEE80211_ADDR_LEN];
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uint16_t txh_unknown2;
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uint8_t txh_rts_fb_plcp[4];
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uint16_t txh_rts_fb_duration;
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uint8_t txh_fb_plcp[4];
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uint16_t txh_fb_duration;
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uint8_t txh_pad2[2];
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uint16_t txh_id; /* BWI_TXH_ID_ */
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uint16_t txh_unknown3;
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uint8_t txh_rts_plcp[6];
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uint8_t txh_rts_fc[2];
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uint16_t txh_rts_duration;
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uint8_t txh_rts_ra[IEEE80211_ADDR_LEN];
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uint8_t txh_rts_ta[IEEE80211_ADDR_LEN];
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uint8_t txh_pad3[2];
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uint8_t txh_plcp[6];
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} __packed;
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#define BWI_TXH_ID_RING_MASK __BITS(15, 13)
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#define BWI_TXH_ID_IDX_MASK __BITS(12, 0)
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#define BWI_TXH_PHY_C_OFDM __BIT(0)
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#define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4)
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#define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8)
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#define BWI_TXH_MAC_C_ACK __BIT(0)
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#define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3)
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#define BWI_TXH_MAC_C_HWSEQ __BIT(4)
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#define BWI_TXH_MAC_C_FB_OFDM __BIT(8)
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struct bwi_txstats {
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/* Little endian */
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uint8_t txs_pad1[4];
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uint16_t txs_id;
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uint8_t txs_flags; /* BWI_TXS_F_ */
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uint8_t txs_txcnt; /* BWI_TXS_TXCNT_ */
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uint8_t txs_pad2[2];
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uint16_t txs_seq;
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uint16_t txs_unknown;
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uint8_t txs_pad3[2]; /* Padded to 16bytes */
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} __packed;
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#define BWI_TXS_TXCNT_DATA __BITS(7, 4)
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#define BWI_TXS_F_ACKED __BIT(0)
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#define BWI_TXS_F_PENDING __BIT(5)
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struct bwi_ring_data {
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uint32_t rdata_txrx_ctrl;
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bus_dmamap_t rdata_dmap;
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bus_addr_t rdata_paddr;
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void *rdata_desc;
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};
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struct bwi_txbuf {
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struct mbuf *tb_mbuf;
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bus_dmamap_t tb_dmap;
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struct ieee80211_node *tb_ni;
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int tb_rate[2];
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};
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struct bwi_txbuf_data {
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struct bwi_txbuf tbd_buf[BWI_TX_NDESC];
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int tbd_used;
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int tbd_idx;
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};
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struct bwi_rxbuf {
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struct mbuf *rb_mbuf;
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bus_addr_t rb_paddr;
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bus_dmamap_t rb_dmap;
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};
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struct bwi_rxbuf_data {
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struct bwi_rxbuf rbd_buf[BWI_RX_NDESC];
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bus_dmamap_t rbd_tmp_dmap;
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int rbd_idx;
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};
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struct bwi_txstats_data {
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bus_dma_tag_t stats_ring_dtag;
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bus_dmamap_t stats_ring_dmap;
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bus_addr_t stats_ring_paddr;
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void *stats_ring;
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bus_dma_tag_t stats_dtag;
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bus_dmamap_t stats_dmap;
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bus_addr_t stats_paddr;
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struct bwi_txstats *stats;
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uint32_t stats_ctrl_base;
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int stats_idx;
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};
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struct bwi_fwhdr {
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/* Big endian */
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uint8_t fw_type; /* BWI_FW_T_ */
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uint8_t fw_gen; /* BWI_FW_GEN */
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uint8_t fw_pad[2];
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uint32_t fw_size;
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#define fw_iv_cnt fw_size
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} __packed;
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#define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr)
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#define BWI_FW_T_UCODE 'u'
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#define BWI_FW_T_PCM 'p'
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#define BWI_FW_T_IV 'i'
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#define BWI_FW_GEN_1 1
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#define BWI_FW_VERSION3 3
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#define BWI_FW_VERSION4 4
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#define BWI_FW_VERSION3_REVMAX 0x128
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#define BWI_FW_PATH "bwi_v%d_"
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#define BWI_FW_STUB_PATH BWI_FW_PATH "ucode"
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#define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d"
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#define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d"
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#define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d"
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#define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d"
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struct bwi_fw_iv {
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/* Big endian */
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uint16_t iv_ofs;
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union {
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uint32_t val32;
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uint16_t val16;
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} __packed iv_val;
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} __packed;
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#define BWI_FW_IV_OFS_MASK __BITS(14, 0)
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#define BWI_FW_IV_IS_32BIT __BIT(15)
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struct bwi_led {
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uint8_t l_flags; /* BWI_LED_F_ */
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uint8_t l_act; /* BWI_LED_ACT_ */
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uint8_t l_mask;
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};
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#define BWI_LED_F_ACTLOW 0x1
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#define BWI_LED_F_BLINK 0x2
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#define BWI_LED_F_POLLABLE 0x4
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#define BWI_LED_F_SLOW 0x8
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enum bwi_clock_mode {
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BWI_CLOCK_MODE_SLOW,
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BWI_CLOCK_MODE_FAST,
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BWI_CLOCK_MODE_DYN
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};
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struct bwi_regwin {
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uint32_t rw_flags; /* BWI_REGWIN_F_ */
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uint16_t rw_type; /* BWI_REGWIN_T_ */
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uint8_t rw_id;
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uint8_t rw_rev;
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};
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#define BWI_REGWIN_F_EXIST 0x1
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#define BWI_CREATE_REGWIN(rw, id, type, rev) \
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do { \
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(rw)->rw_flags = BWI_REGWIN_F_EXIST; \
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(rw)->rw_type = (type); \
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(rw)->rw_id = (id); \
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(rw)->rw_rev = (rev); \
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} while (0)
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#define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST)
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#define BWI_GPIO_REGWIN(sc) \
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(BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
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&(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
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struct bwi_mac;
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struct bwi_phy {
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enum ieee80211_phymode phy_mode;
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int phy_rev;
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int phy_version;
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uint32_t phy_flags; /* BWI_PHY_F_ */
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uint16_t phy_tbl_ctrl;
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uint16_t phy_tbl_data_lo;
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uint16_t phy_tbl_data_hi;
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void (*phy_init)(struct bwi_mac *);
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};
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#define BWI_PHY_F_CALIBRATED 0x1
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#define BWI_PHY_F_LINKED 0x2
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#define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED)
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/* TX power control */
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struct bwi_tpctl {
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uint16_t bbp_atten; /* BBP attenuation: 4bits */
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uint16_t rf_atten; /* RF attenuation */
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uint16_t tp_ctrl1; /* ??: 3bits */
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uint16_t tp_ctrl2; /* ??: 4bits */
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};
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#define BWI_RF_ATTEN_FACTOR 4
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#define BWI_RF_ATTEN_MAX0 9
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#define BWI_RF_ATTEN_MAX1 31
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#define BWI_BBP_ATTEN_MAX 11
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#define BWI_TPCTL1_MAX 7
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struct bwi_rf_lo {
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int8_t ctrl_lo;
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int8_t ctrl_hi;
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};
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struct bwi_rf {
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uint16_t rf_type; /* BWI_RF_T_ */
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uint16_t rf_manu;
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int rf_rev;
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uint32_t rf_flags; /* BWI_RF_F_ */
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#define BWI_RFLO_MAX 56
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struct bwi_rf_lo rf_lo[BWI_RFLO_MAX];
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uint8_t rf_lo_used[8];
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#define BWI_INVALID_NRSSI -1000
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int16_t rf_nrssi[2]; /* Narrow RSSI */
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int32_t rf_nrssi_slope;
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#define BWI_NRSSI_TBLSZ 64
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int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ];
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uint16_t rf_lo_gain; /* loopback gain */
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uint16_t rf_rx_gain; /* TRSW RX gain */
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uint16_t rf_calib; /* RF calibration value */
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u_int rf_curchan; /* current channel */
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uint16_t rf_ctrl_rd;
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int rf_ctrl_adj;
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void (*rf_off)(struct bwi_mac *);
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void (*rf_on)(struct bwi_mac *);
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void (*rf_set_nrssi_thr)(struct bwi_mac *);
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void (*rf_calc_nrssi_slope)(struct bwi_mac *);
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int (*rf_calc_rssi)
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(struct bwi_mac *,
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const struct bwi_rxbuf_hdr *);
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int (*rf_calc_noise)(struct bwi_mac *);
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void (*rf_lo_update)(struct bwi_mac *);
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#define BWI_TSSI_MAX 64
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int8_t rf_txpower_map0[BWI_TSSI_MAX];
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/* Indexed by TSSI */
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int rf_idle_tssi0;
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int8_t rf_txpower_map[BWI_TSSI_MAX];
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int rf_idle_tssi;
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int rf_base_tssi;
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int rf_txpower_max; /* dBm */
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int rf_ant_mode; /* BWI_ANT_MODE_ */
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};
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#define BWI_RF_F_INITED 0x1
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#define BWI_RF_F_ON 0x2
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#define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED)
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#define BWI_ANT_MODE_0 0
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#define BWI_ANT_MODE_1 1
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#define BWI_ANT_MODE_UNKN 2
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#define BWI_ANT_MODE_AUTO 3
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struct bwi_softc;
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struct firmware;
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struct bwi_mac {
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struct bwi_regwin mac_regwin; /* MUST be first field */
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#define mac_rw_flags mac_regwin.rw_flags
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#define mac_type mac_regwin.rw_type
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#define mac_id mac_regwin.rw_id
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#define mac_rev mac_regwin.rw_rev
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struct bwi_softc *mac_sc;
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struct bwi_phy mac_phy; /* PHY I/F */
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struct bwi_rf mac_rf; /* RF I/F */
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struct bwi_tpctl mac_tpctl; /* TX power control */
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uint32_t mac_flags; /* BWI_MAC_F_ */
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const struct firmware *mac_stub;
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const struct firmware *mac_ucode;
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const struct firmware *mac_pcm;
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const struct firmware *mac_iv;
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const struct firmware *mac_iv_ext;
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};
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#define BWI_MAC_F_BSWAP 0x1
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#define BWI_MAC_F_TPCTL_INITED 0x2
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#define BWI_MAC_F_HAS_TXSTATS 0x4
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#define BWI_MAC_F_INITED 0x8
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#define BWI_MAC_F_ENABLED 0x10
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#define BWI_MAC_F_LOCKED 0x20 /* for debug */
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#define BWI_MAC_F_TPCTL_ERROR 0x40
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#define BWI_MAC_F_PHYE_RESET 0x80
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#define BWI_CREATE_MAC(mac, sc, id, rev) \
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do { \
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BWI_CREATE_REGWIN(&(mac)->mac_regwin, \
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(id), \
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BWI_REGWIN_T_MAC, \
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(rev)); \
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(mac)->mac_sc = (sc); \
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} while (0)
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#define BWI_MAC_MAX 2
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#define BWI_LED_MAX 4
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enum bwi_bus_space {
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BWI_BUS_SPACE_30BIT = 1,
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BWI_BUS_SPACE_32BIT,
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BWI_BUS_SPACE_64BIT
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};
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#define BWI_TX_RADIOTAP_PRESENT \
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((1 << IEEE80211_RADIOTAP_FLAGS) | \
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(1 << IEEE80211_RADIOTAP_RATE) | \
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(1 << IEEE80211_RADIOTAP_CHANNEL))
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struct bwi_tx_radiotap_hdr {
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struct ieee80211_radiotap_header wt_ihdr;
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uint8_t wt_flags;
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uint8_t wt_rate;
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uint16_t wt_chan_freq;
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uint16_t wt_chan_flags;
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} __packed;
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#define BWI_RX_RADIOTAP_PRESENT \
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((1 << IEEE80211_RADIOTAP_TSFT) | \
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(1 << IEEE80211_RADIOTAP_FLAGS) | \
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(1 << IEEE80211_RADIOTAP_RATE) | \
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(1 << IEEE80211_RADIOTAP_CHANNEL) | \
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(1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
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(1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
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struct bwi_rx_radiotap_hdr {
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struct ieee80211_radiotap_header wr_ihdr;
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uint64_t wr_tsf;
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uint8_t wr_flags;
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uint8_t wr_rate;
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uint16_t wr_chan_freq;
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uint16_t wr_chan_flags;
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int8_t wr_antsignal;
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int8_t wr_antnoise;
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/* TODO: sq */
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} __packed __aligned(8);
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struct bwi_vap {
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struct ieee80211vap bv_vap;
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int (*bv_newstate)(struct ieee80211vap *,
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enum ieee80211_state, int);
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};
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#define BWI_VAP(vap) ((struct bwi_vap *)(vap))
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struct bwi_softc {
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uint32_t sc_flags; /* BWI_F_ */
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device_t sc_dev;
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struct mtx sc_mtx;
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struct ieee80211com sc_ic;
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struct mbufq sc_snd;
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int sc_invalid;
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uint32_t sc_cap; /* BWI_CAP_ */
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uint16_t sc_bbp_id; /* BWI_BBPID_ */
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uint8_t sc_bbp_rev;
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uint8_t sc_bbp_pkg;
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uint8_t sc_pci_revid;
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uint16_t sc_pci_did;
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uint16_t sc_pci_subvid;
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uint16_t sc_pci_subdid;
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uint16_t sc_card_flags; /* BWI_CARD_F_ */
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uint16_t sc_pwron_delay;
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int sc_locale;
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int sc_irq_rid;
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struct resource *sc_irq_res;
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void *sc_irq_handle;
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int sc_mem_rid;
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struct resource *sc_mem_res;
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bus_space_tag_t sc_mem_bt;
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bus_space_handle_t sc_mem_bh;
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struct callout sc_calib_ch;
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struct callout sc_watchdog_timer;
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struct bwi_regwin *sc_cur_regwin;
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struct bwi_regwin sc_com_regwin;
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struct bwi_regwin sc_bus_regwin;
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int sc_nmac;
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struct bwi_mac sc_mac[BWI_MAC_MAX];
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int sc_rx_rate;
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int sc_tx_rate;
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enum bwi_txpwrcb_type sc_txpwrcb_type;
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int sc_led_blinking;
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int sc_led_ticks;
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struct bwi_led *sc_blink_led;
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struct callout sc_led_blink_ch;
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int sc_led_blink_offdur;
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struct bwi_led sc_leds[BWI_LED_MAX];
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enum bwi_bus_space sc_bus_space;
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bus_dma_tag_t sc_parent_dtag;
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bus_dma_tag_t sc_buf_dtag;
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struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING];
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struct bwi_rxbuf_data sc_rx_bdata;
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bus_dma_tag_t sc_txring_dtag;
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struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING];
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bus_dma_tag_t sc_rxring_dtag;
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struct bwi_ring_data sc_rx_rdata;
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struct bwi_txstats_data *sc_txstats;
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int sc_tx_timer;
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const struct ieee80211_rate_table *sc_rates;
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struct bwi_tx_radiotap_hdr sc_tx_th;
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struct bwi_rx_radiotap_hdr sc_rx_th;
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struct taskqueue *sc_tq;
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struct task sc_restart_task;
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int (*sc_init_tx_ring)(struct bwi_softc *, int);
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void (*sc_free_tx_ring)(struct bwi_softc *, int);
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int (*sc_init_rx_ring)(struct bwi_softc *);
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void (*sc_free_rx_ring)(struct bwi_softc *);
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int (*sc_init_txstats)(struct bwi_softc *);
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void (*sc_free_txstats)(struct bwi_softc *);
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void (*sc_setup_rxdesc)
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(struct bwi_softc *, int, bus_addr_t, int);
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int (*sc_rxeof)(struct bwi_softc *);
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void (*sc_setup_txdesc)
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(struct bwi_softc *, struct bwi_ring_data *,
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int, bus_addr_t, int);
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void (*sc_start_tx)
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(struct bwi_softc *, uint32_t, int);
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void (*sc_txeof_status)(struct bwi_softc *);
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/* Sysctl variables */
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int sc_fw_version; /* BWI_FW_VERSION[34] */
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int sc_dwell_time; /* milliseconds */
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int sc_led_idle;
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int sc_led_blink;
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int sc_txpwr_calib;
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uint32_t sc_debug; /* BWI_DBG_ */
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};
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#define BWI_F_BUS_INITED 0x1
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#define BWI_F_PROMISC 0x2
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#define BWI_F_STOP 0x4
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#define BWI_F_RUNNING 0x8
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#define BWI_DBG_MAC 0x00000001
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#define BWI_DBG_RF 0x00000002
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#define BWI_DBG_PHY 0x00000004
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#define BWI_DBG_MISC 0x00000008
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#define BWI_DBG_ATTACH 0x00000010
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#define BWI_DBG_INIT 0x00000020
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#define BWI_DBG_FIRMWARE 0x00000040
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#define BWI_DBG_80211 0x00000080
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#define BWI_DBG_TXPOWER 0x00000100
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#define BWI_DBG_INTR 0x00000200
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#define BWI_DBG_RX 0x00000400
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#define BWI_DBG_TX 0x00000800
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#define BWI_DBG_TXEOF 0x00001000
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#define BWI_DBG_LED 0x00002000
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#define BWI_LOCK_INIT(sc) \
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mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \
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MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
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#define BWI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
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#define BWI_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define BWI_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define BWI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
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int bwi_attach(struct bwi_softc *);
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int bwi_detach(struct bwi_softc *);
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void bwi_suspend(struct bwi_softc *);
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void bwi_resume(struct bwi_softc *);
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int bwi_shutdown(struct bwi_softc *);
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void bwi_intr(void *);
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int bwi_bus_init(struct bwi_softc *, struct bwi_mac *mac);
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uint16_t bwi_read_sprom(struct bwi_softc *, uint16_t);
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int bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *,
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struct bwi_regwin **);
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int bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *);
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void bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *,
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uint32_t);
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void bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *,
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uint32_t);
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#define abs(a) __builtin_abs(a)
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/* XXX does not belong here */
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struct ieee80211_ds_plcp_hdr {
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uint8_t i_signal;
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uint8_t i_service;
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uint16_t i_length;
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uint16_t i_crc;
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} __packed;
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#endif /* !_IF_BWIVAR_H */
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