558 lines
14 KiB
C
558 lines
14 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef ENA_H
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#define ENA_H
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#include "opt_rss.h"
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#include "ena-com/ena_com.h"
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#include "ena-com/ena_eth_com.h"
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#define ENA_DRV_MODULE_VER_MAJOR 2
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#define ENA_DRV_MODULE_VER_MINOR 6
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#define ENA_DRV_MODULE_VER_SUBMINOR 3
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#define ENA_DRV_MODULE_NAME "ena"
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#ifndef ENA_DRV_MODULE_VERSION
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#define ENA_DRV_MODULE_VERSION \
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__XSTRING(ENA_DRV_MODULE_VER_MAJOR) "." \
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__XSTRING(ENA_DRV_MODULE_VER_MINOR) "." \
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__XSTRING(ENA_DRV_MODULE_VER_SUBMINOR)
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#endif
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#define ENA_DEVICE_NAME "Elastic Network Adapter (ENA)"
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#define ENA_DEVICE_DESC "ENA adapter"
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/* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
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#define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
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/* 1 for AENQ + ADMIN */
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#define ENA_ADMIN_MSIX_VEC 1
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#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
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#define ENA_REG_BAR 0
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#define ENA_MEM_BAR 2
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#define ENA_BUS_DMA_SEGS 32
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#define ENA_DEFAULT_BUF_RING_SIZE 4096
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#define ENA_DEFAULT_RING_SIZE 1024
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#define ENA_MIN_RING_SIZE 256
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/*
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* Refill Rx queue when number of required descriptors is above
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* QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
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*/
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#define ENA_RX_REFILL_THRESH_DIVIDER 8
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#define ENA_RX_REFILL_THRESH_PACKET 256
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#define ENA_IRQNAME_SIZE 40
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#define ENA_PKT_MAX_BUFS 19
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#define ENA_RX_RSS_TABLE_LOG_SIZE 7
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#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
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#define ENA_HASH_KEY_SIZE 40
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#define ENA_MAX_FRAME_LEN 10000
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#define ENA_MIN_FRAME_LEN 60
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#define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2)
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#define ENA_DB_THRESHOLD 64
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#define ENA_TX_COMMIT 32
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/*
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* TX budget for cleaning. It should be half of the RX budget to reduce amount
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* of TCP retransmissions.
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*/
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#define ENA_TX_BUDGET 128
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/* RX cleanup budget. -1 stands for infinity. */
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#define ENA_RX_BUDGET 256
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/*
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* How many times we can repeat cleanup in the io irq handling routine if the
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* RX or TX budget was depleted.
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*/
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#define ENA_CLEAN_BUDGET 8
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#define ENA_RX_IRQ_INTERVAL 20
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#define ENA_TX_IRQ_INTERVAL 50
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#define ENA_MIN_MTU 128
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#define ENA_TSO_MAXSIZE 65536
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#define ENA_MMIO_DISABLE_REG_READ BIT(0)
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#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
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#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
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#define ENA_IO_TXQ_IDX(q) (2 * (q))
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#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
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#define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
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#define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
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#define ENA_MGMNT_IRQ_IDX 0
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#define ENA_IO_IRQ_FIRST_IDX 1
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#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
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#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
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/*
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* ENA device should send keep alive msg every 1 sec.
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* We wait for 6 sec just to be on the safe side.
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*/
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#define ENA_DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6)
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/* Time in jiffies before concluding the transmitter is hung. */
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#define ENA_DEFAULT_TX_CMP_TO (SBT_1S * 5)
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/* Number of queues to check for missing queues per timer tick */
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#define ENA_DEFAULT_TX_MONITORED_QUEUES (4)
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/* Max number of timeouted packets before device reset */
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#define ENA_DEFAULT_TX_CMP_THRESHOLD (128)
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/*
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* Supported PCI vendor and devices IDs
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*/
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#define PCI_VENDOR_ID_AMAZON 0x1d0f
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#define PCI_DEV_ID_ENA_PF 0x0ec2
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#define PCI_DEV_ID_ENA_PF_RSERV0 0x1ec2
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#define PCI_DEV_ID_ENA_VF 0xec20
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#define PCI_DEV_ID_ENA_VF_RSERV0 0xec21
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/*
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* Flags indicating current ENA driver state
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*/
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enum ena_flags_t {
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ENA_FLAG_DEVICE_RUNNING,
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ENA_FLAG_DEV_UP,
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ENA_FLAG_LINK_UP,
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ENA_FLAG_MSIX_ENABLED,
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ENA_FLAG_TRIGGER_RESET,
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ENA_FLAG_ONGOING_RESET,
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ENA_FLAG_DEV_UP_BEFORE_RESET,
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ENA_FLAG_RSS_ACTIVE,
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ENA_FLAGS_NUMBER = ENA_FLAG_RSS_ACTIVE
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};
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BITSET_DEFINE(_ena_state, ENA_FLAGS_NUMBER);
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typedef struct _ena_state ena_state_t;
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#define ENA_FLAG_ZERO(adapter) \
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BIT_ZERO(ENA_FLAGS_NUMBER, &(adapter)->flags)
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#define ENA_FLAG_ISSET(bit, adapter) \
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BIT_ISSET(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags)
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#define ENA_FLAG_SET_ATOMIC(bit, adapter) \
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BIT_SET_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags)
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#define ENA_FLAG_CLEAR_ATOMIC(bit, adapter) \
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BIT_CLR_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags)
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struct msix_entry {
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int entry;
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int vector;
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};
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typedef struct _ena_vendor_info_t {
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uint16_t vendor_id;
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uint16_t device_id;
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unsigned int index;
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} ena_vendor_info_t;
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struct ena_irq {
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/* Interrupt resources */
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struct resource *res;
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driver_filter_t *handler;
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void *data;
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void *cookie;
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unsigned int vector;
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bool requested;
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#ifdef RSS
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int cpu;
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#endif
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char name[ENA_IRQNAME_SIZE];
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};
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struct ena_que {
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struct ena_adapter *adapter;
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struct ena_ring *tx_ring;
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struct ena_ring *rx_ring;
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struct task cleanup_task;
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struct taskqueue *cleanup_tq;
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uint32_t id;
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#ifdef RSS
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int cpu;
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cpuset_t cpu_mask;
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#endif
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int domain;
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struct sysctl_oid *oid;
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};
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struct ena_calc_queue_size_ctx {
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struct ena_com_dev_get_features_ctx *get_feat_ctx;
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struct ena_com_dev *ena_dev;
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device_t pdev;
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uint32_t tx_queue_size;
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uint32_t rx_queue_size;
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uint32_t max_tx_queue_size;
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uint32_t max_rx_queue_size;
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uint16_t max_tx_sgl_size;
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uint16_t max_rx_sgl_size;
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};
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#ifdef DEV_NETMAP
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struct ena_netmap_tx_info {
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uint32_t socket_buf_idx[ENA_PKT_MAX_BUFS];
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bus_dmamap_t map_seg[ENA_PKT_MAX_BUFS];
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unsigned int sockets_used;
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};
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#endif
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struct ena_tx_buffer {
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struct mbuf *mbuf;
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/* # of ena desc for this specific mbuf
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* (includes data desc and metadata desc) */
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unsigned int tx_descs;
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/* # of buffers used by this mbuf */
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unsigned int num_of_bufs;
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bus_dmamap_t dmamap;
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/* Used to detect missing tx packets */
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struct bintime timestamp;
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bool print_once;
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#ifdef DEV_NETMAP
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struct ena_netmap_tx_info nm_info;
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#endif /* DEV_NETMAP */
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struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
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} __aligned(CACHE_LINE_SIZE);
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struct ena_rx_buffer {
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struct mbuf *mbuf;
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bus_dmamap_t map;
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struct ena_com_buf ena_buf;
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#ifdef DEV_NETMAP
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uint32_t netmap_buf_idx;
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#endif /* DEV_NETMAP */
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} __aligned(CACHE_LINE_SIZE);
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struct ena_stats_tx {
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counter_u64_t cnt;
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counter_u64_t bytes;
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counter_u64_t prepare_ctx_err;
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counter_u64_t dma_mapping_err;
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counter_u64_t doorbells;
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counter_u64_t missing_tx_comp;
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counter_u64_t bad_req_id;
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counter_u64_t collapse;
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counter_u64_t collapse_err;
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counter_u64_t queue_wakeup;
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counter_u64_t queue_stop;
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counter_u64_t llq_buffer_copy;
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counter_u64_t unmask_interrupt_num;
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};
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struct ena_stats_rx {
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counter_u64_t cnt;
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counter_u64_t bytes;
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counter_u64_t refil_partial;
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counter_u64_t csum_bad;
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counter_u64_t mjum_alloc_fail;
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counter_u64_t mbuf_alloc_fail;
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counter_u64_t dma_mapping_err;
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counter_u64_t bad_desc_num;
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counter_u64_t bad_req_id;
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counter_u64_t empty_rx_ring;
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counter_u64_t csum_good;
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};
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struct ena_ring {
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/* Holds the empty requests for TX/RX out of order completions */
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union {
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uint16_t *free_tx_ids;
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uint16_t *free_rx_ids;
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};
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struct ena_com_dev *ena_dev;
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struct ena_adapter *adapter;
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struct ena_com_io_cq *ena_com_io_cq;
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struct ena_com_io_sq *ena_com_io_sq;
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uint16_t qid;
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/* Determines if device will use LLQ or normal mode for TX */
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enum ena_admin_placement_policy_type tx_mem_queue_type;
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union {
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/* The maximum length the driver can push to the device (For LLQ) */
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uint8_t tx_max_header_size;
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/* The maximum (and default) mbuf size for the Rx descriptor. */
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uint16_t rx_mbuf_sz;
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};
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uint8_t first_interrupt;
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uint16_t no_interrupt_event_cnt;
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struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
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struct ena_que *que;
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struct lro_ctrl lro;
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uint16_t next_to_use;
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uint16_t next_to_clean;
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union {
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struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
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struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
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};
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int ring_size; /* number of tx/rx_buffer_info's entries */
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struct buf_ring *br; /* only for TX */
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uint32_t buf_ring_size;
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struct mtx ring_mtx;
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char mtx_name[16];
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struct {
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struct task enqueue_task;
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struct taskqueue *enqueue_tq;
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};
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union {
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struct ena_stats_tx tx_stats;
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struct ena_stats_rx rx_stats;
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};
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union {
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int empty_rx_queue;
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/* For Tx ring to indicate if it's running or not */
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bool running;
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};
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/* How many packets are sent in one Tx loop, used for doorbells */
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uint32_t acum_pkts;
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/* Used for LLQ */
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uint8_t *push_buf_intermediate_buf;
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int tx_last_cleanup_ticks;
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#ifdef DEV_NETMAP
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bool initialized;
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#endif /* DEV_NETMAP */
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} __aligned(CACHE_LINE_SIZE);
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struct ena_stats_dev {
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counter_u64_t wd_expired;
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counter_u64_t interface_up;
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counter_u64_t interface_down;
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counter_u64_t admin_q_pause;
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};
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struct ena_hw_stats {
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counter_u64_t rx_packets;
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counter_u64_t tx_packets;
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counter_u64_t rx_bytes;
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counter_u64_t tx_bytes;
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counter_u64_t rx_drops;
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counter_u64_t tx_drops;
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};
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/* Board specific private data structure */
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struct ena_adapter {
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struct ena_com_dev *ena_dev;
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/* OS defined structs */
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if_t ifp;
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device_t pdev;
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struct ifmedia media;
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/* OS resources */
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struct resource *memory;
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struct resource *registers;
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struct resource *msix;
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int msix_rid;
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/* MSI-X */
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struct msix_entry *msix_entries;
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int msix_vecs;
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/* DMA tags used throughout the driver adapter for Tx and Rx */
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bus_dma_tag_t tx_buf_tag;
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bus_dma_tag_t rx_buf_tag;
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int dma_width;
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uint32_t max_mtu;
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uint32_t num_io_queues;
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uint32_t max_num_io_queues;
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uint32_t requested_tx_ring_size;
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uint32_t requested_rx_ring_size;
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uint32_t max_tx_ring_size;
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uint32_t max_rx_ring_size;
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uint16_t max_tx_sgl_size;
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uint16_t max_rx_sgl_size;
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uint32_t tx_offload_cap;
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uint32_t buf_ring_size;
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/* RSS*/
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int first_bind;
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struct ena_indir *rss_indir;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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/* mdio and phy*/
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ena_state_t flags;
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/* Queue will represent one TX and one RX ring */
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struct ena_que que[ENA_MAX_NUM_IO_QUEUES]
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__aligned(CACHE_LINE_SIZE);
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/* TX */
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struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
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__aligned(CACHE_LINE_SIZE);
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/* RX */
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struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
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__aligned(CACHE_LINE_SIZE);
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struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
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/* Timer service */
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struct callout timer_service;
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sbintime_t keep_alive_timestamp;
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uint32_t next_monitored_tx_qid;
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struct task reset_task;
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struct taskqueue *reset_tq;
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struct task metrics_task;
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struct taskqueue *metrics_tq;
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int wd_active;
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sbintime_t keep_alive_timeout;
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sbintime_t missing_tx_timeout;
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uint32_t missing_tx_max_queues;
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uint32_t missing_tx_threshold;
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bool disable_meta_caching;
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uint16_t eni_metrics_sample_interval;
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uint16_t eni_metrics_sample_interval_cnt;
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/* Statistics */
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struct ena_stats_dev dev_stats;
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struct ena_hw_stats hw_stats;
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struct ena_admin_eni_stats eni_metrics;
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enum ena_regs_reset_reason_types reset_reason;
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};
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#define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
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#define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
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#define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
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#define ENA_RING_MTX_ASSERT(_ring) \
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mtx_assert(&(_ring)->ring_mtx, MA_OWNED)
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#define ENA_LOCK_INIT() \
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sx_init(&ena_global_lock, "ENA global lock")
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#define ENA_LOCK_DESTROY() sx_destroy(&ena_global_lock)
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#define ENA_LOCK_LOCK() sx_xlock(&ena_global_lock)
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#define ENA_LOCK_UNLOCK() sx_unlock(&ena_global_lock)
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#define ENA_LOCK_ASSERT() sx_assert(&ena_global_lock, SA_XLOCKED)
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#define ENA_TIMER_INIT(_adapter) \
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callout_init(&(_adapter)->timer_service, true)
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#define ENA_TIMER_DRAIN(_adapter) \
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callout_drain(&(_adapter)->timer_service)
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#define ENA_TIMER_RESET(_adapter) \
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callout_reset_sbt(&(_adapter)->timer_service, SBT_1S, SBT_1S, \
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ena_timer_service, (void*)(_adapter), 0)
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#define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
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#define clamp_val(val, lo, hi) clamp_t(__typeof(val), val, lo, hi)
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extern struct sx ena_global_lock;
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int ena_up(struct ena_adapter *adapter);
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void ena_down(struct ena_adapter *adapter);
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int ena_restore_device(struct ena_adapter *adapter);
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void ena_destroy_device(struct ena_adapter *adapter, bool graceful);
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int ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num);
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int ena_update_buf_ring_size(struct ena_adapter *adapter,
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uint32_t new_buf_ring_size);
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int ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size,
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uint32_t new_rx_size);
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int ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num);
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static inline int
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ena_mbuf_count(struct mbuf *mbuf)
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{
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int count = 1;
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while ((mbuf = mbuf->m_next) != NULL)
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++count;
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return count;
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}
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static inline void
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ena_trigger_reset(struct ena_adapter *adapter,
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enum ena_regs_reset_reason_types reset_reason)
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{
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if (likely(!ENA_FLAG_ISSET(ENA_FLAG_TRIGGER_RESET, adapter))) {
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adapter->reset_reason = reset_reason;
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ENA_FLAG_SET_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter);
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}
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}
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static inline void
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ena_ring_tx_doorbell(struct ena_ring *tx_ring)
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{
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ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
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counter_u64_add(tx_ring->tx_stats.doorbells, 1);
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tx_ring->acum_pkts = 0;
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}
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#endif /* !(ENA_H) */
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