This driver is based of the enic (Cisco VIC) DPDK driver. It provides basic ethernet functionality. Has been run with various VIC cards to do UEFI PXE boot with NFS root.
109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*/
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#ifndef _VNIC_WQ_H_
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#define _VNIC_WQ_H_
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#include "vnic_dev.h"
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#include "vnic_cq.h"
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/* Work queue control */
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struct vnic_wq_ctrl {
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u64 ring_base; /* 0x00 */
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#define TX_RING_BASE 0x00
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u32 ring_size; /* 0x08 */
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#define TX_RING_SIZE 0x08
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u32 pad0;
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u32 posted_index; /* 0x10 */
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#define TX_POSTED_INDEX 0x10
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u32 pad1;
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u32 cq_index; /* 0x18 */
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#define TX_CQ_INDEX 0x18
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u32 pad2;
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u32 enable; /* 0x20 */
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#define TX_ENABLE 0x20
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u32 pad3;
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u32 running; /* 0x28 */
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#define TX_RUNNING 0x28
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u32 pad4;
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u32 fetch_index; /* 0x30 */
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#define TX_FETCH_INDEX 0x30
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u32 pad5;
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u32 dca_value; /* 0x38 */
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#define TX_DCA_VALUE 0x38
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u32 pad6;
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u32 error_interrupt_enable; /* 0x40 */
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#define TX_ERROR_INTR_ENABLE 0x40
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u32 pad7;
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u32 error_interrupt_offset; /* 0x48 */
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#define TX_ERROR_INTR_OFFSET 0x48
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u32 pad8;
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u32 error_status; /* 0x50 */
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#define TX_ERROR_STATUS 0x50
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u32 pad9;
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};
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struct vnic_wq {
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unsigned int index;
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uint64_t tx_offload_notsup_mask;
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struct vnic_dev *vdev;
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struct vnic_res *ctrl;
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struct vnic_dev_ring ring;
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unsigned int head_idx;
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unsigned int cq_pend;
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unsigned int tail_idx;
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unsigned int socket_id;
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unsigned int processed;
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const struct rte_memzone *cqmsg_rz;
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uint16_t last_completed_index;
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uint64_t offloads;
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};
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static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
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{
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/* how many does SW own? */
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return wq->ring.desc_avail;
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}
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static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
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{
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/* how many does HW own? */
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return wq->ring.desc_count - wq->ring.desc_avail - 1;
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}
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#define PI_LOG2_CACHE_LINE_SIZE 5
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#define PI_INDEX_BITS 12
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#define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
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#define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
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#define PI_PREFETCH_LEN_OFF 16
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#define PI_PREFETCH_ADDR_BITS 43
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#define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
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#define PI_PREFETCH_ADDR_OFF 21
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static inline uint32_t
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buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
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{
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idx++;
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if (unlikely(idx == n_descriptors))
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idx = 0;
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return idx;
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}
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void vnic_wq_free(struct vnic_wq *wq);
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void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
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unsigned int fetch_index, unsigned int posted_index,
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unsigned int error_interrupt_enable,
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unsigned int error_interrupt_offset);
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void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
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unsigned int error_interrupt_enable,
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unsigned int error_interrupt_offset);
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void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
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unsigned int vnic_wq_error_status(struct vnic_wq *wq);
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void vnic_wq_enable(struct vnic_wq *wq);
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int vnic_wq_disable(struct vnic_wq *wq);
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void vnic_wq_clean(struct vnic_wq *wq);
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#endif /* _VNIC_WQ_H_ */
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