1081 lines
27 KiB
C
1081 lines
27 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* AMD Geode LX CS5536 System Management Bus controller.
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*
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* Although AMD refers to this device as an SMBus controller, it
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* really is an I2C controller (It lacks SMBus ALERT# and Alert
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* Response support).
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*
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* The driver is implemented as an interrupt-driven state machine,
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* supporting both master and slave mode.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#ifdef GLXIIC_DEBUG
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#include <sys/syslog.h>
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#endif
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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/* CS5536 PCI-ISA ID. */
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#define GLXIIC_CS5536_DEV_ID 0x20901022
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/* MSRs. */
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#define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021
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/* Bus speeds. */
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#define GLXIIC_SLOW 0x0258 /* 10 kHz. */
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#define GLXIIC_FAST 0x0078 /* 50 kHz. */
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#define GLXIIC_FASTEST 0x003c /* 100 kHz. */
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/* Default bus activity timeout in milliseconds. */
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#define GLXIIC_DEFAULT_TIMEOUT 35
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/* GPIO register offsets. */
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#define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10
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#define GLXIIC_GPIOL_IN_AUX1_SEL 0x34
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/* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */
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#define GLXIIC_GPIO_14_15_ENABLE 0x0000c000
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#define GLXIIC_GPIO_14_15_DISABLE 0xc0000000
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/* SMB register offsets. */
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#define GLXIIC_SMB_SDA 0x00
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#define GLXIIC_SMB_STS 0x01
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#define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7)
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#define GLXIIC_SMB_STS_SDAST_BIT (1 << 6)
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#define GLXIIC_SMB_STS_BER_BIT (1 << 5)
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#define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4)
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#define GLXIIC_SMB_STS_STASTR_BIT (1 << 3)
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#define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2)
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#define GLXIIC_SMB_STS_MASTER_BIT (1 << 1)
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#define GLXIIC_SMB_STS_XMIT_BIT (1 << 0)
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#define GLXIIC_SMB_CTRL_STS 0x02
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#define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5)
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#define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4)
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#define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3)
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#define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2)
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#define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1)
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#define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0)
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#define GLXIIC_SMB_CTRL1 0x03
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#define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7)
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#define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6)
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#define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5)
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#define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4)
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#define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2)
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#define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1)
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#define GLXIIC_SMB_CTRL1_START_BIT (1 << 0)
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#define GLXIIC_SMB_ADDR 0x04
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#define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7)
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#define GLXIIC_SMB_CTRL2 0x05
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#define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0)
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#define GLXIIC_SMB_CTRL3 0x06
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typedef enum {
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GLXIIC_STATE_IDLE,
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GLXIIC_STATE_SLAVE_TX,
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GLXIIC_STATE_SLAVE_RX,
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GLXIIC_STATE_MASTER_ADDR,
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GLXIIC_STATE_MASTER_TX,
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GLXIIC_STATE_MASTER_RX,
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GLXIIC_STATE_MASTER_STOP,
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GLXIIC_STATE_MAX,
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} glxiic_state_t;
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struct glxiic_softc {
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device_t dev; /* Myself. */
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device_t iicbus; /* IIC bus. */
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struct mtx mtx; /* Lock. */
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glxiic_state_t state; /* Driver state. */
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struct callout callout; /* Driver state timeout callout. */
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int timeout; /* Driver state timeout (ms). */
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int smb_rid; /* SMB controller resource ID. */
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struct resource *smb_res; /* SMB controller resource. */
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int gpio_rid; /* GPIO resource ID. */
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struct resource *gpio_res; /* GPIO resource. */
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int irq_rid; /* IRQ resource ID. */
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struct resource *irq_res; /* IRQ resource. */
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void *irq_handler; /* IRQ handler cookie. */
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int old_irq; /* IRQ mapped by board firmware. */
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struct iic_msg *msg; /* Current master mode message. */
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uint32_t nmsgs; /* Number of messages remaining. */
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uint8_t *data; /* Current master mode data byte. */
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uint16_t ndata; /* Number of data bytes remaining. */
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int error; /* Last master mode error. */
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uint8_t addr; /* Own address. */
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uint16_t sclfrq; /* Bus frequency. */
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};
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#ifdef GLXIIC_DEBUG
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#define GLXIIC_DEBUG_LOG(fmt, args...) \
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log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args)
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#else
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#define GLXIIC_DEBUG_LOG(fmt, args...)
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#endif
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#define GLXIIC_SCLFRQ(n) ((n << 1))
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#define GLXIIC_SMBADDR(n) ((n >> 1))
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#define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16))
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#define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf)
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#define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx)
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#define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx)
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#define GLXIIC_LOCK_INIT(_sc) \
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mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF)
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#define GLXIIC_SLEEP(_sc) \
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mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0)
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#define GLXIIC_WAKEUP(_sc) wakeup(_sc);
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#define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
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#define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
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typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc,
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uint8_t status);
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static glxiic_state_callback_t glxiic_state_idle_callback;
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static glxiic_state_callback_t glxiic_state_slave_tx_callback;
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static glxiic_state_callback_t glxiic_state_slave_rx_callback;
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static glxiic_state_callback_t glxiic_state_master_addr_callback;
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static glxiic_state_callback_t glxiic_state_master_tx_callback;
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static glxiic_state_callback_t glxiic_state_master_rx_callback;
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static glxiic_state_callback_t glxiic_state_master_stop_callback;
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struct glxiic_state_table_entry {
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glxiic_state_callback_t *callback;
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boolean_t master;
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};
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typedef struct glxiic_state_table_entry glxiic_state_table_entry_t;
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static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = {
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[GLXIIC_STATE_IDLE] = {
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.callback = &glxiic_state_idle_callback,
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.master = FALSE,
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},
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[GLXIIC_STATE_SLAVE_TX] = {
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.callback = &glxiic_state_slave_tx_callback,
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.master = FALSE,
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},
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[GLXIIC_STATE_SLAVE_RX] = {
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.callback = &glxiic_state_slave_rx_callback,
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.master = FALSE,
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},
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[GLXIIC_STATE_MASTER_ADDR] = {
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.callback = &glxiic_state_master_addr_callback,
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.master = TRUE,
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},
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[GLXIIC_STATE_MASTER_TX] = {
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.callback = &glxiic_state_master_tx_callback,
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.master = TRUE,
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},
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[GLXIIC_STATE_MASTER_RX] = {
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.callback = &glxiic_state_master_rx_callback,
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.master = TRUE,
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},
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[GLXIIC_STATE_MASTER_STOP] = {
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.callback = &glxiic_state_master_stop_callback,
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.master = TRUE,
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},
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};
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static void glxiic_identify(driver_t *driver, device_t parent);
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static int glxiic_probe(device_t dev);
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static int glxiic_attach(device_t dev);
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static int glxiic_detach(device_t dev);
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static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc);
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static void glxiic_stop_locked(struct glxiic_softc *sc);
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static void glxiic_timeout(void *arg);
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static void glxiic_start_timeout_locked(struct glxiic_softc *sc);
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static void glxiic_set_state_locked(struct glxiic_softc *sc,
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glxiic_state_t state);
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static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc,
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uint8_t status);
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static void glxiic_intr(void *arg);
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static int glxiic_reset(device_t dev, u_char speed, u_char addr,
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u_char *oldaddr);
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static int glxiic_transfer(device_t dev, struct iic_msg *msgs,
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uint32_t nmsgs);
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static void glxiic_smb_map_interrupt(int irq);
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static void glxiic_gpio_enable(struct glxiic_softc *sc);
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static void glxiic_gpio_disable(struct glxiic_softc *sc);
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static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed,
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uint8_t addr);
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static void glxiic_smb_disable(struct glxiic_softc *sc);
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static device_method_t glxiic_methods[] = {
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DEVMETHOD(device_identify, glxiic_identify),
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DEVMETHOD(device_probe, glxiic_probe),
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DEVMETHOD(device_attach, glxiic_attach),
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DEVMETHOD(device_detach, glxiic_detach),
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DEVMETHOD(iicbus_reset, glxiic_reset),
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DEVMETHOD(iicbus_transfer, glxiic_transfer),
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DEVMETHOD(iicbus_callback, iicbus_null_callback),
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{ 0, 0 }
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};
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static driver_t glxiic_driver = {
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"glxiic",
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glxiic_methods,
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sizeof(struct glxiic_softc),
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};
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DRIVER_MODULE(glxiic, isab, glxiic_driver, 0, 0);
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DRIVER_MODULE(iicbus, glxiic, iicbus_driver, 0, 0);
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MODULE_DEPEND(glxiic, iicbus, 1, 1, 1);
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static void
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glxiic_identify(driver_t *driver, device_t parent)
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{
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/* Prevent child from being added more than once. */
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if (device_find_child(parent, driver->name, -1) != NULL)
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return;
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if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) {
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if (device_add_child(parent, driver->name, -1) == NULL)
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device_printf(parent, "Could not add glxiic child\n");
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}
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}
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static int
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glxiic_probe(device_t dev)
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{
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if (resource_disabled("glxiic", device_get_unit(dev)))
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return (ENXIO);
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device_set_desc(dev, "AMD Geode CS5536 SMBus controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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glxiic_attach(device_t dev)
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{
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struct glxiic_softc *sc;
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struct sysctl_ctx_list *ctx;
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struct sysctl_oid *tree;
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int error, irq, unit;
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uint32_t irq_map;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->state = GLXIIC_STATE_IDLE;
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error = 0;
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GLXIIC_LOCK_INIT(sc);
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callout_init_mtx(&sc->callout, &sc->mtx, 0);
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sc->smb_rid = PCIR_BAR(0);
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sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid,
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RF_ACTIVE);
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if (sc->smb_res == NULL) {
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device_printf(dev, "Could not allocate SMBus I/O port\n");
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error = ENXIO;
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goto out;
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}
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sc->gpio_rid = PCIR_BAR(1);
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sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
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&sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE);
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if (sc->gpio_res == NULL) {
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device_printf(dev, "Could not allocate GPIO I/O port\n");
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error = ENXIO;
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goto out;
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}
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/* Ensure the controller is not enabled by firmware. */
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glxiic_smb_disable(sc);
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/* Read the existing IRQ map. */
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irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
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sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
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unit = device_get_unit(dev);
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if (resource_int_value("glxiic", unit, "irq", &irq) == 0) {
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if (irq < 1 || irq > 15) {
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device_printf(dev, "Bad value %d for glxiic.%d.irq\n",
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irq, unit);
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error = ENXIO;
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goto out;
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}
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if (bootverbose)
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device_printf(dev, "Using irq %d set by hint\n", irq);
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} else if (sc->old_irq != 0) {
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if (bootverbose)
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device_printf(dev, "Using irq %d set by firmware\n",
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irq);
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irq = sc->old_irq;
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} else {
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device_printf(dev, "No irq mapped by firmware");
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printf(" and no glxiic.%d.irq hint provided\n", unit);
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error = ENXIO;
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goto out;
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}
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/* Map the SMBus interrupt to the requested legacy IRQ. */
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glxiic_smb_map_interrupt(irq);
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sc->irq_rid = 0;
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sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
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irq, irq, 1, RF_SHAREABLE | RF_ACTIVE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "Could not allocate IRQ %d\n", irq);
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error = ENXIO;
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goto out;
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}
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error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, glxiic_intr, sc, &(sc->irq_handler));
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if (error != 0) {
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device_printf(dev, "Could not setup IRQ handler\n");
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error = ENXIO;
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goto out;
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}
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if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
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device_printf(dev, "Could not allocate iicbus instance\n");
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error = ENXIO;
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goto out;
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}
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ctx = device_get_sysctl_ctx(dev);
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tree = device_get_sysctl_tree(dev);
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sc->timeout = GLXIIC_DEFAULT_TIMEOUT;
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SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"timeout", CTLFLAG_RWTUN, &sc->timeout, 0,
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"activity timeout in ms");
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glxiic_gpio_enable(sc);
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glxiic_smb_enable(sc, IIC_FASTEST, 0);
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/* Probe and attach the iicbus when interrupts are available. */
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error = bus_delayed_attach_children(dev);
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out:
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if (error != 0) {
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callout_drain(&sc->callout);
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if (sc->iicbus != NULL)
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device_delete_child(dev, sc->iicbus);
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if (sc->smb_res != NULL) {
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glxiic_smb_disable(sc);
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bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
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sc->smb_res);
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}
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if (sc->gpio_res != NULL) {
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glxiic_gpio_disable(sc);
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bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
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sc->gpio_res);
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}
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if (sc->irq_handler != NULL)
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bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
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if (sc->irq_res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
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sc->irq_res);
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/* Restore the old SMBus interrupt mapping. */
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glxiic_smb_map_interrupt(sc->old_irq);
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GLXIIC_LOCK_DESTROY(sc);
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}
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return (error);
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}
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static int
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glxiic_detach(device_t dev)
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{
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struct glxiic_softc *sc;
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int error;
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|
|
sc = device_get_softc(dev);
|
|
|
|
error = bus_generic_detach(dev);
|
|
if (error != 0)
|
|
goto out;
|
|
if (sc->iicbus != NULL)
|
|
error = device_delete_child(dev, sc->iicbus);
|
|
|
|
out:
|
|
callout_drain(&sc->callout);
|
|
|
|
if (sc->smb_res != NULL) {
|
|
glxiic_smb_disable(sc);
|
|
bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
|
|
sc->smb_res);
|
|
}
|
|
if (sc->gpio_res != NULL) {
|
|
glxiic_gpio_disable(sc);
|
|
bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
|
|
sc->gpio_res);
|
|
}
|
|
if (sc->irq_handler != NULL)
|
|
bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
|
|
if (sc->irq_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
|
|
sc->irq_res);
|
|
|
|
/* Restore the old SMBus interrupt mapping. */
|
|
glxiic_smb_map_interrupt(sc->old_irq);
|
|
|
|
GLXIIC_LOCK_DESTROY(sc);
|
|
|
|
return (error);
|
|
}
|
|
|
|
static uint8_t
|
|
glxiic_read_status_locked(struct glxiic_softc *sc)
|
|
{
|
|
uint8_t status;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS);
|
|
|
|
/* Clear all status flags except SDAST and STASTR after reading. */
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT |
|
|
GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT |
|
|
GLXIIC_SMB_STS_NMATCH_BIT));
|
|
|
|
return (status);
|
|
}
|
|
|
|
static void
|
|
glxiic_stop_locked(struct glxiic_softc *sc)
|
|
{
|
|
uint8_t status, ctrl1;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
status = glxiic_read_status_locked(sc);
|
|
|
|
ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
|
|
ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT);
|
|
|
|
/*
|
|
* Perform a dummy read of SDA in master receive mode to clear
|
|
* SDAST if set.
|
|
*/
|
|
if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 &&
|
|
(status & GLXIIC_SMB_STS_SDAST_BIT) != 0)
|
|
bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
|
|
|
|
/* Check stall after start bit and clear if needed */
|
|
if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
|
|
GLXIIC_SMB_STS_STASTR_BIT);
|
|
}
|
|
}
|
|
|
|
static void
|
|
glxiic_timeout(void *arg)
|
|
{
|
|
struct glxiic_softc *sc;
|
|
uint8_t error;
|
|
|
|
sc = (struct glxiic_softc *)arg;
|
|
|
|
GLXIIC_DEBUG_LOG("timeout in state %d", sc->state);
|
|
|
|
if (glxiic_state_table[sc->state].master) {
|
|
sc->error = IIC_ETIMEOUT;
|
|
GLXIIC_WAKEUP(sc);
|
|
} else {
|
|
error = IIC_ETIMEOUT;
|
|
iicbus_intr(sc->iicbus, INTR_ERROR, &error);
|
|
}
|
|
|
|
glxiic_smb_disable(sc);
|
|
glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr);
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
|
|
}
|
|
|
|
static void
|
|
glxiic_start_timeout_locked(struct glxiic_softc *sc)
|
|
{
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0,
|
|
glxiic_timeout, sc, 0);
|
|
}
|
|
|
|
static void
|
|
glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state)
|
|
{
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if (state == GLXIIC_STATE_IDLE)
|
|
callout_stop(&sc->callout);
|
|
else if (sc->timeout > 0)
|
|
glxiic_start_timeout_locked(sc);
|
|
|
|
sc->state = state;
|
|
}
|
|
|
|
static int
|
|
glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
uint8_t ctrl_sts, addr;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS);
|
|
|
|
if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) {
|
|
if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) {
|
|
addr = sc->addr | LSB;
|
|
glxiic_set_state_locked(sc,
|
|
GLXIIC_STATE_SLAVE_TX);
|
|
} else {
|
|
addr = sc->addr & ~LSB;
|
|
glxiic_set_state_locked(sc,
|
|
GLXIIC_STATE_SLAVE_RX);
|
|
}
|
|
iicbus_intr(sc->iicbus, INTR_START, &addr);
|
|
} else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) {
|
|
addr = 0;
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX);
|
|
iicbus_intr(sc->iicbus, INTR_GENERAL, &addr);
|
|
} else {
|
|
GLXIIC_DEBUG_LOG("unknown slave match");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("bus error in idle");
|
|
return (IIC_EBUSERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
|
|
return (glxiic_handle_slave_match_locked(sc, status));
|
|
}
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
uint8_t data;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("bus error in slave tx");
|
|
return (IIC_EBUSERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
|
|
iicbus_intr(sc->iicbus, INTR_STOP, NULL);
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
|
|
iicbus_intr(sc->iicbus, INTR_NOACK, NULL);
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
|
|
/* Handle repeated start in slave mode. */
|
|
return (glxiic_handle_slave_match_locked(sc, status));
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("not awaiting data in slave tx");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data);
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data);
|
|
|
|
glxiic_start_timeout_locked(sc);
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
uint8_t data;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("bus error in slave rx");
|
|
return (IIC_EBUSERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
|
|
iicbus_intr(sc->iicbus, INTR_STOP, NULL);
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
|
|
/* Handle repeated start in slave mode. */
|
|
return (glxiic_handle_slave_match_locked(sc, status));
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("no pending data in slave rx");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
|
|
iicbus_intr(sc->iicbus, INTR_RECEIVE, &data);
|
|
|
|
glxiic_start_timeout_locked(sc);
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
uint8_t slave;
|
|
uint8_t ctrl1;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("bus error after master start");
|
|
return (IIC_EBUSERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("not bus master after master start");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("not awaiting address in master addr");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
if ((sc->msg->flags & IIC_M_RD) != 0) {
|
|
slave = sc->msg->slave | LSB;
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX);
|
|
} else {
|
|
slave = sc->msg->slave & ~LSB;
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX);
|
|
}
|
|
|
|
sc->data = sc->msg->buf;
|
|
sc->ndata = sc->msg->len;
|
|
|
|
/* Handle address-only transfer. */
|
|
if (sc->ndata == 0)
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
|
|
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave);
|
|
|
|
if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) {
|
|
/* Last byte from slave, set NACK. */
|
|
ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
|
|
ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
|
|
}
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("bus error in master tx");
|
|
return (IIC_EBUSERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("not bus master in master tx");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("slave nack in master tx");
|
|
return (IIC_ENOACK);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
|
|
GLXIIC_SMB_STS_STASTR_BIT);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("not awaiting data in master tx");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++);
|
|
if (--sc->ndata == 0)
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
|
|
else
|
|
glxiic_start_timeout_locked(sc);
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
uint8_t ctrl1;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("bus error in master rx");
|
|
return (IIC_EBUSERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("not bus master in master rx");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("slave nack in rx");
|
|
return (IIC_ENOACK);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
|
|
/* Bus is stalled, clear and wait for data. */
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
|
|
GLXIIC_SMB_STS_STASTR_BIT);
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("no pending data in master rx");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
*sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
|
|
if (--sc->ndata == 0) {
|
|
/* Proceed with stop on reading last byte. */
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
|
|
return (glxiic_state_table[sc->state].callback(sc, status));
|
|
}
|
|
|
|
if (sc->ndata == 1) {
|
|
/* Last byte from slave, set NACK. */
|
|
ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
|
|
ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
|
|
}
|
|
|
|
glxiic_start_timeout_locked(sc);
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status)
|
|
{
|
|
uint8_t ctrl1;
|
|
|
|
GLXIIC_ASSERT_LOCKED(sc);
|
|
|
|
if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("bus error in master stop");
|
|
return (IIC_EBUSERR);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
|
|
GLXIIC_DEBUG_LOG("not bus master in master stop");
|
|
return (IIC_ESTATUS);
|
|
}
|
|
|
|
if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
|
|
GLXIIC_DEBUG_LOG("slave nack in master stop");
|
|
return (IIC_ENOACK);
|
|
}
|
|
|
|
if (--sc->nmsgs > 0) {
|
|
/* Start transfer of next message. */
|
|
if ((sc->msg->flags & IIC_M_NOSTOP) == 0) {
|
|
glxiic_stop_locked(sc);
|
|
}
|
|
|
|
ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
|
|
ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
|
|
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
|
|
sc->msg++;
|
|
} else {
|
|
/* Last message. */
|
|
glxiic_stop_locked(sc);
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
|
|
sc->error = IIC_NOERR;
|
|
GLXIIC_WAKEUP(sc);
|
|
}
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static void
|
|
glxiic_intr(void *arg)
|
|
{
|
|
struct glxiic_softc *sc;
|
|
int error;
|
|
uint8_t status, data;
|
|
|
|
sc = (struct glxiic_softc *)arg;
|
|
|
|
GLXIIC_LOCK(sc);
|
|
|
|
status = glxiic_read_status_locked(sc);
|
|
|
|
/* Check if this interrupt originated from the SMBus. */
|
|
if ((status &
|
|
~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) {
|
|
|
|
error = glxiic_state_table[sc->state].callback(sc, status);
|
|
|
|
if (error != IIC_NOERR) {
|
|
if (glxiic_state_table[sc->state].master) {
|
|
glxiic_stop_locked(sc);
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
|
|
sc->error = error;
|
|
GLXIIC_WAKEUP(sc);
|
|
} else {
|
|
data = error & 0xff;
|
|
iicbus_intr(sc->iicbus, INTR_ERROR, &data);
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
|
|
}
|
|
}
|
|
}
|
|
|
|
GLXIIC_UNLOCK(sc);
|
|
}
|
|
|
|
static int
|
|
glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
|
|
{
|
|
struct glxiic_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
GLXIIC_LOCK(sc);
|
|
|
|
if (oldaddr != NULL)
|
|
*oldaddr = sc->addr;
|
|
sc->addr = addr;
|
|
|
|
/* A disable/enable cycle resets the controller. */
|
|
glxiic_smb_disable(sc);
|
|
glxiic_smb_enable(sc, speed, addr);
|
|
|
|
if (glxiic_state_table[sc->state].master) {
|
|
sc->error = IIC_ESTATUS;
|
|
GLXIIC_WAKEUP(sc);
|
|
}
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
|
|
|
|
GLXIIC_UNLOCK(sc);
|
|
|
|
return (IIC_NOERR);
|
|
}
|
|
|
|
static int
|
|
glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
|
|
{
|
|
struct glxiic_softc *sc;
|
|
int error;
|
|
uint8_t ctrl1;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
GLXIIC_LOCK(sc);
|
|
|
|
if (sc->state != GLXIIC_STATE_IDLE) {
|
|
error = IIC_EBUSBSY;
|
|
goto out;
|
|
}
|
|
|
|
sc->msg = msgs;
|
|
sc->nmsgs = nmsgs;
|
|
glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
|
|
|
|
/* Set start bit and let glxiic_intr() handle the transfer. */
|
|
ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
|
|
ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
|
|
|
|
GLXIIC_SLEEP(sc);
|
|
error = sc->error;
|
|
out:
|
|
GLXIIC_UNLOCK(sc);
|
|
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
glxiic_smb_map_interrupt(int irq)
|
|
{
|
|
uint32_t irq_map;
|
|
int old_irq;
|
|
|
|
/* Protect the read-modify-write operation. */
|
|
critical_enter();
|
|
|
|
irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
|
|
old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
|
|
|
|
if (irq != old_irq) {
|
|
irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq);
|
|
irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq);
|
|
wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map);
|
|
}
|
|
|
|
critical_exit();
|
|
}
|
|
|
|
static void
|
|
glxiic_gpio_enable(struct glxiic_softc *sc)
|
|
{
|
|
|
|
bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
|
|
GLXIIC_GPIO_14_15_ENABLE);
|
|
bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
|
|
GLXIIC_GPIO_14_15_ENABLE);
|
|
}
|
|
|
|
static void
|
|
glxiic_gpio_disable(struct glxiic_softc *sc)
|
|
{
|
|
|
|
bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
|
|
GLXIIC_GPIO_14_15_DISABLE);
|
|
bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
|
|
GLXIIC_GPIO_14_15_DISABLE);
|
|
}
|
|
|
|
static void
|
|
glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr)
|
|
{
|
|
uint8_t ctrl1;
|
|
|
|
ctrl1 = 0;
|
|
|
|
switch (speed) {
|
|
case IIC_SLOW:
|
|
sc->sclfrq = GLXIIC_SLOW;
|
|
break;
|
|
case IIC_FAST:
|
|
sc->sclfrq = GLXIIC_FAST;
|
|
break;
|
|
case IIC_FASTEST:
|
|
sc->sclfrq = GLXIIC_FASTEST;
|
|
break;
|
|
case IIC_UNKNOWN:
|
|
default:
|
|
/* Reuse last frequency. */
|
|
break;
|
|
}
|
|
|
|
/* Set bus speed and enable controller. */
|
|
bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
|
|
GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT);
|
|
|
|
if (addr != 0) {
|
|
/* Enable new match and global call match interrupts. */
|
|
ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT |
|
|
GLXIIC_SMB_CTRL1_GCMEN_BIT;
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR,
|
|
GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr));
|
|
} else {
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0);
|
|
}
|
|
|
|
/* Enable stall after start and interrupt. */
|
|
bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
|
|
ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT);
|
|
}
|
|
|
|
static void
|
|
glxiic_smb_disable(struct glxiic_softc *sc)
|
|
{
|
|
uint16_t sclfrq;
|
|
|
|
sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2);
|
|
bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
|
|
sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT);
|
|
}
|