578 lines
14 KiB
C
578 lines
14 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Amazon.com, Inc. or its affiliates.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <sys/interrupt.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/gpio/gpiobusvar.h>
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#include "pl061.h"
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#include "gpio_if.h"
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#include "pic_if.h"
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#define PL061_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define PL061_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define PL061_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define PL061_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define PL061_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
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#if 0
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#define dprintf(fmt, args...) do { \
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printf(fmt, ##args); \
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} while (0)
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#else
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#define dprintf(fmt, args...)
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#endif
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#define PL061_PIN_TO_ADDR(pin) (1 << (pin + 2))
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#define PL061_DATA 0x3FC
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#define PL061_DIR 0x400
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#define PL061_INTSENSE 0x404
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#define PL061_INTBOTHEDGES 0x408
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#define PL061_INTEVENT 0x40C
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#define PL061_INTMASK 0x410
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#define PL061_RAWSTATUS 0x414
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#define PL061_STATUS 0x418
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#define PL061_INTCLR 0x41C
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#define PL061_MODECTRL 0x420
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#define PL061_ALLOWED_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_INTR_EDGE_BOTH | \
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GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \
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GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW )
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#define PIC_INTR_ISRC(sc, irq) (&(sc->sc_isrcs[irq].isrc))
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static device_t
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pl061_get_bus(device_t dev)
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{
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struct pl061_softc *sc;
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sc = device_get_softc(dev);
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return (sc->sc_busdev);
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}
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static int
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pl061_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = PL061_NUM_GPIO - 1;
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return (0);
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}
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static int
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pl061_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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if (pin >= PL061_NUM_GPIO)
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return (EINVAL);
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snprintf(name, GPIOMAXNAME, "p%u", pin);
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name[GPIOMAXNAME - 1] = '\0';
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return (0);
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}
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static int
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pl061_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct pl061_softc *sc;
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uint8_t mask = 1 << pin;
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sc = device_get_softc(dev);
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if (pin >= PL061_NUM_GPIO)
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return (EINVAL);
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PL061_LOCK(sc);
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*flags = 0;
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if (mask & bus_read_1(sc->sc_mem_res, PL061_DIR))
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*flags |= GPIO_PIN_OUTPUT;
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else
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*flags |= GPIO_PIN_INPUT;
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PL061_UNLOCK(sc);
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return (0);
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}
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static int
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pl061_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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if (pin >= PL061_NUM_GPIO)
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return (EINVAL);
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*caps = PL061_ALLOWED_CAPS;
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return (0);
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}
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static void
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mask_and_set(struct pl061_softc *sc, long a, uint8_t m, uint8_t b)
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{
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uint8_t tmp;
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tmp = bus_read_1(sc->sc_mem_res, a);
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tmp &= ~m;
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tmp |= b;
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bus_write_1(sc->sc_mem_res, a, tmp);
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dprintf("%s: writing %#x to register %#lx\n", __func__, tmp, a);
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}
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static int
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pl061_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct pl061_softc *sc;
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uint8_t mask = 1 << pin;
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const uint32_t in_out = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
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sc = device_get_softc(dev);
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if (pin >= PL061_NUM_GPIO)
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return (EINVAL);
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if (flags & ~PL061_ALLOWED_CAPS)
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return (EINVAL);
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/* can't be both input and output */
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if ((flags & in_out) == in_out)
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return (EINVAL);
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PL061_LOCK(sc);
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mask_and_set(sc, PL061_DIR, mask, flags & GPIO_PIN_OUTPUT ? mask : 0);
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PL061_UNLOCK(sc);
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return (0);
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}
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static int
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pl061_pin_get(device_t dev, uint32_t pin, uint32_t *value)
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{
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struct pl061_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= PL061_NUM_GPIO)
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return (EINVAL);
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PL061_LOCK(sc);
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if (bus_read_1(sc->sc_mem_res, PL061_PIN_TO_ADDR(pin)))
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*value = GPIO_PIN_HIGH;
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else
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*value = GPIO_PIN_LOW;
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PL061_UNLOCK(sc);
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return (0);
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}
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static int
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pl061_pin_set(device_t dev, uint32_t pin, uint32_t value)
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{
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struct pl061_softc *sc;
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uint8_t d = (value == GPIO_PIN_HIGH) ? 0xff : 0x00;
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sc = device_get_softc(dev);
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if (pin >= PL061_NUM_GPIO)
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return (EINVAL);
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PL061_LOCK(sc);
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bus_write_1(sc->sc_mem_res, PL061_PIN_TO_ADDR(pin), d);
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PL061_UNLOCK(sc);
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return (0);
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}
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static int
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pl061_pin_toggle(device_t dev, uint32_t pin)
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{
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struct pl061_softc *sc;
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uint8_t d;
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sc = device_get_softc(dev);
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if (pin >= PL061_NUM_GPIO)
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return (EINVAL);
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PL061_LOCK(sc);
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d = ~bus_read_1(sc->sc_mem_res, PL061_PIN_TO_ADDR(pin));
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bus_write_1(sc->sc_mem_res, PL061_PIN_TO_ADDR(pin), d);
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PL061_UNLOCK(sc);
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return (0);
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}
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static void
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pl061_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct pl061_softc *sc;
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uint8_t mask;
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sc = device_get_softc(dev);
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mask = 1 << ((struct pl061_pin_irqsrc *)isrc)->irq;
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dprintf("%s: calling disable interrupt %#x\n", __func__, mask);
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PL061_LOCK(sc);
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mask_and_set(sc, PL061_INTMASK, mask, 0);
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PL061_UNLOCK(sc);
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}
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static void
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pl061_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct pl061_softc *sc;
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uint8_t mask;
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sc = device_get_softc(dev);
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mask = 1 << ((struct pl061_pin_irqsrc *)isrc)->irq;
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dprintf("%s: calling enable interrupt %#x\n", __func__, mask);
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PL061_LOCK(sc);
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mask_and_set(sc, PL061_INTMASK, mask, mask);
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PL061_UNLOCK(sc);
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}
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static int
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pl061_pic_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct pl061_softc *sc;
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struct intr_map_data_gpio *gdata;
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uint32_t irq;
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sc = device_get_softc(dev);
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if (data->type != INTR_MAP_DATA_GPIO)
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return (ENOTSUP);
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gdata = (struct intr_map_data_gpio *)data;
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irq = gdata->gpio_pin_num;
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if (irq >= PL061_NUM_GPIO) {
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device_printf(dev, "invalid interrupt number %u\n", irq);
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return (EINVAL);
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}
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dprintf("%s: calling map interrupt %u\n", __func__, irq);
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*isrcp = PIC_INTR_ISRC(sc, irq);
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return (0);
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}
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static int
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pl061_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct pl061_softc *sc;
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struct intr_map_data_gpio *gdata;
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struct pl061_pin_irqsrc *irqsrc;
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uint32_t mode;
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uint8_t mask;
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if (data == NULL)
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return (ENOTSUP);
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sc = device_get_softc(dev);
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gdata = (struct intr_map_data_gpio *)data;
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irqsrc = (struct pl061_pin_irqsrc *)isrc;
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mode = gdata->gpio_intr_mode;
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mask = 1 << gdata->gpio_pin_num;
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dprintf("%s: calling setup interrupt %u mode %#x\n", __func__,
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irqsrc->irq, mode);
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if (irqsrc->irq != gdata->gpio_pin_num) {
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dprintf("%s: interrupts don't match\n", __func__);
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return (EINVAL);
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}
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if (isrc->isrc_handlers != 0) {
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dprintf("%s: handler already attached\n", __func__);
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return (irqsrc->mode == mode ? 0 : EINVAL);
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}
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irqsrc->mode = mode;
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PL061_LOCK(sc);
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if (mode & GPIO_INTR_EDGE_BOTH) {
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mask_and_set(sc, PL061_INTBOTHEDGES, mask, mask);
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mask_and_set(sc, PL061_INTSENSE, mask, 0);
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} else if (mode & GPIO_INTR_EDGE_RISING) {
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mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
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mask_and_set(sc, PL061_INTSENSE, mask, 0);
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mask_and_set(sc, PL061_INTEVENT, mask, mask);
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} else if (mode & GPIO_INTR_EDGE_FALLING) {
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mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
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mask_and_set(sc, PL061_INTSENSE, mask, 0);
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mask_and_set(sc, PL061_INTEVENT, mask, 0);
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} else if (mode & GPIO_INTR_LEVEL_HIGH) {
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mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
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mask_and_set(sc, PL061_INTSENSE, mask, mask);
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mask_and_set(sc, PL061_INTEVENT, mask, mask);
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} else if (mode & GPIO_INTR_LEVEL_LOW) {
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mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
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mask_and_set(sc, PL061_INTSENSE, mask, mask);
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mask_and_set(sc, PL061_INTEVENT, mask, 0);
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}
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PL061_UNLOCK(sc);
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return (0);
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}
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static int
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pl061_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct pl061_softc *sc;
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struct pl061_pin_irqsrc *irqsrc;
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uint8_t mask;
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irqsrc = (struct pl061_pin_irqsrc *)isrc;
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mask = 1 << irqsrc->irq;
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dprintf("%s: calling teardown interrupt %#x\n", __func__, mask);
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sc = device_get_softc(dev);
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if (isrc->isrc_handlers == 0) {
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irqsrc->mode = GPIO_INTR_CONFORM;
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PL061_LOCK(sc);
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mask_and_set(sc, PL061_INTMASK, mask, 0);
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PL061_UNLOCK(sc);
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}
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return (0);
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}
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static void
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pl061_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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struct pl061_softc *sc;
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uint8_t mask;
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sc = device_get_softc(dev);
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mask = 1 << ((struct pl061_pin_irqsrc *)isrc)->irq;
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dprintf("%s: calling post filter %#x\n", __func__, mask);
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bus_write_1(sc->sc_mem_res, PL061_INTCLR, mask);
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}
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static void
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pl061_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct pl061_softc *sc;
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uint8_t mask;
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sc = device_get_softc(dev);
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mask = 1 << ((struct pl061_pin_irqsrc *)isrc)->irq;
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dprintf("%s: calling post ithread %#x\n", __func__, mask);
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bus_write_1(sc->sc_mem_res, PL061_INTCLR, mask);
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pl061_pic_enable_intr(dev, isrc);
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}
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static void
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pl061_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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pl061_pic_disable_intr(dev, isrc);
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}
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static int
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pl061_intr(void *arg)
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{
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struct pl061_softc *sc;
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struct trapframe *tf;
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uint8_t status;
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int pin;
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sc = (struct pl061_softc *)arg;
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tf = curthread->td_intr_frame;
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status = bus_read_1(sc->sc_mem_res, PL061_STATUS);
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while (status != 0) {
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pin = ffs(status) - 1;
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status &= ~(1 << pin);
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if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, pin), tf) != 0)
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device_printf(sc->sc_dev, "spurious interrupt %d\n",
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pin);
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dprintf("got IRQ on %d\n", pin);
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}
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return (FILTER_HANDLED);
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}
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int
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pl061_attach(device_t dev)
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{
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struct pl061_softc *sc;
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int ret;
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int irq;
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const char *name;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_mem_rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->sc_mem_rid, RF_ACTIVE);
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if (sc->sc_mem_res == NULL) {
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device_printf(dev, "can't allocate memory resource\n");
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return (ENXIO);
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}
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sc->sc_irq_rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&sc->sc_irq_rid, RF_ACTIVE);
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if (sc->sc_irq_res == NULL) {
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device_printf(dev, "can't allocate IRQ resource\n");
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goto free_mem;
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}
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ret = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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pl061_intr, NULL, sc, &sc->sc_irq_hdlr);
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if (ret) {
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device_printf(dev, "can't setup IRQ\n");
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goto free_pic;
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}
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name = device_get_nameunit(dev);
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for (irq = 0; irq < PL061_NUM_GPIO; irq++) {
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if (bootverbose) {
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device_printf(dev,
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"trying to register pin %d name %s\n", irq, name);
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}
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sc->sc_isrcs[irq].irq = irq;
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sc->sc_isrcs[irq].mode = GPIO_INTR_CONFORM;
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ret = intr_isrc_register(PIC_INTR_ISRC(sc, irq), dev, 0,
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"%s", name);
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if (ret) {
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device_printf(dev, "can't register isrc %d\n", ret);
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goto free_isrc;
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}
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}
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sc->sc_busdev = gpiobus_attach_bus(dev);
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if (sc->sc_busdev == NULL) {
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device_printf(dev, "couldn't attach gpio bus\n");
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goto free_isrc;
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}
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mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "pl061", MTX_SPIN);
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return (0);
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free_isrc:
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/*
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* XXX isrc_release_counters() not implemented
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* for (irq = 0; irq < PL061_NUM_GPIO; irq++)
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* intr_isrc_deregister(PIC_INTR_ISRC(sc, irq));
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*/
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bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
|
|
sc->sc_irq_res);
|
|
free_pic:
|
|
/*
|
|
* XXX intr_pic_deregister: not implemented
|
|
* intr_pic_deregister(dev, 0);
|
|
*/
|
|
|
|
free_mem:
|
|
bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
|
|
sc->sc_mem_res);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
int
|
|
pl061_detach(device_t dev)
|
|
{
|
|
struct pl061_softc *sc;
|
|
sc = device_get_softc(dev);
|
|
|
|
if (sc->sc_busdev)
|
|
gpiobus_detach_bus(dev);
|
|
|
|
if (sc->sc_irq_hdlr != NULL)
|
|
bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_hdlr);
|
|
|
|
if (sc->sc_irq_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
|
|
sc->sc_irq_res);
|
|
|
|
if (sc->sc_mem_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
|
|
sc->sc_mem_res);
|
|
PL061_LOCK_DESTROY(sc);
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t pl061_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_attach, pl061_attach),
|
|
DEVMETHOD(device_detach, pl061_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, pl061_get_bus),
|
|
DEVMETHOD(gpio_pin_max, pl061_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, pl061_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, pl061_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, pl061_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, pl061_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, pl061_pin_get),
|
|
DEVMETHOD(gpio_pin_set, pl061_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, pl061_pin_toggle),
|
|
|
|
/* Interrupt controller interface */
|
|
DEVMETHOD(pic_disable_intr, pl061_pic_disable_intr),
|
|
DEVMETHOD(pic_enable_intr, pl061_pic_enable_intr),
|
|
DEVMETHOD(pic_map_intr, pl061_pic_map_intr),
|
|
DEVMETHOD(pic_setup_intr, pl061_pic_setup_intr),
|
|
DEVMETHOD(pic_teardown_intr, pl061_pic_teardown_intr),
|
|
DEVMETHOD(pic_post_filter, pl061_pic_post_filter),
|
|
DEVMETHOD(pic_post_ithread, pl061_pic_post_ithread),
|
|
DEVMETHOD(pic_pre_ithread, pl061_pic_pre_ithread),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_0(gpio, pl061_driver, pl061_methods, sizeof(struct pl061_softc));
|