685dc743dc
Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
719 lines
19 KiB
C
719 lines
19 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <sys/cdefs.h>
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#include "igc_api.h"
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/**
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* igc_init_mac_params - Initialize MAC function pointers
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* @hw: pointer to the HW structure
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*
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* This function initializes the function pointers for the MAC
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* set of functions. Called by drivers or by igc_setup_init_funcs.
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**/
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s32 igc_init_mac_params(struct igc_hw *hw)
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{
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s32 ret_val = IGC_SUCCESS;
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if (hw->mac.ops.init_params) {
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ret_val = hw->mac.ops.init_params(hw);
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if (ret_val) {
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DEBUGOUT("MAC Initialization Error\n");
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goto out;
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}
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} else {
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DEBUGOUT("mac.init_mac_params was NULL\n");
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ret_val = -IGC_ERR_CONFIG;
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}
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out:
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return ret_val;
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}
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/**
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* igc_init_nvm_params - Initialize NVM function pointers
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* @hw: pointer to the HW structure
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*
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* This function initializes the function pointers for the NVM
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* set of functions. Called by drivers or by igc_setup_init_funcs.
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**/
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s32 igc_init_nvm_params(struct igc_hw *hw)
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{
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s32 ret_val = IGC_SUCCESS;
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if (hw->nvm.ops.init_params) {
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ret_val = hw->nvm.ops.init_params(hw);
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if (ret_val) {
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DEBUGOUT("NVM Initialization Error\n");
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goto out;
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}
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} else {
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DEBUGOUT("nvm.init_nvm_params was NULL\n");
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ret_val = -IGC_ERR_CONFIG;
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}
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out:
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return ret_val;
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}
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/**
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* igc_init_phy_params - Initialize PHY function pointers
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* @hw: pointer to the HW structure
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*
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* This function initializes the function pointers for the PHY
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* set of functions. Called by drivers or by igc_setup_init_funcs.
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**/
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s32 igc_init_phy_params(struct igc_hw *hw)
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{
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s32 ret_val = IGC_SUCCESS;
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if (hw->phy.ops.init_params) {
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ret_val = hw->phy.ops.init_params(hw);
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if (ret_val) {
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DEBUGOUT("PHY Initialization Error\n");
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goto out;
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}
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} else {
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DEBUGOUT("phy.init_phy_params was NULL\n");
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ret_val = -IGC_ERR_CONFIG;
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}
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out:
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return ret_val;
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}
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/**
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* igc_set_mac_type - Sets MAC type
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* @hw: pointer to the HW structure
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*
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* This function sets the mac type of the adapter based on the
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* device ID stored in the hw structure.
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* MUST BE FIRST FUNCTION CALLED (explicitly or through
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* igc_setup_init_funcs()).
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**/
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s32 igc_set_mac_type(struct igc_hw *hw)
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{
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struct igc_mac_info *mac = &hw->mac;
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s32 ret_val = IGC_SUCCESS;
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DEBUGFUNC("igc_set_mac_type");
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switch (hw->device_id) {
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case IGC_DEV_ID_I225_LM:
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case IGC_DEV_ID_I225_V:
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case IGC_DEV_ID_I225_K:
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case IGC_DEV_ID_I225_I:
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case IGC_DEV_ID_I220_V:
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case IGC_DEV_ID_I225_K2:
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case IGC_DEV_ID_I225_LMVP:
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case IGC_DEV_ID_I225_IT:
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case IGC_DEV_ID_I226_LM:
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case IGC_DEV_ID_I226_V:
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case IGC_DEV_ID_I226_IT:
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case IGC_DEV_ID_I221_V:
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case IGC_DEV_ID_I226_BLANK_NVM:
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case IGC_DEV_ID_I225_BLANK_NVM:
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mac->type = igc_i225;
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break;
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default:
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/* Should never have loaded on this device */
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ret_val = -IGC_ERR_MAC_INIT;
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break;
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}
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return ret_val;
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}
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/**
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* igc_setup_init_funcs - Initializes function pointers
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* @hw: pointer to the HW structure
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* @init_device: true will initialize the rest of the function pointers
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* getting the device ready for use. FALSE will only set
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* MAC type and the function pointers for the other init
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* functions. Passing FALSE will not generate any hardware
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* reads or writes.
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*
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* This function must be called by a driver in order to use the rest
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* of the 'shared' code files. Called by drivers only.
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**/
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s32 igc_setup_init_funcs(struct igc_hw *hw, bool init_device)
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{
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s32 ret_val;
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/* Can't do much good without knowing the MAC type. */
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ret_val = igc_set_mac_type(hw);
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if (ret_val) {
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DEBUGOUT("ERROR: MAC type could not be set properly.\n");
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goto out;
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}
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if (!hw->hw_addr) {
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DEBUGOUT("ERROR: Registers not mapped\n");
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ret_val = -IGC_ERR_CONFIG;
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goto out;
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}
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/*
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* Init function pointers to generic implementations. We do this first
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* allowing a driver module to override it afterward.
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*/
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igc_init_mac_ops_generic(hw);
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igc_init_phy_ops_generic(hw);
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igc_init_nvm_ops_generic(hw);
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/*
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* Set up the init function pointers. These are functions within the
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* adapter family file that sets up function pointers for the rest of
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* the functions in that family.
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*/
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switch (hw->mac.type) {
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case igc_i225:
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igc_init_function_pointers_i225(hw);
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break;
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default:
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DEBUGOUT("Hardware not supported\n");
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ret_val = -IGC_ERR_CONFIG;
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break;
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}
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/*
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* Initialize the rest of the function pointers. These require some
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* register reads/writes in some cases.
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*/
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if (!(ret_val) && init_device) {
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ret_val = igc_init_mac_params(hw);
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if (ret_val)
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goto out;
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ret_val = igc_init_nvm_params(hw);
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if (ret_val)
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goto out;
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ret_val = igc_init_phy_params(hw);
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if (ret_val)
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goto out;
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}
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out:
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return ret_val;
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}
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/**
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* igc_get_bus_info - Obtain bus information for adapter
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* @hw: pointer to the HW structure
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*
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* This will obtain information about the HW bus for which the
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* adapter is attached and stores it in the hw structure. This is a
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* function pointer entry point called by drivers.
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**/
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s32 igc_get_bus_info(struct igc_hw *hw)
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{
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if (hw->mac.ops.get_bus_info)
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return hw->mac.ops.get_bus_info(hw);
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return IGC_SUCCESS;
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}
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/**
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* igc_clear_vfta - Clear VLAN filter table
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* @hw: pointer to the HW structure
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*
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* This clears the VLAN filter table on the adapter. This is a function
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* pointer entry point called by drivers.
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**/
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void igc_clear_vfta(struct igc_hw *hw)
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{
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if (hw->mac.ops.clear_vfta)
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hw->mac.ops.clear_vfta(hw);
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}
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/**
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* igc_write_vfta - Write value to VLAN filter table
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* @hw: pointer to the HW structure
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* @offset: the 32-bit offset in which to write the value to.
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* @value: the 32-bit value to write at location offset.
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*
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* This writes a 32-bit value to a 32-bit offset in the VLAN filter
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* table. This is a function pointer entry point called by drivers.
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**/
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void igc_write_vfta(struct igc_hw *hw, u32 offset, u32 value)
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{
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if (hw->mac.ops.write_vfta)
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hw->mac.ops.write_vfta(hw, offset, value);
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}
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/**
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* igc_update_mc_addr_list - Update Multicast addresses
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* @hw: pointer to the HW structure
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* @mc_addr_list: array of multicast addresses to program
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* @mc_addr_count: number of multicast addresses to program
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*
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* Updates the Multicast Table Array.
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* The caller must have a packed mc_addr_list of multicast addresses.
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**/
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void igc_update_mc_addr_list(struct igc_hw *hw, u8 *mc_addr_list,
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u32 mc_addr_count)
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{
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if (hw->mac.ops.update_mc_addr_list)
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hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
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mc_addr_count);
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}
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/**
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* igc_force_mac_fc - Force MAC flow control
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* @hw: pointer to the HW structure
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*
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* Force the MAC's flow control settings. Currently no func pointer exists
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* and all implementations are handled in the generic version of this
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* function.
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**/
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s32 igc_force_mac_fc(struct igc_hw *hw)
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{
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return igc_force_mac_fc_generic(hw);
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}
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/**
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* igc_check_for_link - Check/Store link connection
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* @hw: pointer to the HW structure
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*
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* This checks the link condition of the adapter and stores the
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* results in the hw->mac structure. This is a function pointer entry
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* point called by drivers.
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**/
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s32 igc_check_for_link(struct igc_hw *hw)
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{
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if (hw->mac.ops.check_for_link)
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return hw->mac.ops.check_for_link(hw);
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return -IGC_ERR_CONFIG;
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}
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/**
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* igc_reset_hw - Reset hardware
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* @hw: pointer to the HW structure
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*
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* This resets the hardware into a known state. This is a function pointer
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* entry point called by drivers.
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**/
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s32 igc_reset_hw(struct igc_hw *hw)
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{
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if (hw->mac.ops.reset_hw)
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return hw->mac.ops.reset_hw(hw);
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return -IGC_ERR_CONFIG;
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}
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/**
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* igc_init_hw - Initialize hardware
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* @hw: pointer to the HW structure
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*
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* This inits the hardware readying it for operation. This is a function
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* pointer entry point called by drivers.
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**/
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s32 igc_init_hw(struct igc_hw *hw)
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{
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if (hw->mac.ops.init_hw)
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return hw->mac.ops.init_hw(hw);
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return -IGC_ERR_CONFIG;
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}
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/**
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* igc_setup_link - Configures link and flow control
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* @hw: pointer to the HW structure
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*
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* This configures link and flow control settings for the adapter. This
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* is a function pointer entry point called by drivers. While modules can
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* also call this, they probably call their own version of this function.
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**/
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s32 igc_setup_link(struct igc_hw *hw)
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{
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if (hw->mac.ops.setup_link)
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return hw->mac.ops.setup_link(hw);
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return -IGC_ERR_CONFIG;
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}
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/**
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* igc_get_speed_and_duplex - Returns current speed and duplex
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* @hw: pointer to the HW structure
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* @speed: pointer to a 16-bit value to store the speed
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* @duplex: pointer to a 16-bit value to store the duplex.
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*
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* This returns the speed and duplex of the adapter in the two 'out'
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* variables passed in. This is a function pointer entry point called
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* by drivers.
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**/
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s32 igc_get_speed_and_duplex(struct igc_hw *hw, u16 *speed, u16 *duplex)
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{
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if (hw->mac.ops.get_link_up_info)
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return hw->mac.ops.get_link_up_info(hw, speed, duplex);
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return -IGC_ERR_CONFIG;
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}
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/**
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* igc_disable_pcie_master - Disable PCI-Express master access
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* @hw: pointer to the HW structure
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*
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* Disables PCI-Express master access and verifies there are no pending
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* requests. Currently no func pointer exists and all implementations are
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* handled in the generic version of this function.
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**/
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s32 igc_disable_pcie_master(struct igc_hw *hw)
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{
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return igc_disable_pcie_master_generic(hw);
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}
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/**
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* igc_config_collision_dist - Configure collision distance
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* @hw: pointer to the HW structure
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*
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* Configures the collision distance to the default value and is used
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* during link setup.
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**/
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void igc_config_collision_dist(struct igc_hw *hw)
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{
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if (hw->mac.ops.config_collision_dist)
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hw->mac.ops.config_collision_dist(hw);
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}
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/**
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* igc_rar_set - Sets a receive address register
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* @hw: pointer to the HW structure
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* @addr: address to set the RAR to
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* @index: the RAR to set
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*
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* Sets a Receive Address Register (RAR) to the specified address.
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**/
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int igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
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{
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if (hw->mac.ops.rar_set)
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return hw->mac.ops.rar_set(hw, addr, index);
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return IGC_SUCCESS;
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}
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/**
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* igc_validate_mdi_setting - Ensures valid MDI/MDIX SW state
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* @hw: pointer to the HW structure
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*
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* Ensures that the MDI/MDIX SW state is valid.
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**/
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s32 igc_validate_mdi_setting(struct igc_hw *hw)
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{
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if (hw->mac.ops.validate_mdi_setting)
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return hw->mac.ops.validate_mdi_setting(hw);
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return IGC_SUCCESS;
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}
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/**
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* igc_hash_mc_addr - Determines address location in multicast table
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* @hw: pointer to the HW structure
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* @mc_addr: Multicast address to hash.
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*
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* This hashes an address to determine its location in the multicast
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* table. Currently no func pointer exists and all implementations
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* are handled in the generic version of this function.
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**/
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u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)
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{
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return igc_hash_mc_addr_generic(hw, mc_addr);
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}
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/**
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* igc_check_reset_block - Verifies PHY can be reset
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* @hw: pointer to the HW structure
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*
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* Checks if the PHY is in a state that can be reset or if manageability
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* has it tied up. This is a function pointer entry point called by drivers.
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**/
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s32 igc_check_reset_block(struct igc_hw *hw)
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{
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if (hw->phy.ops.check_reset_block)
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return hw->phy.ops.check_reset_block(hw);
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return IGC_SUCCESS;
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}
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/**
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* igc_read_phy_reg - Reads PHY register
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* @hw: pointer to the HW structure
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* @offset: the register to read
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* @data: the buffer to store the 16-bit read.
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*
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* Reads the PHY register and returns the value in data.
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* This is a function pointer entry point called by drivers.
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**/
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s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
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{
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if (hw->phy.ops.read_reg)
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return hw->phy.ops.read_reg(hw, offset, data);
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return IGC_SUCCESS;
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}
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/**
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* igc_write_phy_reg - Writes PHY register
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* @hw: pointer to the HW structure
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* @offset: the register to write
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* @data: the value to write.
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*
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* Writes the PHY register at offset with the value in data.
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* This is a function pointer entry point called by drivers.
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**/
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s32 igc_write_phy_reg(struct igc_hw *hw, u32 offset, u16 data)
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{
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if (hw->phy.ops.write_reg)
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return hw->phy.ops.write_reg(hw, offset, data);
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return IGC_SUCCESS;
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}
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/**
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* igc_release_phy - Generic release PHY
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* @hw: pointer to the HW structure
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*
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* Return if silicon family does not require a semaphore when accessing the
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* PHY.
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**/
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void igc_release_phy(struct igc_hw *hw)
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{
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if (hw->phy.ops.release)
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hw->phy.ops.release(hw);
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}
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|
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/**
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* igc_acquire_phy - Generic acquire PHY
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* @hw: pointer to the HW structure
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*
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* Return success if silicon family does not require a semaphore when
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* accessing the PHY.
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**/
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s32 igc_acquire_phy(struct igc_hw *hw)
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{
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if (hw->phy.ops.acquire)
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return hw->phy.ops.acquire(hw);
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return IGC_SUCCESS;
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}
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|
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/**
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* igc_get_phy_info - Retrieves PHY information from registers
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* @hw: pointer to the HW structure
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*
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* This function gets some information from various PHY registers and
|
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* populates hw->phy values with it. This is a function pointer entry
|
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* point called by drivers.
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**/
|
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s32 igc_get_phy_info(struct igc_hw *hw)
|
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{
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if (hw->phy.ops.get_info)
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return hw->phy.ops.get_info(hw);
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|
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return IGC_SUCCESS;
|
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}
|
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|
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/**
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* igc_phy_hw_reset - Hard PHY reset
|
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* @hw: pointer to the HW structure
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*
|
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* Performs a hard PHY reset. This is a function pointer entry point called
|
|
* by drivers.
|
|
**/
|
|
s32 igc_phy_hw_reset(struct igc_hw *hw)
|
|
{
|
|
if (hw->phy.ops.reset)
|
|
return hw->phy.ops.reset(hw);
|
|
|
|
return IGC_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* igc_set_d0_lplu_state - Sets low power link up state for D0
|
|
* @hw: pointer to the HW structure
|
|
* @active: boolean used to enable/disable lplu
|
|
*
|
|
* Success returns 0, Failure returns 1
|
|
*
|
|
* The low power link up (lplu) state is set to the power management level D0
|
|
* and SmartSpeed is disabled when active is true, else clear lplu for D0
|
|
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
|
|
* is used during Dx states where the power conservation is most important.
|
|
* During driver activity, SmartSpeed should be enabled so performance is
|
|
* maintained. This is a function pointer entry point called by drivers.
|
|
**/
|
|
s32 igc_set_d0_lplu_state(struct igc_hw *hw, bool active)
|
|
{
|
|
if (hw->phy.ops.set_d0_lplu_state)
|
|
return hw->phy.ops.set_d0_lplu_state(hw, active);
|
|
|
|
return IGC_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* igc_set_d3_lplu_state - Sets low power link up state for D3
|
|
* @hw: pointer to the HW structure
|
|
* @active: boolean used to enable/disable lplu
|
|
*
|
|
* Success returns 0, Failure returns 1
|
|
*
|
|
* The low power link up (lplu) state is set to the power management level D3
|
|
* and SmartSpeed is disabled when active is true, else clear lplu for D3
|
|
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
|
|
* is used during Dx states where the power conservation is most important.
|
|
* During driver activity, SmartSpeed should be enabled so performance is
|
|
* maintained. This is a function pointer entry point called by drivers.
|
|
**/
|
|
s32 igc_set_d3_lplu_state(struct igc_hw *hw, bool active)
|
|
{
|
|
if (hw->phy.ops.set_d3_lplu_state)
|
|
return hw->phy.ops.set_d3_lplu_state(hw, active);
|
|
|
|
return IGC_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* igc_read_mac_addr - Reads MAC address
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Reads the MAC address out of the adapter and stores it in the HW structure.
|
|
* Currently no func pointer exists and all implementations are handled in the
|
|
* generic version of this function.
|
|
**/
|
|
s32 igc_read_mac_addr(struct igc_hw *hw)
|
|
{
|
|
if (hw->mac.ops.read_mac_addr)
|
|
return hw->mac.ops.read_mac_addr(hw);
|
|
|
|
return igc_read_mac_addr_generic(hw);
|
|
}
|
|
|
|
/**
|
|
* igc_read_pba_string - Read device part number string
|
|
* @hw: pointer to the HW structure
|
|
* @pba_num: pointer to device part number
|
|
* @pba_num_size: size of part number buffer
|
|
*
|
|
* Reads the product board assembly (PBA) number from the EEPROM and stores
|
|
* the value in pba_num.
|
|
* Currently no func pointer exists and all implementations are handled in the
|
|
* generic version of this function.
|
|
**/
|
|
s32 igc_read_pba_string(struct igc_hw *hw, u8 *pba_num, u32 pba_num_size)
|
|
{
|
|
return igc_read_pba_string_generic(hw, pba_num, pba_num_size);
|
|
}
|
|
|
|
/**
|
|
* igc_validate_nvm_checksum - Verifies NVM (EEPROM) checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Validates the NVM checksum is correct. This is a function pointer entry
|
|
* point called by drivers.
|
|
**/
|
|
s32 igc_validate_nvm_checksum(struct igc_hw *hw)
|
|
{
|
|
if (hw->nvm.ops.validate)
|
|
return hw->nvm.ops.validate(hw);
|
|
|
|
return -IGC_ERR_CONFIG;
|
|
}
|
|
|
|
/**
|
|
* igc_update_nvm_checksum - Updates NVM (EEPROM) checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Updates the NVM checksum. Currently no func pointer exists and all
|
|
* implementations are handled in the generic version of this function.
|
|
**/
|
|
s32 igc_update_nvm_checksum(struct igc_hw *hw)
|
|
{
|
|
if (hw->nvm.ops.update)
|
|
return hw->nvm.ops.update(hw);
|
|
|
|
return -IGC_ERR_CONFIG;
|
|
}
|
|
|
|
/**
|
|
* igc_reload_nvm - Reloads EEPROM
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
|
|
* extended control register.
|
|
**/
|
|
void igc_reload_nvm(struct igc_hw *hw)
|
|
{
|
|
if (hw->nvm.ops.reload)
|
|
hw->nvm.ops.reload(hw);
|
|
}
|
|
|
|
/**
|
|
* igc_read_nvm - Reads NVM (EEPROM)
|
|
* @hw: pointer to the HW structure
|
|
* @offset: the word offset to read
|
|
* @words: number of 16-bit words to read
|
|
* @data: pointer to the properly sized buffer for the data.
|
|
*
|
|
* Reads 16-bit chunks of data from the NVM (EEPROM). This is a function
|
|
* pointer entry point called by drivers.
|
|
**/
|
|
s32 igc_read_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
|
|
{
|
|
if (hw->nvm.ops.read)
|
|
return hw->nvm.ops.read(hw, offset, words, data);
|
|
|
|
return -IGC_ERR_CONFIG;
|
|
}
|
|
|
|
/**
|
|
* igc_write_nvm - Writes to NVM (EEPROM)
|
|
* @hw: pointer to the HW structure
|
|
* @offset: the word offset to read
|
|
* @words: number of 16-bit words to write
|
|
* @data: pointer to the properly sized buffer for the data.
|
|
*
|
|
* Writes 16-bit chunks of data to the NVM (EEPROM). This is a function
|
|
* pointer entry point called by drivers.
|
|
**/
|
|
s32 igc_write_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
|
|
{
|
|
if (hw->nvm.ops.write)
|
|
return hw->nvm.ops.write(hw, offset, words, data);
|
|
|
|
return IGC_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* igc_power_up_phy - Restores link in case of PHY power down
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* The phy may be powered down to save power, to turn off link when the
|
|
* driver is unloaded, or wake on lan is not enabled (among others).
|
|
**/
|
|
void igc_power_up_phy(struct igc_hw *hw)
|
|
{
|
|
if (hw->phy.ops.power_up)
|
|
hw->phy.ops.power_up(hw);
|
|
|
|
igc_setup_link(hw);
|
|
}
|
|
|
|
/**
|
|
* igc_power_down_phy - Power down PHY
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* The phy may be powered down to save power, to turn off link when the
|
|
* driver is unloaded, or wake on lan is not enabled (among others).
|
|
**/
|
|
void igc_power_down_phy(struct igc_hw *hw)
|
|
{
|
|
if (hw->phy.ops.power_down)
|
|
hw->phy.ops.power_down(hw);
|
|
}
|
|
|