187 lines
4.8 KiB
C
187 lines
4.8 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <sys/cdefs.h>
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#include "igc_hw.h"
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#include "igc_i225.h"
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#include "igc_mac.h"
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#include "igc_base.h"
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/**
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* igc_acquire_phy_base - Acquire rights to access PHY
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* @hw: pointer to the HW structure
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*
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* Acquire access rights to the correct PHY.
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**/
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s32 igc_acquire_phy_base(struct igc_hw *hw)
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{
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u16 mask = IGC_SWFW_PHY0_SM;
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DEBUGFUNC("igc_acquire_phy_base");
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if (hw->bus.func == IGC_FUNC_1)
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mask = IGC_SWFW_PHY1_SM;
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return hw->mac.ops.acquire_swfw_sync(hw, mask);
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}
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/**
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* igc_release_phy_base - Release rights to access PHY
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* @hw: pointer to the HW structure
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*
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* A wrapper to release access rights to the correct PHY.
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**/
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void igc_release_phy_base(struct igc_hw *hw)
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{
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u16 mask = IGC_SWFW_PHY0_SM;
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DEBUGFUNC("igc_release_phy_base");
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if (hw->bus.func == IGC_FUNC_1)
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mask = IGC_SWFW_PHY1_SM;
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hw->mac.ops.release_swfw_sync(hw, mask);
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}
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/**
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* igc_init_hw_base - Initialize hardware
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* @hw: pointer to the HW structure
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*
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* This inits the hardware readying it for operation.
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**/
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s32 igc_init_hw_base(struct igc_hw *hw)
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{
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struct igc_mac_info *mac = &hw->mac;
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s32 ret_val;
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u16 i, rar_count = mac->rar_entry_count;
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DEBUGFUNC("igc_init_hw_base");
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/* Setup the receive address */
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igc_init_rx_addrs_generic(hw, rar_count);
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/* Zero out the Multicast HASH table */
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DEBUGOUT("Zeroing the MTA\n");
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for (i = 0; i < mac->mta_reg_count; i++)
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IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0);
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/* Zero out the Unicast HASH table */
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DEBUGOUT("Zeroing the UTA\n");
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for (i = 0; i < mac->uta_reg_count; i++)
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IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0);
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/* Setup link and flow control */
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ret_val = mac->ops.setup_link(hw);
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/*
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* Clear all of the statistics registers (clear on read). It is
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* important that we do this after we have tried to establish link
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* because the symbol error count will increment wildly if there
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* is no link.
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*/
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igc_clear_hw_cntrs_base_generic(hw);
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return ret_val;
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}
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/**
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* igc_power_down_phy_copper_base - Remove link during PHY power down
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* @hw: pointer to the HW structure
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*
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* In the case of a PHY power down to save power, or to turn off link during a
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* driver unload, or wake on lan is not enabled, remove the link.
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**/
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void igc_power_down_phy_copper_base(struct igc_hw *hw)
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{
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struct igc_phy_info *phy = &hw->phy;
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if (!(phy->ops.check_reset_block))
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return;
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/* If the management interface is not enabled, then power down */
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if (phy->ops.check_reset_block(hw))
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igc_power_down_phy_copper(hw);
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return;
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}
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/**
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* igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable
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* @hw: pointer to the HW structure
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*
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* After Rx enable, if manageability is enabled then there is likely some
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* bad data at the start of the FIFO and possibly in the DMA FIFO. This
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* function clears the FIFOs and flushes any packets that came in as Rx was
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* being enabled.
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**/
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void igc_rx_fifo_flush_base(struct igc_hw *hw)
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{
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u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
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int i, ms_wait;
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DEBUGFUNC("igc_rx_fifo_flush_base");
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/* disable IPv6 options as per hardware errata */
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rfctl = IGC_READ_REG(hw, IGC_RFCTL);
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rfctl |= IGC_RFCTL_IPV6_EX_DIS;
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IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
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if (!(IGC_READ_REG(hw, IGC_MANC) & IGC_MANC_RCV_TCO_EN))
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return;
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/* Disable all Rx queues */
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for (i = 0; i < 4; i++) {
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rxdctl[i] = IGC_READ_REG(hw, IGC_RXDCTL(i));
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IGC_WRITE_REG(hw, IGC_RXDCTL(i),
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rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
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}
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/* Poll all queues to verify they have shut down */
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for (ms_wait = 0; ms_wait < 10; ms_wait++) {
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msec_delay(1);
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rx_enabled = 0;
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for (i = 0; i < 4; i++)
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rx_enabled |= IGC_READ_REG(hw, IGC_RXDCTL(i));
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if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
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break;
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}
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if (ms_wait == 10)
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DEBUGOUT("Queue disable timed out after 10ms\n");
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/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
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* incoming packets are rejected. Set enable and wait 2ms so that
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* any packet that was coming in as RCTL.EN was set is flushed
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*/
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IGC_WRITE_REG(hw, IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);
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rlpml = IGC_READ_REG(hw, IGC_RLPML);
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IGC_WRITE_REG(hw, IGC_RLPML, 0);
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rctl = IGC_READ_REG(hw, IGC_RCTL);
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temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
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temp_rctl |= IGC_RCTL_LPE;
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IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl);
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IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl | IGC_RCTL_EN);
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IGC_WRITE_FLUSH(hw);
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msec_delay(2);
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/* Enable Rx queues that were previously enabled and restore our
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* previous state
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*/
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for (i = 0; i < 4; i++)
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IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl[i]);
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IGC_WRITE_REG(hw, IGC_RCTL, rctl);
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IGC_WRITE_FLUSH(hw);
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IGC_WRITE_REG(hw, IGC_RLPML, rlpml);
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IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
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/* Flush receive errors generated by workaround */
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IGC_READ_REG(hw, IGC_ROC);
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IGC_READ_REG(hw, IGC_RNBC);
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IGC_READ_REG(hw, IGC_MPC);
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}
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