340 lines
9.9 KiB
C
340 lines
9.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
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*
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* Copyright (c) 2017-2018 Panasas
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/endian.h>
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#include <sys/errno.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/syslog.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/atomic.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/smbus/smbconf.h>
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#include "imcsmb_reg.h"
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#include "imcsmb_var.h"
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/* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two
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* "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
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* SMBus controllers. These are used for reading SPD data from the DIMMs, and
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* for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
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* are very simple devices, and have limited functionality compared to
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* full-fledged SMBus controllers, like the one in Intel ICHs and PCHs.
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*
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* The publicly available documentation for the iMC SMBus controllers can be
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* found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and
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* (Has,broad)well-Xeon, respectively:
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*
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* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/
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* Sandybridge xeon-e5-1600-2600-vol-2-datasheet.pdf
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* Ivybridge xeon-e5-v2-datasheet-vol-2.pdf
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* Haswell xeon-e5-v3-datasheet-vol-2.pdf
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* Broadwell xeon-e5-v4-datasheet-vol-2.pdf
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*
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* Another useful resource is the Linux driver. It is not in the main tree.
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*
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* https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg840043.html
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*
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* The iMC SMBus controllers do not support interrupts (thus, they must be
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* polled for IO completion). All of the iMC registers are in PCI configuration
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* space; there is no support for PIO or MMIO. As a result, this driver does
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* not need to perform and newbus resource manipulation.
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*
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* Because there are multiple SMBus controllers sharing the same PCI device,
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* this driver is actually *two* drivers:
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*
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* - "imcsmb" is an smbus(4)-compliant SMBus controller driver
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*
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* - "imcsmb_pci" recognizes the PCI device and assigns the appropriate set of
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* PCI config registers to a specific "imcsmb" instance.
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*/
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/* Depending on the motherboard and firmware, the TSODs might be polled by
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* firmware. Therefore, when this driver accesses these SMBus controllers, the
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* firmware polling must be disabled as part of requesting the bus, and
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* re-enabled when releasing the bus. Unfortunately, the details of how to do
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* this are vendor-specific. Contact your motherboard vendor to get the
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* information you need to do proper implementations.
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*
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* For NVDIMMs which conform to the ACPI "NFIT" standard, the ACPI firmware
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* manages the NVDIMM; for those which pre-date the standard, the operating
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* system interacts with the NVDIMM controller using a vendor-proprietary API
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* over the SMBus. In that case, the NVDIMM driver would be an SMBus slave
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* device driver, and would interface with the hardware via an SMBus controller
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* driver such as this one.
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*/
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/* PCIe device IDs for (Sandy,Ivy)bridge)-Xeon and (Has,Broad)well-Xeon */
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#define PCI_VENDOR_INTEL 0x8086
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#define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8
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#define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8
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#define IMCSMB_PCI_DEV_ID_IMC0_HSX 0x2fa8
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#define IMCSMB_PCI_DEV_ID_IMC0_BDX 0x6fa8
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/* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */
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#define IMCSMB_PCI_DEV_ID_IMC1_HSX 0x2f68
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#define IMCSMB_PCI_DEV_ID_IMC1_BDX 0x6f68
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/* There are two SMBus controllers in each device. These define the registers
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* for each of these devices.
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*/
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static struct imcsmb_reg_set imcsmb_regs[] = {
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{
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.smb_stat = IMCSMB_REG_STATUS0,
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.smb_cmd = IMCSMB_REG_COMMAND0,
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.smb_cntl = IMCSMB_REG_CONTROL0
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},
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{
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.smb_stat = IMCSMB_REG_STATUS1,
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.smb_cmd = IMCSMB_REG_COMMAND1,
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.smb_cntl = IMCSMB_REG_CONTROL1
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},
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};
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static struct imcsmb_pci_device {
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uint16_t id;
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char *name;
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} imcsmb_pci_devices[] = {
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{IMCSMB_PCI_DEV_ID_IMC0_SBX,
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"Intel Sandybridge Xeon iMC 0 SMBus controllers" },
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{IMCSMB_PCI_DEV_ID_IMC0_IBX,
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"Intel Ivybridge Xeon iMC 0 SMBus controllers" },
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{IMCSMB_PCI_DEV_ID_IMC0_HSX,
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"Intel Haswell Xeon iMC 0 SMBus controllers" },
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{IMCSMB_PCI_DEV_ID_IMC1_HSX,
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"Intel Haswell Xeon iMC 1 SMBus controllers" },
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{IMCSMB_PCI_DEV_ID_IMC0_BDX,
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"Intel Broadwell Xeon iMC 0 SMBus controllers" },
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{IMCSMB_PCI_DEV_ID_IMC1_BDX,
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"Intel Broadwell Xeon iMC 1 SMBus controllers" },
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{0, NULL},
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};
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/* Device methods. */
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static int imcsmb_pci_attach(device_t dev);
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static int imcsmb_pci_detach(device_t dev);
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static int imcsmb_pci_probe(device_t dev);
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/**
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* device_attach() method. Set up the PCI device's softc, then explicitly create
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* children for the actual imcsmbX controllers. Set up the child's ivars to
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* point to the proper set of the PCI device's config registers.
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*
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* @author Joe Kloss, rpokala
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*
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* @param[in,out] dev
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* Device being attached.
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*/
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static int
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imcsmb_pci_attach(device_t dev)
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{
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struct imcsmb_pci_softc *sc;
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device_t child;
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int rc;
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int unit;
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/* Initialize private state */
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->semaphore = 0;
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/* Create the imcsmbX children */
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for (unit = 0; unit < 2; unit++) {
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child = device_add_child(dev, "imcsmb", -1);
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if (child == NULL) {
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/* Nothing has been allocated, so there's no cleanup. */
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device_printf(dev, "Child imcsmb not added\n");
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rc = ENXIO;
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goto out;
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}
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/* Set the child's ivars to point to the appropriate set of
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* the PCI device's registers.
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*/
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device_set_ivars(child, &imcsmb_regs[unit]);
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}
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/* Attach the imcsmbX children. */
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if ((rc = bus_generic_attach(dev)) != 0) {
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device_printf(dev, "failed to attach children: %d\n", rc);
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goto out;
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}
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out:
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return (rc);
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}
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/**
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* device_detach() method. attach() didn't do any allocations, so all that's
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* needed here is to free up any downstream drivers and children.
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*
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* @author Joe Kloss
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*
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* @param[in] dev
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* Device being detached.
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*/
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static int
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imcsmb_pci_detach(device_t dev)
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{
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int rc;
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/* Detach any attached drivers */
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rc = bus_generic_detach(dev);
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if (rc == 0) {
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/* Remove all children */
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rc = device_delete_children(dev);
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}
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return (rc);
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}
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/**
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* device_probe() method. Look for the right PCI vendor/device IDs.
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*
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* @author Joe Kloss, rpokala
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*
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* @param[in,out] dev
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* Device being probed.
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*/
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static int
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imcsmb_pci_probe(device_t dev)
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{
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struct imcsmb_pci_device *pci_device;
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int rc;
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uint16_t pci_dev_id;
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rc = ENXIO;
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if (pci_get_vendor(dev) != PCI_VENDOR_INTEL) {
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goto out;
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}
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pci_dev_id = pci_get_device(dev);
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for (pci_device = imcsmb_pci_devices;
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pci_device->name != NULL;
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pci_device++) {
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if (pci_dev_id == pci_device->id) {
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device_set_desc(dev, pci_device->name);
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rc = BUS_PROBE_DEFAULT;
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goto out;
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}
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}
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out:
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return (rc);
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}
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/**
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* Invoked via smbus_callback() -> imcsmb_callback(); clear the semaphore, and
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* re-enable motherboard-specific DIMM temperature monitoring if needed. This
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* gets called after the transaction completes.
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*
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* @author Joe Kloss
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*
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* @param[in,out] dev
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* The device whose busses to release.
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*/
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void
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imcsmb_pci_release_bus(device_t dev)
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{
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struct imcsmb_pci_softc *sc;
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sc = device_get_softc(dev);
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/*
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* IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO RE-ENABLE DIMM
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* TEMPERATURE MONITORING HERE.
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*/
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atomic_store_rel_int(&sc->semaphore, 0);
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}
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/**
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* Invoked via smbus_callback() -> imcsmb_callback(); set the semaphore, and
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* disable motherboard-specific DIMM temperature monitoring if needed. This gets
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* called before the transaction starts.
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*
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* @author Joe Kloss
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*
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* @param[in,out] dev
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* The device whose busses to request.
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*/
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int
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imcsmb_pci_request_bus(device_t dev)
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{
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struct imcsmb_pci_softc *sc;
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int rc;
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sc = device_get_softc(dev);
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rc = 0;
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/* We don't want to block. Use a simple test-and-set semaphore to
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* protect the bus.
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*/
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if (atomic_cmpset_acq_int(&sc->semaphore, 0, 1) == 0) {
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rc = EWOULDBLOCK;
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}
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/*
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* IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO DISABLE DIMM
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* TEMPERATURE MONITORING HERE.
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*/
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return (rc);
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}
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/* Device methods */
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static device_method_t imcsmb_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_attach, imcsmb_pci_attach),
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DEVMETHOD(device_detach, imcsmb_pci_detach),
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DEVMETHOD(device_probe, imcsmb_pci_probe),
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DEVMETHOD_END
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};
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static driver_t imcsmb_pci_driver = {
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.name = "imcsmb_pci",
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.methods = imcsmb_pci_methods,
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.size = sizeof(struct imcsmb_pci_softc),
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};
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DRIVER_MODULE(imcsmb_pci, pci, imcsmb_pci_driver, 0, 0);
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MODULE_DEPEND(imcsmb_pci, pci, 1, 1, 1);
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MODULE_VERSION(imcsmb_pci, 1);
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/* vi: set ts=8 sw=4 sts=8 noet: */
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