5710 lines
156 KiB
C
5710 lines
156 KiB
C
/******************************************************************************
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SPDX-License-Identifier: BSD-3-Clause
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Copyright (c) 2001-2020, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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#include "ixgbe_common.h"
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#include "ixgbe_phy.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82599.h"
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#include "ixgbe_api.h"
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static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
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static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
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static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
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static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
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static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
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static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
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u16 count);
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static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
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static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
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static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
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static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
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static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
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static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
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u16 *san_mac_offset);
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static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
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u16 offset);
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/**
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* ixgbe_init_ops_generic - Inits function ptrs
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* @hw: pointer to the hardware structure
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*
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* Initialize the function pointers.
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**/
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s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
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{
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struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
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struct ixgbe_mac_info *mac = &hw->mac;
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u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
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DEBUGFUNC("ixgbe_init_ops_generic");
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/* EEPROM */
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eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
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/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
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if (eec & IXGBE_EEC_PRES) {
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eeprom->ops.read = ixgbe_read_eerd_generic;
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eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
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} else {
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eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
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eeprom->ops.read_buffer =
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ixgbe_read_eeprom_buffer_bit_bang_generic;
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}
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eeprom->ops.write = ixgbe_write_eeprom_generic;
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eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
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eeprom->ops.validate_checksum =
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ixgbe_validate_eeprom_checksum_generic;
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eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
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eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
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/* MAC */
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mac->ops.init_hw = ixgbe_init_hw_generic;
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mac->ops.reset_hw = NULL;
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mac->ops.start_hw = ixgbe_start_hw_generic;
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mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
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mac->ops.get_media_type = NULL;
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mac->ops.get_supported_physical_layer = NULL;
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mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
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mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
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mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
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mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
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mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
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mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
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mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
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mac->ops.prot_autoc_read = prot_autoc_read_generic;
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mac->ops.prot_autoc_write = prot_autoc_write_generic;
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/* LEDs */
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mac->ops.led_on = ixgbe_led_on_generic;
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mac->ops.led_off = ixgbe_led_off_generic;
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mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
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mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
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mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
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/* RAR, Multicast, VLAN */
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mac->ops.set_rar = ixgbe_set_rar_generic;
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mac->ops.clear_rar = ixgbe_clear_rar_generic;
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mac->ops.insert_mac_addr = NULL;
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mac->ops.set_vmdq = NULL;
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mac->ops.clear_vmdq = NULL;
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mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
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mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
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mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
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mac->ops.enable_mc = ixgbe_enable_mc_generic;
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mac->ops.disable_mc = ixgbe_disable_mc_generic;
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mac->ops.clear_vfta = NULL;
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mac->ops.set_vfta = NULL;
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mac->ops.set_vlvf = NULL;
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mac->ops.init_uta_tables = NULL;
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mac->ops.enable_rx = ixgbe_enable_rx_generic;
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mac->ops.disable_rx = ixgbe_disable_rx_generic;
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/* Flow Control */
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mac->ops.fc_enable = ixgbe_fc_enable_generic;
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mac->ops.setup_fc = ixgbe_setup_fc_generic;
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mac->ops.fc_autoneg = ixgbe_fc_autoneg;
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/* Link */
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mac->ops.get_link_capabilities = NULL;
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mac->ops.setup_link = NULL;
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mac->ops.check_link = NULL;
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mac->ops.dmac_config = NULL;
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mac->ops.dmac_update_tcs = NULL;
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mac->ops.dmac_config_tcs = NULL;
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
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* of flow control
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* @hw: pointer to hardware structure
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*
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* This function returns true if the device supports flow control
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* autonegotiation, and false if it does not.
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*
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**/
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bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
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{
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bool supported = false;
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ixgbe_link_speed speed;
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bool link_up;
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DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
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switch (hw->phy.media_type) {
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case ixgbe_media_type_fiber_fixed:
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case ixgbe_media_type_fiber_qsfp:
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case ixgbe_media_type_fiber:
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/* flow control autoneg black list */
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switch (hw->device_id) {
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case IXGBE_DEV_ID_X550EM_A_SFP:
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case IXGBE_DEV_ID_X550EM_A_SFP_N:
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case IXGBE_DEV_ID_X550EM_A_QSFP:
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case IXGBE_DEV_ID_X550EM_A_QSFP_N:
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supported = false;
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break;
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default:
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hw->mac.ops.check_link(hw, &speed, &link_up, false);
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/* if link is down, assume supported */
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if (link_up)
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supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
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true : false;
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else
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supported = true;
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}
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break;
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case ixgbe_media_type_backplane:
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if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
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supported = false;
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else
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supported = true;
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break;
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case ixgbe_media_type_copper:
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/* only some copper devices support flow control autoneg */
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switch (hw->device_id) {
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case IXGBE_DEV_ID_82599_T3_LOM:
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case IXGBE_DEV_ID_X540T:
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case IXGBE_DEV_ID_X540T1:
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case IXGBE_DEV_ID_X540_BYPASS:
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case IXGBE_DEV_ID_X550T:
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case IXGBE_DEV_ID_X550T1:
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case IXGBE_DEV_ID_X550EM_X_10G_T:
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case IXGBE_DEV_ID_X550EM_A_10G_T:
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case IXGBE_DEV_ID_X550EM_A_1G_T:
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case IXGBE_DEV_ID_X550EM_A_1G_T_L:
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supported = true;
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break;
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default:
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supported = false;
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}
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default:
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break;
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}
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if (!supported)
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ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
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"Device %x does not support flow control autoneg",
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hw->device_id);
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return supported;
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}
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/**
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* ixgbe_setup_fc_generic - Set up flow control
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* @hw: pointer to hardware structure
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*
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* Called at init time to set up flow control.
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**/
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s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
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{
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s32 ret_val = IXGBE_SUCCESS;
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u32 reg = 0, reg_bp = 0;
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u16 reg_cu = 0;
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bool locked = false;
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DEBUGFUNC("ixgbe_setup_fc_generic");
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/* Validate the requested mode */
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if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
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ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
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"ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
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ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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/*
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* 10gig parts do not have a word in the EEPROM to determine the
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* default flow control setting, so we explicitly set it to full.
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*/
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if (hw->fc.requested_mode == ixgbe_fc_default)
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hw->fc.requested_mode = ixgbe_fc_full;
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/*
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* Set up the 1G and 10G flow control advertisement registers so the
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* HW will be able to do fc autoneg once the cable is plugged in. If
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* we link at 10G, the 1G advertisement is harmless and vice versa.
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*/
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switch (hw->phy.media_type) {
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case ixgbe_media_type_backplane:
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/* some MAC's need RMW protection on AUTOC */
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ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
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if (ret_val != IXGBE_SUCCESS)
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goto out;
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/* only backplane uses autoc */
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/* FALLTHROUGH */
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case ixgbe_media_type_fiber_fixed:
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case ixgbe_media_type_fiber_qsfp:
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case ixgbe_media_type_fiber:
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reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
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break;
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case ixgbe_media_type_copper:
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hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
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break;
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default:
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break;
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}
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/*
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* The possible values of fc.requested_mode are:
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames,
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* but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames but
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* we do not support receiving pause frames).
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* 3: Both Rx and Tx flow control (symmetric) are enabled.
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* other: Invalid.
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*/
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switch (hw->fc.requested_mode) {
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case ixgbe_fc_none:
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/* Flow control completely disabled by software override. */
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reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
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if (hw->phy.media_type == ixgbe_media_type_backplane)
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reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
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IXGBE_AUTOC_ASM_PAUSE);
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else if (hw->phy.media_type == ixgbe_media_type_copper)
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reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
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break;
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case ixgbe_fc_tx_pause:
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/*
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* Tx Flow control is enabled, and Rx Flow control is
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* disabled by software override.
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*/
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reg |= IXGBE_PCS1GANA_ASM_PAUSE;
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reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
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if (hw->phy.media_type == ixgbe_media_type_backplane) {
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reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
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reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
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} else if (hw->phy.media_type == ixgbe_media_type_copper) {
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reg_cu |= IXGBE_TAF_ASM_PAUSE;
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reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
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}
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break;
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case ixgbe_fc_rx_pause:
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/*
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* Rx Flow control is enabled and Tx Flow control is
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* disabled by software override. Since there really
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* isn't a way to advertise that we are capable of RX
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* Pause ONLY, we will advertise that we support both
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* symmetric and asymmetric Rx PAUSE, as such we fall
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* through to the fc_full statement. Later, we will
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* disable the adapter's ability to send PAUSE frames.
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*/
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case ixgbe_fc_full:
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/* Flow control (both Rx and Tx) is enabled by SW override. */
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reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
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if (hw->phy.media_type == ixgbe_media_type_backplane)
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reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
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IXGBE_AUTOC_ASM_PAUSE;
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else if (hw->phy.media_type == ixgbe_media_type_copper)
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reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
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break;
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default:
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ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
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"Flow control param set incorrectly\n");
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ret_val = IXGBE_ERR_CONFIG;
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goto out;
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break;
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}
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if (hw->mac.type < ixgbe_mac_X540) {
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/*
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* Enable auto-negotiation between the MAC & PHY;
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* the MAC will advertise clause 37 flow control.
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*/
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IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
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/* Disable AN timeout */
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if (hw->fc.strict_ieee)
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reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
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IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
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DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
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}
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/*
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* AUTOC restart handles negotiation of 1G and 10G on backplane
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* and copper. There is no need to set the PCS1GCTL register.
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*
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*/
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if (hw->phy.media_type == ixgbe_media_type_backplane) {
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reg_bp |= IXGBE_AUTOC_AN_RESTART;
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ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
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if (ret_val)
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goto out;
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} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
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(ixgbe_device_supports_autoneg_fc(hw))) {
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hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
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}
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DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
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out:
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return ret_val;
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}
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/**
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* ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
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* @hw: pointer to hardware structure
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*
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* Starts the hardware by filling the bus info structure and media type, clears
|
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* all on chip counters, initializes receive address registers, multicast
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* table, VLAN filter table, calls routine to set up link and flow control
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* settings, and leaves transmit and receive units disabled and uninitialized
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**/
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s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
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{
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s32 ret_val;
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u32 ctrl_ext;
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u16 device_caps;
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DEBUGFUNC("ixgbe_start_hw_generic");
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/* Set the media type */
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hw->phy.media_type = hw->mac.ops.get_media_type(hw);
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/* PHY ops initialization must be done in reset_hw() */
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/* Clear the VLAN filter table */
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hw->mac.ops.clear_vfta(hw);
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/* Clear statistics registers */
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hw->mac.ops.clear_hw_cntrs(hw);
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/* Set No Snoop Disable */
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ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
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ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
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IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
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IXGBE_WRITE_FLUSH(hw);
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/* Setup flow control */
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ret_val = ixgbe_setup_fc(hw);
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if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
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DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
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return ret_val;
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}
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|
/* Cache bit indicating need for crosstalk fix */
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X550EM_x:
|
|
case ixgbe_mac_X550EM_a:
|
|
hw->mac.ops.get_device_caps(hw, &device_caps);
|
|
if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
|
|
hw->need_crosstalk_fix = false;
|
|
else
|
|
hw->need_crosstalk_fix = true;
|
|
break;
|
|
default:
|
|
hw->need_crosstalk_fix = false;
|
|
break;
|
|
}
|
|
|
|
/* Clear adapter stopped flag */
|
|
hw->adapter_stopped = false;
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_start_hw_gen2 - Init sequence for common device family
|
|
* @hw: pointer to hw structure
|
|
*
|
|
* Performs the init sequence common to the second generation
|
|
* of 10 GbE devices.
|
|
* Devices in the second generation:
|
|
* 82599
|
|
* X540
|
|
**/
|
|
void ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
|
|
{
|
|
u32 i;
|
|
u32 regval;
|
|
|
|
/* Clear the rate limiters */
|
|
for (i = 0; i < hw->mac.max_tx_queues; i++) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
|
|
IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
|
|
}
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
/* Disable relaxed ordering */
|
|
for (i = 0; i < hw->mac.max_tx_queues; i++) {
|
|
regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
|
|
regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
|
|
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
|
|
}
|
|
|
|
for (i = 0; i < hw->mac.max_rx_queues; i++) {
|
|
regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
|
|
regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
|
|
IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
|
|
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ixgbe_init_hw_generic - Generic hardware initialization
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Initialize the hardware by resetting the hardware, filling the bus info
|
|
* structure and media type, clears all on chip counters, initializes receive
|
|
* address registers, multicast table, VLAN filter table, calls routine to set
|
|
* up link and flow control settings, and leaves transmit and receive units
|
|
* disabled and uninitialized
|
|
**/
|
|
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status;
|
|
|
|
DEBUGFUNC("ixgbe_init_hw_generic");
|
|
|
|
/* Reset the hardware */
|
|
status = hw->mac.ops.reset_hw(hw);
|
|
|
|
if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
|
|
/* Start the HW */
|
|
status = hw->mac.ops.start_hw(hw);
|
|
}
|
|
|
|
/* Initialize the LED link active for LED blink support */
|
|
if (hw->mac.ops.init_led_link_act)
|
|
hw->mac.ops.init_led_link_act(hw);
|
|
|
|
if (status != IXGBE_SUCCESS)
|
|
DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Clears all hardware statistics counters by reading them from the hardware
|
|
* Statistics counters are clear on read.
|
|
**/
|
|
s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u16 i = 0;
|
|
|
|
DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
|
|
|
|
IXGBE_READ_REG(hw, IXGBE_CRCERRS);
|
|
IXGBE_READ_REG(hw, IXGBE_ILLERRC);
|
|
IXGBE_READ_REG(hw, IXGBE_ERRBC);
|
|
IXGBE_READ_REG(hw, IXGBE_MSPDC);
|
|
for (i = 0; i < 8; i++)
|
|
IXGBE_READ_REG(hw, IXGBE_MPC(i));
|
|
|
|
IXGBE_READ_REG(hw, IXGBE_MLFC);
|
|
IXGBE_READ_REG(hw, IXGBE_MRFC);
|
|
IXGBE_READ_REG(hw, IXGBE_RLEC);
|
|
IXGBE_READ_REG(hw, IXGBE_LXONTXC);
|
|
IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
|
|
if (hw->mac.type >= ixgbe_mac_82599EB) {
|
|
IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
|
|
IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
|
|
} else {
|
|
IXGBE_READ_REG(hw, IXGBE_LXONRXC);
|
|
IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
|
|
}
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
|
|
IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
|
|
if (hw->mac.type >= ixgbe_mac_82599EB) {
|
|
IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
|
|
IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
|
|
} else {
|
|
IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
|
|
IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
|
|
}
|
|
}
|
|
if (hw->mac.type >= ixgbe_mac_82599EB)
|
|
for (i = 0; i < 8; i++)
|
|
IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
|
|
IXGBE_READ_REG(hw, IXGBE_PRC64);
|
|
IXGBE_READ_REG(hw, IXGBE_PRC127);
|
|
IXGBE_READ_REG(hw, IXGBE_PRC255);
|
|
IXGBE_READ_REG(hw, IXGBE_PRC511);
|
|
IXGBE_READ_REG(hw, IXGBE_PRC1023);
|
|
IXGBE_READ_REG(hw, IXGBE_PRC1522);
|
|
IXGBE_READ_REG(hw, IXGBE_GPRC);
|
|
IXGBE_READ_REG(hw, IXGBE_BPRC);
|
|
IXGBE_READ_REG(hw, IXGBE_MPRC);
|
|
IXGBE_READ_REG(hw, IXGBE_GPTC);
|
|
IXGBE_READ_REG(hw, IXGBE_GORCL);
|
|
IXGBE_READ_REG(hw, IXGBE_GORCH);
|
|
IXGBE_READ_REG(hw, IXGBE_GOTCL);
|
|
IXGBE_READ_REG(hw, IXGBE_GOTCH);
|
|
if (hw->mac.type == ixgbe_mac_82598EB)
|
|
for (i = 0; i < 8; i++)
|
|
IXGBE_READ_REG(hw, IXGBE_RNBC(i));
|
|
IXGBE_READ_REG(hw, IXGBE_RUC);
|
|
IXGBE_READ_REG(hw, IXGBE_RFC);
|
|
IXGBE_READ_REG(hw, IXGBE_ROC);
|
|
IXGBE_READ_REG(hw, IXGBE_RJC);
|
|
IXGBE_READ_REG(hw, IXGBE_MNGPRC);
|
|
IXGBE_READ_REG(hw, IXGBE_MNGPDC);
|
|
IXGBE_READ_REG(hw, IXGBE_MNGPTC);
|
|
IXGBE_READ_REG(hw, IXGBE_TORL);
|
|
IXGBE_READ_REG(hw, IXGBE_TORH);
|
|
IXGBE_READ_REG(hw, IXGBE_TPR);
|
|
IXGBE_READ_REG(hw, IXGBE_TPT);
|
|
IXGBE_READ_REG(hw, IXGBE_PTC64);
|
|
IXGBE_READ_REG(hw, IXGBE_PTC127);
|
|
IXGBE_READ_REG(hw, IXGBE_PTC255);
|
|
IXGBE_READ_REG(hw, IXGBE_PTC511);
|
|
IXGBE_READ_REG(hw, IXGBE_PTC1023);
|
|
IXGBE_READ_REG(hw, IXGBE_PTC1522);
|
|
IXGBE_READ_REG(hw, IXGBE_MPTC);
|
|
IXGBE_READ_REG(hw, IXGBE_BPTC);
|
|
for (i = 0; i < 16; i++) {
|
|
IXGBE_READ_REG(hw, IXGBE_QPRC(i));
|
|
IXGBE_READ_REG(hw, IXGBE_QPTC(i));
|
|
if (hw->mac.type >= ixgbe_mac_82599EB) {
|
|
IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
|
|
IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
|
|
IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
|
|
IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
|
|
IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
|
|
} else {
|
|
IXGBE_READ_REG(hw, IXGBE_QBRC(i));
|
|
IXGBE_READ_REG(hw, IXGBE_QBTC(i));
|
|
}
|
|
}
|
|
|
|
if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
|
|
if (hw->phy.id == 0)
|
|
ixgbe_identify_phy(hw);
|
|
hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
|
|
IXGBE_MDIO_PCS_DEV_TYPE, &i);
|
|
hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
|
|
IXGBE_MDIO_PCS_DEV_TYPE, &i);
|
|
hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
|
|
IXGBE_MDIO_PCS_DEV_TYPE, &i);
|
|
hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
|
|
IXGBE_MDIO_PCS_DEV_TYPE, &i);
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_pba_string_generic - Reads part number string from EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @pba_num: stores the part number string from the EEPROM
|
|
* @pba_num_size: part number string buffer length
|
|
*
|
|
* Reads the part number string from the EEPROM.
|
|
**/
|
|
s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
|
|
u32 pba_num_size)
|
|
{
|
|
s32 ret_val;
|
|
u16 data;
|
|
u16 pba_ptr;
|
|
u16 offset;
|
|
u16 length;
|
|
|
|
DEBUGFUNC("ixgbe_read_pba_string_generic");
|
|
|
|
if (pba_num == NULL) {
|
|
DEBUGOUT("PBA string buffer was null\n");
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
return ret_val;
|
|
}
|
|
|
|
ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
return ret_val;
|
|
}
|
|
|
|
/*
|
|
* if data is not ptr guard the PBA must be in legacy format which
|
|
* means pba_ptr is actually our second data word for the PBA number
|
|
* and we can decode it into an ascii string
|
|
*/
|
|
if (data != IXGBE_PBANUM_PTR_GUARD) {
|
|
DEBUGOUT("NVM PBA number is not stored as string\n");
|
|
|
|
/* we will need 11 characters to store the PBA */
|
|
if (pba_num_size < 11) {
|
|
DEBUGOUT("PBA string buffer too small\n");
|
|
return IXGBE_ERR_NO_SPACE;
|
|
}
|
|
|
|
/* extract hex string from data and pba_ptr */
|
|
pba_num[0] = (data >> 12) & 0xF;
|
|
pba_num[1] = (data >> 8) & 0xF;
|
|
pba_num[2] = (data >> 4) & 0xF;
|
|
pba_num[3] = data & 0xF;
|
|
pba_num[4] = (pba_ptr >> 12) & 0xF;
|
|
pba_num[5] = (pba_ptr >> 8) & 0xF;
|
|
pba_num[6] = '-';
|
|
pba_num[7] = 0;
|
|
pba_num[8] = (pba_ptr >> 4) & 0xF;
|
|
pba_num[9] = pba_ptr & 0xF;
|
|
|
|
/* put a null character on the end of our string */
|
|
pba_num[10] = '\0';
|
|
|
|
/* switch all the data but the '-' to hex char */
|
|
for (offset = 0; offset < 10; offset++) {
|
|
if (pba_num[offset] < 0xA)
|
|
pba_num[offset] += '0';
|
|
else if (pba_num[offset] < 0x10)
|
|
pba_num[offset] += 'A' - 0xA;
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
return ret_val;
|
|
}
|
|
|
|
if (length == 0xFFFF || length == 0) {
|
|
DEBUGOUT("NVM PBA number section invalid length\n");
|
|
return IXGBE_ERR_PBA_SECTION;
|
|
}
|
|
|
|
/* check if pba_num buffer is big enough */
|
|
if (pba_num_size < (((u32)length * 2) - 1)) {
|
|
DEBUGOUT("PBA string buffer too small\n");
|
|
return IXGBE_ERR_NO_SPACE;
|
|
}
|
|
|
|
/* trim pba length from start of string */
|
|
pba_ptr++;
|
|
length--;
|
|
|
|
for (offset = 0; offset < length; offset++) {
|
|
ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
return ret_val;
|
|
}
|
|
pba_num[offset * 2] = (u8)(data >> 8);
|
|
pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
|
|
}
|
|
pba_num[offset * 2] = '\0';
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_pba_num_generic - Reads part number from EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @pba_num: stores the part number from the EEPROM
|
|
*
|
|
* Reads the part number from the EEPROM.
|
|
**/
|
|
s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
|
|
{
|
|
s32 ret_val;
|
|
u16 data;
|
|
|
|
DEBUGFUNC("ixgbe_read_pba_num_generic");
|
|
|
|
ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
return ret_val;
|
|
} else if (data == IXGBE_PBANUM_PTR_GUARD) {
|
|
DEBUGOUT("NVM Not supported\n");
|
|
return IXGBE_NOT_IMPLEMENTED;
|
|
}
|
|
*pba_num = (u32)(data << 16);
|
|
|
|
ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
return ret_val;
|
|
}
|
|
*pba_num |= (u32)data;
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_pba_raw
|
|
* @hw: pointer to the HW structure
|
|
* @eeprom_buf: optional pointer to EEPROM image
|
|
* @eeprom_buf_size: size of EEPROM image in words
|
|
* @max_pba_block_size: PBA block size limit
|
|
* @pba: pointer to output PBA structure
|
|
*
|
|
* Reads PBA from EEPROM image when eeprom_buf is not NULL.
|
|
* Reads PBA from physical EEPROM device when eeprom_buf is NULL.
|
|
*
|
|
**/
|
|
s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
|
|
u32 eeprom_buf_size, u16 max_pba_block_size,
|
|
struct ixgbe_pba *pba)
|
|
{
|
|
s32 ret_val;
|
|
u16 pba_block_size;
|
|
|
|
if (pba == NULL)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
if (eeprom_buf == NULL) {
|
|
ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
|
|
&pba->word[0]);
|
|
if (ret_val)
|
|
return ret_val;
|
|
} else {
|
|
if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
|
|
pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
|
|
pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
|
|
} else {
|
|
return IXGBE_ERR_PARAM;
|
|
}
|
|
}
|
|
|
|
if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
|
|
if (pba->pba_block == NULL)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
|
|
eeprom_buf_size,
|
|
&pba_block_size);
|
|
if (ret_val)
|
|
return ret_val;
|
|
|
|
if (pba_block_size > max_pba_block_size)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
if (eeprom_buf == NULL) {
|
|
ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
|
|
pba_block_size,
|
|
pba->pba_block);
|
|
if (ret_val)
|
|
return ret_val;
|
|
} else {
|
|
if (eeprom_buf_size > (u32)(pba->word[1] +
|
|
pba_block_size)) {
|
|
memcpy(pba->pba_block,
|
|
&eeprom_buf[pba->word[1]],
|
|
pba_block_size * sizeof(u16));
|
|
} else {
|
|
return IXGBE_ERR_PARAM;
|
|
}
|
|
}
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_write_pba_raw
|
|
* @hw: pointer to the HW structure
|
|
* @eeprom_buf: optional pointer to EEPROM image
|
|
* @eeprom_buf_size: size of EEPROM image in words
|
|
* @pba: pointer to PBA structure
|
|
*
|
|
* Writes PBA to EEPROM image when eeprom_buf is not NULL.
|
|
* Writes PBA to physical EEPROM device when eeprom_buf is NULL.
|
|
*
|
|
**/
|
|
s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
|
|
u32 eeprom_buf_size, struct ixgbe_pba *pba)
|
|
{
|
|
s32 ret_val;
|
|
|
|
if (pba == NULL)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
if (eeprom_buf == NULL) {
|
|
ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
|
|
&pba->word[0]);
|
|
if (ret_val)
|
|
return ret_val;
|
|
} else {
|
|
if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
|
|
eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
|
|
eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
|
|
} else {
|
|
return IXGBE_ERR_PARAM;
|
|
}
|
|
}
|
|
|
|
if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
|
|
if (pba->pba_block == NULL)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
if (eeprom_buf == NULL) {
|
|
ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
|
|
pba->pba_block[0],
|
|
pba->pba_block);
|
|
if (ret_val)
|
|
return ret_val;
|
|
} else {
|
|
if (eeprom_buf_size > (u32)(pba->word[1] +
|
|
pba->pba_block[0])) {
|
|
memcpy(&eeprom_buf[pba->word[1]],
|
|
pba->pba_block,
|
|
pba->pba_block[0] * sizeof(u16));
|
|
} else {
|
|
return IXGBE_ERR_PARAM;
|
|
}
|
|
}
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_pba_block_size
|
|
* @hw: pointer to the HW structure
|
|
* @eeprom_buf: optional pointer to EEPROM image
|
|
* @eeprom_buf_size: size of EEPROM image in words
|
|
* @pba_data_size: pointer to output variable
|
|
*
|
|
* Returns the size of the PBA block in words. Function operates on EEPROM
|
|
* image if the eeprom_buf pointer is not NULL otherwise it accesses physical
|
|
* EEPROM device.
|
|
*
|
|
**/
|
|
s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
|
|
u32 eeprom_buf_size, u16 *pba_block_size)
|
|
{
|
|
s32 ret_val;
|
|
u16 pba_word[2];
|
|
u16 length;
|
|
|
|
DEBUGFUNC("ixgbe_get_pba_block_size");
|
|
|
|
if (eeprom_buf == NULL) {
|
|
ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
|
|
&pba_word[0]);
|
|
if (ret_val)
|
|
return ret_val;
|
|
} else {
|
|
if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
|
|
pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
|
|
pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
|
|
} else {
|
|
return IXGBE_ERR_PARAM;
|
|
}
|
|
}
|
|
|
|
if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
|
|
if (eeprom_buf == NULL) {
|
|
ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
|
|
&length);
|
|
if (ret_val)
|
|
return ret_val;
|
|
} else {
|
|
if (eeprom_buf_size > pba_word[1])
|
|
length = eeprom_buf[pba_word[1] + 0];
|
|
else
|
|
return IXGBE_ERR_PARAM;
|
|
}
|
|
|
|
if (length == 0xFFFF || length == 0)
|
|
return IXGBE_ERR_PBA_SECTION;
|
|
} else {
|
|
/* PBA number in legacy format, there is no PBA Block. */
|
|
length = 0;
|
|
}
|
|
|
|
if (pba_block_size != NULL)
|
|
*pba_block_size = length;
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_mac_addr_generic - Generic get MAC address
|
|
* @hw: pointer to hardware structure
|
|
* @mac_addr: Adapter MAC address
|
|
*
|
|
* Reads the adapter's MAC address from first Receive Address Register (RAR0)
|
|
* A reset of the adapter must be performed prior to calling this function
|
|
* in order for the MAC address to have been loaded from the EEPROM into RAR0
|
|
**/
|
|
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
|
|
{
|
|
u32 rar_high;
|
|
u32 rar_low;
|
|
u16 i;
|
|
|
|
DEBUGFUNC("ixgbe_get_mac_addr_generic");
|
|
|
|
rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
|
|
rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
|
|
|
|
for (i = 0; i < 4; i++)
|
|
mac_addr[i] = (u8)(rar_low >> (i*8));
|
|
|
|
for (i = 0; i < 2; i++)
|
|
mac_addr[i+4] = (u8)(rar_high >> (i*8));
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_pci_config_data_generic - Generic store PCI bus info
|
|
* @hw: pointer to hardware structure
|
|
* @link_status: the link status returned by the PCI config space
|
|
*
|
|
* Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
|
|
**/
|
|
void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
|
|
{
|
|
struct ixgbe_mac_info *mac = &hw->mac;
|
|
|
|
if (hw->bus.type == ixgbe_bus_type_unknown)
|
|
hw->bus.type = ixgbe_bus_type_pci_express;
|
|
|
|
switch (link_status & IXGBE_PCI_LINK_WIDTH) {
|
|
case IXGBE_PCI_LINK_WIDTH_1:
|
|
hw->bus.width = ixgbe_bus_width_pcie_x1;
|
|
break;
|
|
case IXGBE_PCI_LINK_WIDTH_2:
|
|
hw->bus.width = ixgbe_bus_width_pcie_x2;
|
|
break;
|
|
case IXGBE_PCI_LINK_WIDTH_4:
|
|
hw->bus.width = ixgbe_bus_width_pcie_x4;
|
|
break;
|
|
case IXGBE_PCI_LINK_WIDTH_8:
|
|
hw->bus.width = ixgbe_bus_width_pcie_x8;
|
|
break;
|
|
default:
|
|
hw->bus.width = ixgbe_bus_width_unknown;
|
|
break;
|
|
}
|
|
|
|
switch (link_status & IXGBE_PCI_LINK_SPEED) {
|
|
case IXGBE_PCI_LINK_SPEED_2500:
|
|
hw->bus.speed = ixgbe_bus_speed_2500;
|
|
break;
|
|
case IXGBE_PCI_LINK_SPEED_5000:
|
|
hw->bus.speed = ixgbe_bus_speed_5000;
|
|
break;
|
|
case IXGBE_PCI_LINK_SPEED_8000:
|
|
hw->bus.speed = ixgbe_bus_speed_8000;
|
|
break;
|
|
default:
|
|
hw->bus.speed = ixgbe_bus_speed_unknown;
|
|
break;
|
|
}
|
|
|
|
mac->ops.set_lan_id(hw);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_bus_info_generic - Generic set PCI bus info
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Gets the PCI bus info (speed, width, type) then calls helper function to
|
|
* store this data within the ixgbe_hw structure.
|
|
**/
|
|
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u16 link_status;
|
|
|
|
DEBUGFUNC("ixgbe_get_bus_info_generic");
|
|
|
|
/* Get the negotiated link width and speed from PCI config space */
|
|
link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
|
|
|
|
ixgbe_set_pci_config_data_generic(hw, link_status);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Determines the LAN function id by reading memory-mapped registers and swaps
|
|
* the port value if requested, and set MAC instance for devices that share
|
|
* CS4227.
|
|
**/
|
|
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
|
|
{
|
|
struct ixgbe_bus_info *bus = &hw->bus;
|
|
u32 reg;
|
|
u16 ee_ctrl_4;
|
|
|
|
DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
|
|
|
|
reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
|
|
bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
|
|
bus->lan_id = (u8)bus->func;
|
|
|
|
/* check for a port swap */
|
|
reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
|
|
if (reg & IXGBE_FACTPS_LFS)
|
|
bus->func ^= 0x1;
|
|
|
|
/* Get MAC instance from EEPROM for configuring CS4227 */
|
|
if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
|
|
hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
|
|
bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
|
|
IXGBE_EE_CTRL_4_INST_ID_SHIFT;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
|
|
* disables transmit and receive units. The adapter_stopped flag is used by
|
|
* the shared code and drivers to determine if the adapter is in a stopped
|
|
* state and should not touch the hardware.
|
|
**/
|
|
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u32 reg_val;
|
|
u16 i;
|
|
|
|
DEBUGFUNC("ixgbe_stop_adapter_generic");
|
|
|
|
/*
|
|
* Set the adapter_stopped flag so other driver functions stop touching
|
|
* the hardware
|
|
*/
|
|
hw->adapter_stopped = true;
|
|
|
|
/* Disable the receive unit */
|
|
ixgbe_disable_rx(hw);
|
|
|
|
/* Clear interrupt mask to stop interrupts from being generated */
|
|
IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
|
|
|
|
/* Clear any pending interrupts, flush previous writes */
|
|
IXGBE_READ_REG(hw, IXGBE_EICR);
|
|
|
|
/* Disable the transmit unit. Each queue must be disabled. */
|
|
for (i = 0; i < hw->mac.max_tx_queues; i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
|
|
|
|
/* Disable the receive unit by stopping each queue */
|
|
for (i = 0; i < hw->mac.max_rx_queues; i++) {
|
|
reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
|
|
reg_val &= ~IXGBE_RXDCTL_ENABLE;
|
|
reg_val |= IXGBE_RXDCTL_SWFLSH;
|
|
IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
|
|
}
|
|
|
|
/* flush all queues disables */
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(2);
|
|
|
|
/*
|
|
* Prevent the PCI-E bus from hanging by disabling PCI-E master
|
|
* access and verify no pending requests
|
|
*/
|
|
return ixgbe_disable_pcie_master(hw);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_init_led_link_act_generic - Store the LED index link/activity.
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Store the index for the link active LED. This will be used to support
|
|
* blinking the LED.
|
|
**/
|
|
s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
|
|
{
|
|
struct ixgbe_mac_info *mac = &hw->mac;
|
|
u32 led_reg, led_mode;
|
|
u8 i;
|
|
|
|
led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
|
|
|
|
/* Get LED link active from the LEDCTL register */
|
|
for (i = 0; i < 4; i++) {
|
|
led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
|
|
|
|
if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
|
|
IXGBE_LED_LINK_ACTIVE) {
|
|
mac->led_link_act = i;
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* If LEDCTL register does not have the LED link active set, then use
|
|
* known MAC defaults.
|
|
*/
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_X550EM_a:
|
|
case ixgbe_mac_X550EM_x:
|
|
mac->led_link_act = 1;
|
|
break;
|
|
default:
|
|
mac->led_link_act = 2;
|
|
}
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_led_on_generic - Turns on the software controllable LEDs.
|
|
* @hw: pointer to hardware structure
|
|
* @index: led number to turn on
|
|
**/
|
|
s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
|
|
{
|
|
u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
|
|
|
|
DEBUGFUNC("ixgbe_led_on_generic");
|
|
|
|
if (index > 3)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
/* To turn on the LED, set mode to ON. */
|
|
led_reg &= ~IXGBE_LED_MODE_MASK(index);
|
|
led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
|
|
IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_led_off_generic - Turns off the software controllable LEDs.
|
|
* @hw: pointer to hardware structure
|
|
* @index: led number to turn off
|
|
**/
|
|
s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
|
|
{
|
|
u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
|
|
|
|
DEBUGFUNC("ixgbe_led_off_generic");
|
|
|
|
if (index > 3)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
/* To turn off the LED, set mode to OFF. */
|
|
led_reg &= ~IXGBE_LED_MODE_MASK(index);
|
|
led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
|
|
IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_init_eeprom_params_generic - Initialize EEPROM params
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Initializes the EEPROM parameters ixgbe_eeprom_info within the
|
|
* ixgbe_hw struct in order to set up EEPROM access.
|
|
**/
|
|
s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
|
|
{
|
|
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
|
|
u32 eec;
|
|
u16 eeprom_size;
|
|
|
|
DEBUGFUNC("ixgbe_init_eeprom_params_generic");
|
|
|
|
if (eeprom->type == ixgbe_eeprom_uninitialized) {
|
|
eeprom->type = ixgbe_eeprom_none;
|
|
/* Set default semaphore delay to 10ms which is a well
|
|
* tested value */
|
|
eeprom->semaphore_delay = 10;
|
|
/* Clear EEPROM page size, it will be initialized as needed */
|
|
eeprom->word_page_size = 0;
|
|
|
|
/*
|
|
* Check for EEPROM present first.
|
|
* If not present leave as none
|
|
*/
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
if (eec & IXGBE_EEC_PRES) {
|
|
eeprom->type = ixgbe_eeprom_spi;
|
|
|
|
/*
|
|
* SPI EEPROM is assumed here. This code would need to
|
|
* change if a future EEPROM is not SPI.
|
|
*/
|
|
eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
|
|
IXGBE_EEC_SIZE_SHIFT);
|
|
eeprom->word_size = 1 << (eeprom_size +
|
|
IXGBE_EEPROM_WORD_SIZE_SHIFT);
|
|
}
|
|
|
|
if (eec & IXGBE_EEC_ADDR_SIZE)
|
|
eeprom->address_bits = 16;
|
|
else
|
|
eeprom->address_bits = 8;
|
|
DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
|
|
"%d\n", eeprom->type, eeprom->word_size,
|
|
eeprom->address_bits);
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset within the EEPROM to write
|
|
* @words: number of word(s)
|
|
* @data: 16 bit word(s) to write to EEPROM
|
|
*
|
|
* Reads 16 bit word(s) from EEPROM through bit-bang method
|
|
**/
|
|
s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
|
|
u16 words, u16 *data)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
u16 i, count;
|
|
|
|
DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
|
|
|
|
hw->eeprom.ops.init_params(hw);
|
|
|
|
if (words == 0) {
|
|
status = IXGBE_ERR_INVALID_ARGUMENT;
|
|
goto out;
|
|
}
|
|
|
|
if (offset + words > hw->eeprom.word_size) {
|
|
status = IXGBE_ERR_EEPROM;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* The EEPROM page size cannot be queried from the chip. We do lazy
|
|
* initialization. It is worth to do that when we write large buffer.
|
|
*/
|
|
if ((hw->eeprom.word_page_size == 0) &&
|
|
(words > IXGBE_EEPROM_PAGE_SIZE_MAX))
|
|
ixgbe_detect_eeprom_page_size_generic(hw, offset);
|
|
|
|
/*
|
|
* We cannot hold synchronization semaphores for too long
|
|
* to avoid other entity starvation. However it is more efficient
|
|
* to read in bursts than synchronizing access for each word.
|
|
*/
|
|
for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
|
|
count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
|
|
IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
|
|
status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
|
|
count, &data[i]);
|
|
|
|
if (status != IXGBE_SUCCESS)
|
|
break;
|
|
}
|
|
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset within the EEPROM to be written to
|
|
* @words: number of word(s)
|
|
* @data: 16 bit word(s) to be written to the EEPROM
|
|
*
|
|
* If ixgbe_eeprom_update_checksum is not called after this function, the
|
|
* EEPROM will most likely contain an invalid checksum.
|
|
**/
|
|
static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
|
|
u16 words, u16 *data)
|
|
{
|
|
s32 status;
|
|
u16 word;
|
|
u16 page_size;
|
|
u16 i;
|
|
u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
|
|
|
|
DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
|
|
|
|
/* Prepare the EEPROM for writing */
|
|
status = ixgbe_acquire_eeprom(hw);
|
|
|
|
if (status == IXGBE_SUCCESS) {
|
|
if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
|
|
ixgbe_release_eeprom(hw);
|
|
status = IXGBE_ERR_EEPROM;
|
|
}
|
|
}
|
|
|
|
if (status == IXGBE_SUCCESS) {
|
|
for (i = 0; i < words; i++) {
|
|
ixgbe_standby_eeprom(hw);
|
|
|
|
/* Send the WRITE ENABLE command (8 bit opcode ) */
|
|
ixgbe_shift_out_eeprom_bits(hw,
|
|
IXGBE_EEPROM_WREN_OPCODE_SPI,
|
|
IXGBE_EEPROM_OPCODE_BITS);
|
|
|
|
ixgbe_standby_eeprom(hw);
|
|
|
|
/*
|
|
* Some SPI eeproms use the 8th address bit embedded
|
|
* in the opcode
|
|
*/
|
|
if ((hw->eeprom.address_bits == 8) &&
|
|
((offset + i) >= 128))
|
|
write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
|
|
|
|
/* Send the Write command (8-bit opcode + addr) */
|
|
ixgbe_shift_out_eeprom_bits(hw, write_opcode,
|
|
IXGBE_EEPROM_OPCODE_BITS);
|
|
ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
|
|
hw->eeprom.address_bits);
|
|
|
|
page_size = hw->eeprom.word_page_size;
|
|
|
|
/* Send the data in burst via SPI*/
|
|
do {
|
|
word = data[i];
|
|
word = (word >> 8) | (word << 8);
|
|
ixgbe_shift_out_eeprom_bits(hw, word, 16);
|
|
|
|
if (page_size == 0)
|
|
break;
|
|
|
|
/* do not wrap around page */
|
|
if (((offset + i) & (page_size - 1)) ==
|
|
(page_size - 1))
|
|
break;
|
|
} while (++i < words);
|
|
|
|
ixgbe_standby_eeprom(hw);
|
|
msec_delay(10);
|
|
}
|
|
/* Done with writing - release the EEPROM */
|
|
ixgbe_release_eeprom(hw);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset within the EEPROM to be written to
|
|
* @data: 16 bit word to be written to the EEPROM
|
|
*
|
|
* If ixgbe_eeprom_update_checksum is not called after this function, the
|
|
* EEPROM will most likely contain an invalid checksum.
|
|
**/
|
|
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
|
|
{
|
|
s32 status;
|
|
|
|
DEBUGFUNC("ixgbe_write_eeprom_generic");
|
|
|
|
hw->eeprom.ops.init_params(hw);
|
|
|
|
if (offset >= hw->eeprom.word_size) {
|
|
status = IXGBE_ERR_EEPROM;
|
|
goto out;
|
|
}
|
|
|
|
status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
|
|
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset within the EEPROM to be read
|
|
* @data: read 16 bit words(s) from EEPROM
|
|
* @words: number of word(s)
|
|
*
|
|
* Reads 16 bit word(s) from EEPROM through bit-bang method
|
|
**/
|
|
s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
|
|
u16 words, u16 *data)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
u16 i, count;
|
|
|
|
DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
|
|
|
|
hw->eeprom.ops.init_params(hw);
|
|
|
|
if (words == 0) {
|
|
status = IXGBE_ERR_INVALID_ARGUMENT;
|
|
goto out;
|
|
}
|
|
|
|
if (offset + words > hw->eeprom.word_size) {
|
|
status = IXGBE_ERR_EEPROM;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* We cannot hold synchronization semaphores for too long
|
|
* to avoid other entity starvation. However it is more efficient
|
|
* to read in bursts than synchronizing access for each word.
|
|
*/
|
|
for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
|
|
count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
|
|
IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
|
|
|
|
status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
|
|
count, &data[i]);
|
|
|
|
if (status != IXGBE_SUCCESS)
|
|
break;
|
|
}
|
|
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset within the EEPROM to be read
|
|
* @words: number of word(s)
|
|
* @data: read 16 bit word(s) from EEPROM
|
|
*
|
|
* Reads 16 bit word(s) from EEPROM through bit-bang method
|
|
**/
|
|
static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
|
|
u16 words, u16 *data)
|
|
{
|
|
s32 status;
|
|
u16 word_in;
|
|
u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
|
|
u16 i;
|
|
|
|
DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
|
|
|
|
/* Prepare the EEPROM for reading */
|
|
status = ixgbe_acquire_eeprom(hw);
|
|
|
|
if (status == IXGBE_SUCCESS) {
|
|
if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
|
|
ixgbe_release_eeprom(hw);
|
|
status = IXGBE_ERR_EEPROM;
|
|
}
|
|
}
|
|
|
|
if (status == IXGBE_SUCCESS) {
|
|
for (i = 0; i < words; i++) {
|
|
ixgbe_standby_eeprom(hw);
|
|
/*
|
|
* Some SPI eeproms use the 8th address bit embedded
|
|
* in the opcode
|
|
*/
|
|
if ((hw->eeprom.address_bits == 8) &&
|
|
((offset + i) >= 128))
|
|
read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
|
|
|
|
/* Send the READ command (opcode + addr) */
|
|
ixgbe_shift_out_eeprom_bits(hw, read_opcode,
|
|
IXGBE_EEPROM_OPCODE_BITS);
|
|
ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
|
|
hw->eeprom.address_bits);
|
|
|
|
/* Read the data. */
|
|
word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
|
|
data[i] = (word_in >> 8) | (word_in << 8);
|
|
}
|
|
|
|
/* End this read operation */
|
|
ixgbe_release_eeprom(hw);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset within the EEPROM to be read
|
|
* @data: read 16 bit value from EEPROM
|
|
*
|
|
* Reads 16 bit value from EEPROM through bit-bang method
|
|
**/
|
|
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
|
|
u16 *data)
|
|
{
|
|
s32 status;
|
|
|
|
DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
|
|
|
|
hw->eeprom.ops.init_params(hw);
|
|
|
|
if (offset >= hw->eeprom.word_size) {
|
|
status = IXGBE_ERR_EEPROM;
|
|
goto out;
|
|
}
|
|
|
|
status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
|
|
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset of word in the EEPROM to read
|
|
* @words: number of word(s)
|
|
* @data: 16 bit word(s) from the EEPROM
|
|
*
|
|
* Reads a 16 bit word(s) from the EEPROM using the EERD register.
|
|
**/
|
|
s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
|
|
u16 words, u16 *data)
|
|
{
|
|
u32 eerd;
|
|
s32 status = IXGBE_SUCCESS;
|
|
u32 i;
|
|
|
|
DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
|
|
|
|
hw->eeprom.ops.init_params(hw);
|
|
|
|
if (words == 0) {
|
|
status = IXGBE_ERR_INVALID_ARGUMENT;
|
|
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
|
|
goto out;
|
|
}
|
|
|
|
if (offset >= hw->eeprom.word_size) {
|
|
status = IXGBE_ERR_EEPROM;
|
|
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < words; i++) {
|
|
eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
|
|
IXGBE_EEPROM_RW_REG_START;
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
|
|
status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
|
|
|
|
if (status == IXGBE_SUCCESS) {
|
|
data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
|
|
IXGBE_EEPROM_RW_REG_DATA);
|
|
} else {
|
|
DEBUGOUT("Eeprom read timed out\n");
|
|
goto out;
|
|
}
|
|
}
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset within the EEPROM to be used as a scratch pad
|
|
*
|
|
* Discover EEPROM page size by writing marching data at given offset.
|
|
* This function is called only when we are writing a new large buffer
|
|
* at given offset so the data would be overwritten anyway.
|
|
**/
|
|
static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
|
|
u16 offset)
|
|
{
|
|
u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
|
|
s32 status = IXGBE_SUCCESS;
|
|
u16 i;
|
|
|
|
DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
|
|
|
|
for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
|
|
data[i] = i;
|
|
|
|
hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
|
|
status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
|
|
IXGBE_EEPROM_PAGE_SIZE_MAX, data);
|
|
hw->eeprom.word_page_size = 0;
|
|
if (status != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
|
|
if (status != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
/*
|
|
* When writing in burst more than the actual page size
|
|
* EEPROM address wraps around current page.
|
|
*/
|
|
hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
|
|
|
|
DEBUGOUT1("Detected EEPROM page size = %d words.",
|
|
hw->eeprom.word_page_size);
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_read_eerd_generic - Read EEPROM word using EERD
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset of word in the EEPROM to read
|
|
* @data: word read from the EEPROM
|
|
*
|
|
* Reads a 16 bit word from the EEPROM using the EERD register.
|
|
**/
|
|
s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
|
|
{
|
|
return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset of word in the EEPROM to write
|
|
* @words: number of word(s)
|
|
* @data: word(s) write to the EEPROM
|
|
*
|
|
* Write a 16 bit word(s) to the EEPROM using the EEWR register.
|
|
**/
|
|
s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
|
|
u16 words, u16 *data)
|
|
{
|
|
u32 eewr;
|
|
s32 status = IXGBE_SUCCESS;
|
|
u16 i;
|
|
|
|
DEBUGFUNC("ixgbe_write_eewr_generic");
|
|
|
|
hw->eeprom.ops.init_params(hw);
|
|
|
|
if (words == 0) {
|
|
status = IXGBE_ERR_INVALID_ARGUMENT;
|
|
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
|
|
goto out;
|
|
}
|
|
|
|
if (offset >= hw->eeprom.word_size) {
|
|
status = IXGBE_ERR_EEPROM;
|
|
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < words; i++) {
|
|
eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
|
|
(data[i] << IXGBE_EEPROM_RW_REG_DATA) |
|
|
IXGBE_EEPROM_RW_REG_START;
|
|
|
|
status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
|
|
if (status != IXGBE_SUCCESS) {
|
|
DEBUGOUT("Eeprom write EEWR timed out\n");
|
|
goto out;
|
|
}
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
|
|
|
|
status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
|
|
if (status != IXGBE_SUCCESS) {
|
|
DEBUGOUT("Eeprom write EEWR timed out\n");
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_write_eewr_generic - Write EEPROM word using EEWR
|
|
* @hw: pointer to hardware structure
|
|
* @offset: offset of word in the EEPROM to write
|
|
* @data: word write to the EEPROM
|
|
*
|
|
* Write a 16 bit word to the EEPROM using the EEWR register.
|
|
**/
|
|
s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
|
|
{
|
|
return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
|
|
* @hw: pointer to hardware structure
|
|
* @ee_reg: EEPROM flag for polling
|
|
*
|
|
* Polls the status bit (bit 1) of the EERD or EEWR to determine when the
|
|
* read or write is done respectively.
|
|
**/
|
|
s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
|
|
{
|
|
u32 i;
|
|
u32 reg;
|
|
s32 status = IXGBE_ERR_EEPROM;
|
|
|
|
DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
|
|
|
|
for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
|
|
if (ee_reg == IXGBE_NVM_POLL_READ)
|
|
reg = IXGBE_READ_REG(hw, IXGBE_EERD);
|
|
else
|
|
reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
|
|
|
|
if (reg & IXGBE_EEPROM_RW_REG_DONE) {
|
|
status = IXGBE_SUCCESS;
|
|
break;
|
|
}
|
|
usec_delay(5);
|
|
}
|
|
|
|
if (i == IXGBE_EERD_EEWR_ATTEMPTS)
|
|
ERROR_REPORT1(IXGBE_ERROR_POLLING,
|
|
"EEPROM read/write done polling timed out");
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Prepares EEPROM for access using bit-bang method. This function should
|
|
* be called before issuing a command to the EEPROM.
|
|
**/
|
|
static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
u32 eec;
|
|
u32 i;
|
|
|
|
DEBUGFUNC("ixgbe_acquire_eeprom");
|
|
|
|
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
|
|
!= IXGBE_SUCCESS)
|
|
status = IXGBE_ERR_SWFW_SYNC;
|
|
|
|
if (status == IXGBE_SUCCESS) {
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
|
|
/* Request EEPROM Access */
|
|
eec |= IXGBE_EEC_REQ;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
|
|
for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
if (eec & IXGBE_EEC_GNT)
|
|
break;
|
|
usec_delay(5);
|
|
}
|
|
|
|
/* Release if grant not acquired */
|
|
if (!(eec & IXGBE_EEC_GNT)) {
|
|
eec &= ~IXGBE_EEC_REQ;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
DEBUGOUT("Could not acquire EEPROM grant\n");
|
|
|
|
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
|
|
status = IXGBE_ERR_EEPROM;
|
|
}
|
|
|
|
/* Setup EEPROM for Read/Write */
|
|
if (status == IXGBE_SUCCESS) {
|
|
/* Clear CS and SK */
|
|
eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
usec_delay(1);
|
|
}
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_eeprom_semaphore - Get hardware semaphore
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Sets the hardware semaphores so EEPROM access can occur for bit-bang method
|
|
**/
|
|
static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status = IXGBE_ERR_EEPROM;
|
|
u32 timeout = 2000;
|
|
u32 i;
|
|
u32 swsm;
|
|
|
|
DEBUGFUNC("ixgbe_get_eeprom_semaphore");
|
|
|
|
|
|
/* Get SMBI software semaphore between device drivers first */
|
|
for (i = 0; i < timeout; i++) {
|
|
/*
|
|
* If the SMBI bit is 0 when we read it, then the bit will be
|
|
* set and we have the semaphore
|
|
*/
|
|
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
|
|
if (!(swsm & IXGBE_SWSM_SMBI)) {
|
|
status = IXGBE_SUCCESS;
|
|
break;
|
|
}
|
|
usec_delay(50);
|
|
}
|
|
|
|
if (i == timeout) {
|
|
DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
|
|
"not granted.\n");
|
|
/*
|
|
* this release is particularly important because our attempts
|
|
* above to get the semaphore may have succeeded, and if there
|
|
* was a timeout, we should unconditionally clear the semaphore
|
|
* bits to free the driver to make progress
|
|
*/
|
|
ixgbe_release_eeprom_semaphore(hw);
|
|
|
|
usec_delay(50);
|
|
/*
|
|
* one last try
|
|
* If the SMBI bit is 0 when we read it, then the bit will be
|
|
* set and we have the semaphore
|
|
*/
|
|
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
|
|
if (!(swsm & IXGBE_SWSM_SMBI))
|
|
status = IXGBE_SUCCESS;
|
|
}
|
|
|
|
/* Now get the semaphore between SW/FW through the SWESMBI bit */
|
|
if (status == IXGBE_SUCCESS) {
|
|
for (i = 0; i < timeout; i++) {
|
|
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
|
|
|
|
/* Set the SW EEPROM semaphore bit to request access */
|
|
swsm |= IXGBE_SWSM_SWESMBI;
|
|
IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
|
|
|
|
/*
|
|
* If we set the bit successfully then we got the
|
|
* semaphore.
|
|
*/
|
|
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
|
|
if (swsm & IXGBE_SWSM_SWESMBI)
|
|
break;
|
|
|
|
usec_delay(50);
|
|
}
|
|
|
|
/*
|
|
* Release semaphores and return error if SW EEPROM semaphore
|
|
* was not granted because we don't have access to the EEPROM
|
|
*/
|
|
if (i >= timeout) {
|
|
ERROR_REPORT1(IXGBE_ERROR_POLLING,
|
|
"SWESMBI Software EEPROM semaphore not granted.\n");
|
|
ixgbe_release_eeprom_semaphore(hw);
|
|
status = IXGBE_ERR_EEPROM;
|
|
}
|
|
} else {
|
|
ERROR_REPORT1(IXGBE_ERROR_POLLING,
|
|
"Software semaphore SMBI between device drivers "
|
|
"not granted.\n");
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_release_eeprom_semaphore - Release hardware semaphore
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* This function clears hardware semaphore bits.
|
|
**/
|
|
static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
|
|
{
|
|
u32 swsm;
|
|
|
|
DEBUGFUNC("ixgbe_release_eeprom_semaphore");
|
|
|
|
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
|
|
|
|
/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
|
|
swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
|
|
IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_ready_eeprom - Polls for EEPROM ready
|
|
* @hw: pointer to hardware structure
|
|
**/
|
|
static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
u16 i;
|
|
u8 spi_stat_reg;
|
|
|
|
DEBUGFUNC("ixgbe_ready_eeprom");
|
|
|
|
/*
|
|
* Read "Status Register" repeatedly until the LSB is cleared. The
|
|
* EEPROM will signal that the command has been completed by clearing
|
|
* bit 0 of the internal status register. If it's not cleared within
|
|
* 5 milliseconds, then error out.
|
|
*/
|
|
for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
|
|
ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
|
|
IXGBE_EEPROM_OPCODE_BITS);
|
|
spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
|
|
if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
|
|
break;
|
|
|
|
usec_delay(5);
|
|
ixgbe_standby_eeprom(hw);
|
|
}
|
|
|
|
/*
|
|
* On some parts, SPI write time could vary from 0-20mSec on 3.3V
|
|
* devices (and only 0-5mSec on 5V devices)
|
|
*/
|
|
if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
|
|
DEBUGOUT("SPI EEPROM Status error\n");
|
|
status = IXGBE_ERR_EEPROM;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
|
|
* @hw: pointer to hardware structure
|
|
**/
|
|
static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
|
|
{
|
|
u32 eec;
|
|
|
|
DEBUGFUNC("ixgbe_standby_eeprom");
|
|
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
|
|
/* Toggle CS to flush commands */
|
|
eec |= IXGBE_EEC_CS;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
usec_delay(1);
|
|
eec &= ~IXGBE_EEC_CS;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
usec_delay(1);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
|
|
* @hw: pointer to hardware structure
|
|
* @data: data to send to the EEPROM
|
|
* @count: number of bits to shift out
|
|
**/
|
|
static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
|
|
u16 count)
|
|
{
|
|
u32 eec;
|
|
u32 mask;
|
|
u32 i;
|
|
|
|
DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
|
|
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
|
|
/*
|
|
* Mask is used to shift "count" bits of "data" out to the EEPROM
|
|
* one bit at a time. Determine the starting bit based on count
|
|
*/
|
|
mask = 0x01 << (count - 1);
|
|
|
|
for (i = 0; i < count; i++) {
|
|
/*
|
|
* A "1" is shifted out to the EEPROM by setting bit "DI" to a
|
|
* "1", and then raising and then lowering the clock (the SK
|
|
* bit controls the clock input to the EEPROM). A "0" is
|
|
* shifted out to the EEPROM by setting "DI" to "0" and then
|
|
* raising and then lowering the clock.
|
|
*/
|
|
if (data & mask)
|
|
eec |= IXGBE_EEC_DI;
|
|
else
|
|
eec &= ~IXGBE_EEC_DI;
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
usec_delay(1);
|
|
|
|
ixgbe_raise_eeprom_clk(hw, &eec);
|
|
ixgbe_lower_eeprom_clk(hw, &eec);
|
|
|
|
/*
|
|
* Shift mask to signify next bit of data to shift in to the
|
|
* EEPROM
|
|
*/
|
|
mask = mask >> 1;
|
|
}
|
|
|
|
/* We leave the "DI" bit set to "0" when we leave this routine. */
|
|
eec &= ~IXGBE_EEC_DI;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @count: number of bits to shift
|
|
**/
|
|
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
|
|
{
|
|
u32 eec;
|
|
u32 i;
|
|
u16 data = 0;
|
|
|
|
DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
|
|
|
|
/*
|
|
* In order to read a register from the EEPROM, we need to shift
|
|
* 'count' bits in from the EEPROM. Bits are "shifted in" by raising
|
|
* the clock input to the EEPROM (setting the SK bit), and then reading
|
|
* the value of the "DO" bit. During this "shifting in" process the
|
|
* "DI" bit should always be clear.
|
|
*/
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
|
|
eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
|
|
|
|
for (i = 0; i < count; i++) {
|
|
data = data << 1;
|
|
ixgbe_raise_eeprom_clk(hw, &eec);
|
|
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
|
|
eec &= ~(IXGBE_EEC_DI);
|
|
if (eec & IXGBE_EEC_DO)
|
|
data |= 1;
|
|
|
|
ixgbe_lower_eeprom_clk(hw, &eec);
|
|
}
|
|
|
|
return data;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
|
|
* @hw: pointer to hardware structure
|
|
* @eec: EEC register's current value
|
|
**/
|
|
static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
|
|
{
|
|
DEBUGFUNC("ixgbe_raise_eeprom_clk");
|
|
|
|
/*
|
|
* Raise the clock input to the EEPROM
|
|
* (setting the SK bit), then delay
|
|
*/
|
|
*eec = *eec | IXGBE_EEC_SK;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
usec_delay(1);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
|
|
* @hw: pointer to hardware structure
|
|
* @eec: EEC's current value
|
|
**/
|
|
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
|
|
{
|
|
DEBUGFUNC("ixgbe_lower_eeprom_clk");
|
|
|
|
/*
|
|
* Lower the clock input to the EEPROM (clearing the SK bit), then
|
|
* delay
|
|
*/
|
|
*eec = *eec & ~IXGBE_EEC_SK;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
usec_delay(1);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_release_eeprom - Release EEPROM, release semaphores
|
|
* @hw: pointer to hardware structure
|
|
**/
|
|
static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
|
|
{
|
|
u32 eec;
|
|
|
|
DEBUGFUNC("ixgbe_release_eeprom");
|
|
|
|
eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
|
|
|
|
eec |= IXGBE_EEC_CS; /* Pull CS high */
|
|
eec &= ~IXGBE_EEC_SK; /* Lower SCK */
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
usec_delay(1);
|
|
|
|
/* Stop requesting EEPROM access */
|
|
eec &= ~IXGBE_EEC_REQ;
|
|
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
|
|
|
|
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
|
|
|
|
/* Delay before attempt to obtain semaphore again to allow FW access */
|
|
msec_delay(hw->eeprom.semaphore_delay);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Returns a negative error code on error, or the 16-bit checksum
|
|
**/
|
|
s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u16 i;
|
|
u16 j;
|
|
u16 checksum = 0;
|
|
u16 length = 0;
|
|
u16 pointer = 0;
|
|
u16 word = 0;
|
|
|
|
DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
|
|
|
|
/* Include 0x0-0x3F in the checksum */
|
|
for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
|
|
if (hw->eeprom.ops.read(hw, i, &word)) {
|
|
DEBUGOUT("EEPROM read failed\n");
|
|
return IXGBE_ERR_EEPROM;
|
|
}
|
|
checksum += word;
|
|
}
|
|
|
|
/* Include all data from pointers except for the fw pointer */
|
|
for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
|
|
if (hw->eeprom.ops.read(hw, i, &pointer)) {
|
|
DEBUGOUT("EEPROM read failed\n");
|
|
return IXGBE_ERR_EEPROM;
|
|
}
|
|
|
|
/* If the pointer seems invalid */
|
|
if (pointer == 0xFFFF || pointer == 0)
|
|
continue;
|
|
|
|
if (hw->eeprom.ops.read(hw, pointer, &length)) {
|
|
DEBUGOUT("EEPROM read failed\n");
|
|
return IXGBE_ERR_EEPROM;
|
|
}
|
|
|
|
if (length == 0xFFFF || length == 0)
|
|
continue;
|
|
|
|
for (j = pointer + 1; j <= pointer + length; j++) {
|
|
if (hw->eeprom.ops.read(hw, j, &word)) {
|
|
DEBUGOUT("EEPROM read failed\n");
|
|
return IXGBE_ERR_EEPROM;
|
|
}
|
|
checksum += word;
|
|
}
|
|
}
|
|
|
|
checksum = (u16)IXGBE_EEPROM_SUM - checksum;
|
|
|
|
return (s32)checksum;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
|
|
* @hw: pointer to hardware structure
|
|
* @checksum_val: calculated checksum
|
|
*
|
|
* Performs checksum calculation and validates the EEPROM checksum. If the
|
|
* caller does not need checksum_val, the value can be NULL.
|
|
**/
|
|
s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
|
|
u16 *checksum_val)
|
|
{
|
|
s32 status;
|
|
u16 checksum;
|
|
u16 read_checksum = 0;
|
|
|
|
DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
|
|
|
|
/* Read the first word from the EEPROM. If this times out or fails, do
|
|
* not continue or we could be in for a very long wait while every
|
|
* EEPROM read fails
|
|
*/
|
|
status = hw->eeprom.ops.read(hw, 0, &checksum);
|
|
if (status) {
|
|
DEBUGOUT("EEPROM read failed\n");
|
|
return status;
|
|
}
|
|
|
|
status = hw->eeprom.ops.calc_checksum(hw);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
checksum = (u16)(status & 0xffff);
|
|
|
|
status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
|
|
if (status) {
|
|
DEBUGOUT("EEPROM read failed\n");
|
|
return status;
|
|
}
|
|
|
|
/* Verify read checksum from EEPROM is the same as
|
|
* calculated checksum
|
|
*/
|
|
if (read_checksum != checksum)
|
|
status = IXGBE_ERR_EEPROM_CHECKSUM;
|
|
|
|
/* If the user cares, return the calculated checksum */
|
|
if (checksum_val)
|
|
*checksum_val = checksum;
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
|
|
* @hw: pointer to hardware structure
|
|
**/
|
|
s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status;
|
|
u16 checksum;
|
|
|
|
DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
|
|
|
|
/* Read the first word from the EEPROM. If this times out or fails, do
|
|
* not continue or we could be in for a very long wait while every
|
|
* EEPROM read fails
|
|
*/
|
|
status = hw->eeprom.ops.read(hw, 0, &checksum);
|
|
if (status) {
|
|
DEBUGOUT("EEPROM read failed\n");
|
|
return status;
|
|
}
|
|
|
|
status = hw->eeprom.ops.calc_checksum(hw);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
checksum = (u16)(status & 0xffff);
|
|
|
|
status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_validate_mac_addr - Validate MAC address
|
|
* @mac_addr: pointer to MAC address.
|
|
*
|
|
* Tests a MAC address to ensure it is a valid Individual Address.
|
|
**/
|
|
s32 ixgbe_validate_mac_addr(u8 *mac_addr)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
|
|
DEBUGFUNC("ixgbe_validate_mac_addr");
|
|
|
|
/* Make sure it is not a multicast address */
|
|
if (IXGBE_IS_MULTICAST(mac_addr)) {
|
|
status = IXGBE_ERR_INVALID_MAC_ADDR;
|
|
/* Not a broadcast address */
|
|
} else if (IXGBE_IS_BROADCAST(mac_addr)) {
|
|
status = IXGBE_ERR_INVALID_MAC_ADDR;
|
|
/* Reject the zero address */
|
|
} else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
|
|
mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
|
|
status = IXGBE_ERR_INVALID_MAC_ADDR;
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_rar_generic - Set Rx address register
|
|
* @hw: pointer to hardware structure
|
|
* @index: Receive address register to write
|
|
* @addr: Address to put into receive address register
|
|
* @vmdq: VMDq "set" or "pool" index
|
|
* @enable_addr: set flag that address is active
|
|
*
|
|
* Puts an ethernet address into a receive address register.
|
|
**/
|
|
s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
|
|
u32 enable_addr)
|
|
{
|
|
u32 rar_low, rar_high;
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
|
DEBUGFUNC("ixgbe_set_rar_generic");
|
|
|
|
/* Make sure we are using a valid rar index range */
|
|
if (index >= rar_entries) {
|
|
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
|
|
"RAR index %d is out of range.\n", index);
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
/* setup VMDq pool selection before this RAR gets enabled */
|
|
hw->mac.ops.set_vmdq(hw, index, vmdq);
|
|
|
|
/*
|
|
* HW expects these in little endian so we reverse the byte
|
|
* order from network order (big endian) to little endian
|
|
*/
|
|
rar_low = ((u32)addr[0] |
|
|
((u32)addr[1] << 8) |
|
|
((u32)addr[2] << 16) |
|
|
((u32)addr[3] << 24));
|
|
/*
|
|
* Some parts put the VMDq setting in the extra RAH bits,
|
|
* so save everything except the lower 16 bits that hold part
|
|
* of the address and the address valid bit.
|
|
*/
|
|
rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
|
|
rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
|
|
rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
|
|
|
|
if (enable_addr != 0)
|
|
rar_high |= IXGBE_RAH_AV;
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_clear_rar_generic - Remove Rx address register
|
|
* @hw: pointer to hardware structure
|
|
* @index: Receive address register to write
|
|
*
|
|
* Clears an ethernet address from a receive address register.
|
|
**/
|
|
s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
|
|
{
|
|
u32 rar_high;
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
|
DEBUGFUNC("ixgbe_clear_rar_generic");
|
|
|
|
/* Make sure we are using a valid rar index range */
|
|
if (index >= rar_entries) {
|
|
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
|
|
"RAR index %d is out of range.\n", index);
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
/*
|
|
* Some parts put the VMDq setting in the extra RAH bits,
|
|
* so save everything except the lower 16 bits that hold part
|
|
* of the address and the address valid bit.
|
|
*/
|
|
rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
|
|
rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
|
|
|
|
/* clear VMDq pool/queue selection for this RAR */
|
|
hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_init_rx_addrs_generic - Initializes receive address filters.
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Places the MAC address in receive address register 0 and clears the rest
|
|
* of the receive address registers. Clears the multicast table. Assumes
|
|
* the receiver is in reset when the routine is called.
|
|
**/
|
|
s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u32 i;
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
|
DEBUGFUNC("ixgbe_init_rx_addrs_generic");
|
|
|
|
/*
|
|
* If the current mac address is valid, assume it is a software override
|
|
* to the permanent address.
|
|
* Otherwise, use the permanent address from the eeprom.
|
|
*/
|
|
if (ixgbe_validate_mac_addr(hw->mac.addr) ==
|
|
IXGBE_ERR_INVALID_MAC_ADDR) {
|
|
/* Get the MAC address from the RAR0 for later reference */
|
|
hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
|
|
|
|
DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
|
|
hw->mac.addr[0], hw->mac.addr[1],
|
|
hw->mac.addr[2]);
|
|
DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
|
|
hw->mac.addr[4], hw->mac.addr[5]);
|
|
} else {
|
|
/* Setup the receive address. */
|
|
DEBUGOUT("Overriding MAC Address in RAR[0]\n");
|
|
DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
|
|
hw->mac.addr[0], hw->mac.addr[1],
|
|
hw->mac.addr[2]);
|
|
DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
|
|
hw->mac.addr[4], hw->mac.addr[5]);
|
|
|
|
hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
|
|
}
|
|
|
|
/* clear VMDq pool/queue selection for RAR 0 */
|
|
hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
|
|
|
|
hw->addr_ctrl.overflow_promisc = 0;
|
|
|
|
hw->addr_ctrl.rar_used_count = 1;
|
|
|
|
/* Zero out the other receive addresses. */
|
|
DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
|
|
for (i = 1; i < rar_entries; i++) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
|
|
}
|
|
|
|
/* Clear the MTA */
|
|
hw->addr_ctrl.mta_in_use = 0;
|
|
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
|
|
|
|
DEBUGOUT(" Clearing MTA\n");
|
|
for (i = 0; i < hw->mac.mcft_size; i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
|
|
|
|
ixgbe_init_uta_tables(hw);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_add_uc_addr - Adds a secondary unicast address.
|
|
* @hw: pointer to hardware structure
|
|
* @addr: new address
|
|
* @vmdq: VMDq "set" or "pool" index
|
|
*
|
|
* Adds it to unused receive address register or goes into promiscuous mode.
|
|
**/
|
|
void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
|
|
{
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
u32 rar;
|
|
|
|
DEBUGFUNC("ixgbe_add_uc_addr");
|
|
|
|
DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
|
|
addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
|
|
|
|
/*
|
|
* Place this address in the RAR if there is room,
|
|
* else put the controller into promiscuous mode
|
|
*/
|
|
if (hw->addr_ctrl.rar_used_count < rar_entries) {
|
|
rar = hw->addr_ctrl.rar_used_count;
|
|
hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
|
|
DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
|
|
hw->addr_ctrl.rar_used_count++;
|
|
} else {
|
|
hw->addr_ctrl.overflow_promisc++;
|
|
}
|
|
|
|
DEBUGOUT("ixgbe_add_uc_addr Complete\n");
|
|
}
|
|
|
|
/**
|
|
* ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
|
|
* @hw: pointer to hardware structure
|
|
* @addr_list: the list of new addresses
|
|
* @addr_count: number of addresses
|
|
* @next: iterator function to walk the address list
|
|
*
|
|
* The given list replaces any existing list. Clears the secondary addrs from
|
|
* receive address registers. Uses unused receive address registers for the
|
|
* first secondary addresses, and falls back to promiscuous mode as needed.
|
|
*
|
|
* Drivers using secondary unicast addresses must set user_set_promisc when
|
|
* manually putting the device into promiscuous mode.
|
|
**/
|
|
s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
|
|
u32 addr_count, ixgbe_mc_addr_itr next)
|
|
{
|
|
u8 *addr;
|
|
u32 i;
|
|
u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
|
|
u32 uc_addr_in_use;
|
|
u32 fctrl;
|
|
u32 vmdq;
|
|
|
|
DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
|
|
|
|
/*
|
|
* Clear accounting of old secondary address list,
|
|
* don't count RAR[0]
|
|
*/
|
|
uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
|
|
hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
|
|
hw->addr_ctrl.overflow_promisc = 0;
|
|
|
|
/* Zero out the other receive addresses */
|
|
DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
|
|
for (i = 0; i < uc_addr_in_use; i++) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
|
|
}
|
|
|
|
/* Add the new addresses */
|
|
for (i = 0; i < addr_count; i++) {
|
|
DEBUGOUT(" Adding the secondary addresses:\n");
|
|
addr = next(hw, &addr_list, &vmdq);
|
|
ixgbe_add_uc_addr(hw, addr, vmdq);
|
|
}
|
|
|
|
if (hw->addr_ctrl.overflow_promisc) {
|
|
/* enable promisc if not already in overflow or set by user */
|
|
if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
|
|
DEBUGOUT(" Entering address overflow promisc mode\n");
|
|
fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
|
|
fctrl |= IXGBE_FCTRL_UPE;
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
|
|
}
|
|
} else {
|
|
/* only disable if set by overflow, not by user */
|
|
if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
|
|
DEBUGOUT(" Leaving address overflow promisc mode\n");
|
|
fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
|
|
fctrl &= ~IXGBE_FCTRL_UPE;
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
|
|
}
|
|
}
|
|
|
|
DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_mta_vector - Determines bit-vector in multicast table to set
|
|
* @hw: pointer to hardware structure
|
|
* @mc_addr: the multicast address
|
|
*
|
|
* Extracts the 12 bits, from a multicast address, to determine which
|
|
* bit-vector to set in the multicast table. The hardware uses 12 bits, from
|
|
* incoming rx multicast addresses, to determine the bit-vector to check in
|
|
* the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
|
|
* by the MO field of the MCSTCTRL. The MO field is set during initialization
|
|
* to mc_filter_type.
|
|
**/
|
|
static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
|
|
{
|
|
u32 vector = 0;
|
|
|
|
DEBUGFUNC("ixgbe_mta_vector");
|
|
|
|
switch (hw->mac.mc_filter_type) {
|
|
case 0: /* use bits [47:36] of the address */
|
|
vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
|
|
break;
|
|
case 1: /* use bits [46:35] of the address */
|
|
vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
|
|
break;
|
|
case 2: /* use bits [45:34] of the address */
|
|
vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
|
|
break;
|
|
case 3: /* use bits [43:32] of the address */
|
|
vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
|
|
break;
|
|
default: /* Invalid mc_filter_type */
|
|
DEBUGOUT("MC filter type param set incorrectly\n");
|
|
ASSERT(0);
|
|
break;
|
|
}
|
|
|
|
/* vector can only be 12-bits or boundary will be exceeded */
|
|
vector &= 0xFFF;
|
|
return vector;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_mta - Set bit-vector in multicast table
|
|
* @hw: pointer to hardware structure
|
|
* @mc_addr: Multicast address
|
|
*
|
|
* Sets the bit-vector in the multicast table.
|
|
**/
|
|
void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
|
|
{
|
|
u32 vector;
|
|
u32 vector_bit;
|
|
u32 vector_reg;
|
|
|
|
DEBUGFUNC("ixgbe_set_mta");
|
|
|
|
hw->addr_ctrl.mta_in_use++;
|
|
|
|
vector = ixgbe_mta_vector(hw, mc_addr);
|
|
DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
|
|
|
|
/*
|
|
* The MTA is a register array of 128 32-bit registers. It is treated
|
|
* like an array of 4096 bits. We want to set bit
|
|
* BitArray[vector_value]. So we figure out what register the bit is
|
|
* in, read it, OR in the new bit, then write back the new value. The
|
|
* register is determined by the upper 7 bits of the vector value and
|
|
* the bit within that register are determined by the lower 5 bits of
|
|
* the value.
|
|
*/
|
|
vector_reg = (vector >> 5) & 0x7F;
|
|
vector_bit = vector & 0x1F;
|
|
hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
|
|
* @hw: pointer to hardware structure
|
|
* @mc_addr_list: the list of new multicast addresses
|
|
* @mc_addr_count: number of addresses
|
|
* @next: iterator function to walk the multicast address list
|
|
* @clear: flag, when set clears the table beforehand
|
|
*
|
|
* When the clear flag is set, the given list replaces any existing list.
|
|
* Hashes the given addresses into the multicast table.
|
|
**/
|
|
s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
|
|
u32 mc_addr_count, ixgbe_mc_addr_itr next,
|
|
bool clear)
|
|
{
|
|
u32 i;
|
|
u32 vmdq;
|
|
|
|
DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
|
|
|
|
/*
|
|
* Set the new number of MC addresses that we are being requested to
|
|
* use.
|
|
*/
|
|
hw->addr_ctrl.num_mc_addrs = mc_addr_count;
|
|
hw->addr_ctrl.mta_in_use = 0;
|
|
|
|
/* Clear mta_shadow */
|
|
if (clear) {
|
|
DEBUGOUT(" Clearing MTA\n");
|
|
memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
|
|
}
|
|
|
|
/* Update mta_shadow */
|
|
for (i = 0; i < mc_addr_count; i++) {
|
|
DEBUGOUT(" Adding the multicast addresses:\n");
|
|
ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
|
|
}
|
|
|
|
/* Enable mta */
|
|
for (i = 0; i < hw->mac.mcft_size; i++)
|
|
IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
|
|
hw->mac.mta_shadow[i]);
|
|
|
|
if (hw->addr_ctrl.mta_in_use > 0)
|
|
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
|
|
IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
|
|
|
|
DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_enable_mc_generic - Enable multicast address in RAR
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Enables multicast address in RAR and the use of the multicast hash table.
|
|
**/
|
|
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
|
|
{
|
|
struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
|
|
|
|
DEBUGFUNC("ixgbe_enable_mc_generic");
|
|
|
|
if (a->mta_in_use > 0)
|
|
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
|
|
hw->mac.mc_filter_type);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_disable_mc_generic - Disable multicast address in RAR
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Disables multicast address in RAR and the use of the multicast hash table.
|
|
**/
|
|
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
|
|
{
|
|
struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
|
|
|
|
DEBUGFUNC("ixgbe_disable_mc_generic");
|
|
|
|
if (a->mta_in_use > 0)
|
|
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_fc_enable_generic - Enable flow control
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Enable flow control according to the current settings.
|
|
**/
|
|
s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
|
|
{
|
|
s32 ret_val = IXGBE_SUCCESS;
|
|
u32 mflcn_reg, fccfg_reg;
|
|
u32 reg;
|
|
u32 fcrtl, fcrth;
|
|
int i;
|
|
|
|
DEBUGFUNC("ixgbe_fc_enable_generic");
|
|
|
|
/* Validate the water mark configuration */
|
|
if (!hw->fc.pause_time) {
|
|
ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
|
|
goto out;
|
|
}
|
|
|
|
/* Low water mark of zero causes XOFF floods */
|
|
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
|
|
if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
|
|
hw->fc.high_water[i]) {
|
|
if (!hw->fc.low_water[i] ||
|
|
hw->fc.low_water[i] >= hw->fc.high_water[i]) {
|
|
DEBUGOUT("Invalid water mark configuration\n");
|
|
ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
|
|
goto out;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Negotiate the fc mode to use */
|
|
hw->mac.ops.fc_autoneg(hw);
|
|
|
|
/* Disable any previous flow control settings */
|
|
mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
|
|
mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
|
|
|
|
fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
|
|
fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
|
|
|
|
/*
|
|
* The possible values of fc.current_mode are:
|
|
* 0: Flow control is completely disabled
|
|
* 1: Rx flow control is enabled (we can receive pause frames,
|
|
* but not send pause frames).
|
|
* 2: Tx flow control is enabled (we can send pause frames but
|
|
* we do not support receiving pause frames).
|
|
* 3: Both Rx and Tx flow control (symmetric) are enabled.
|
|
* other: Invalid.
|
|
*/
|
|
switch (hw->fc.current_mode) {
|
|
case ixgbe_fc_none:
|
|
/*
|
|
* Flow control is disabled by software override or autoneg.
|
|
* The code below will actually disable it in the HW.
|
|
*/
|
|
break;
|
|
case ixgbe_fc_rx_pause:
|
|
/*
|
|
* Rx Flow control is enabled and Tx Flow control is
|
|
* disabled by software override. Since there really
|
|
* isn't a way to advertise that we are capable of RX
|
|
* Pause ONLY, we will advertise that we support both
|
|
* symmetric and asymmetric Rx PAUSE. Later, we will
|
|
* disable the adapter's ability to send PAUSE frames.
|
|
*/
|
|
mflcn_reg |= IXGBE_MFLCN_RFCE;
|
|
break;
|
|
case ixgbe_fc_tx_pause:
|
|
/*
|
|
* Tx Flow control is enabled, and Rx Flow control is
|
|
* disabled by software override.
|
|
*/
|
|
fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
|
|
break;
|
|
case ixgbe_fc_full:
|
|
/* Flow control (both Rx and Tx) is enabled by SW override. */
|
|
mflcn_reg |= IXGBE_MFLCN_RFCE;
|
|
fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
|
|
break;
|
|
default:
|
|
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
|
|
"Flow control param set incorrectly\n");
|
|
ret_val = IXGBE_ERR_CONFIG;
|
|
goto out;
|
|
break;
|
|
}
|
|
|
|
/* Set 802.3x based flow control settings. */
|
|
mflcn_reg |= IXGBE_MFLCN_DPF;
|
|
IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
|
|
|
|
|
|
/* Set up and enable Rx high/low water mark thresholds, enable XON. */
|
|
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
|
|
if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
|
|
hw->fc.high_water[i]) {
|
|
fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
|
|
fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
|
|
} else {
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
|
|
/*
|
|
* In order to prevent Tx hangs when the internal Tx
|
|
* switch is enabled we must set the high water mark
|
|
* to the Rx packet buffer size - 24KB. This allows
|
|
* the Tx switch to function even under heavy Rx
|
|
* workloads.
|
|
*/
|
|
fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
|
|
}
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
|
|
}
|
|
|
|
/* Configure pause time (2 TCs per register) */
|
|
reg = hw->fc.pause_time * 0x00010001;
|
|
for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
|
|
|
|
/* Configure flow control refresh threshold value */
|
|
IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_negotiate_fc - Negotiate flow control
|
|
* @hw: pointer to hardware structure
|
|
* @adv_reg: flow control advertised settings
|
|
* @lp_reg: link partner's flow control settings
|
|
* @adv_sym: symmetric pause bit in advertisement
|
|
* @adv_asm: asymmetric pause bit in advertisement
|
|
* @lp_sym: symmetric pause bit in link partner advertisement
|
|
* @lp_asm: asymmetric pause bit in link partner advertisement
|
|
*
|
|
* Find the intersection between advertised settings and link partner's
|
|
* advertised settings
|
|
**/
|
|
s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
|
|
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
|
|
{
|
|
if ((!(adv_reg)) || (!(lp_reg))) {
|
|
ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
|
|
"Local or link partner's advertised flow control "
|
|
"settings are NULL. Local: %x, link partner: %x\n",
|
|
adv_reg, lp_reg);
|
|
return IXGBE_ERR_FC_NOT_NEGOTIATED;
|
|
}
|
|
|
|
if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
|
|
/*
|
|
* Now we need to check if the user selected Rx ONLY
|
|
* of pause frames. In this case, we had to advertise
|
|
* FULL flow control because we could not advertise RX
|
|
* ONLY. Hence, we must now check to see if we need to
|
|
* turn OFF the TRANSMISSION of PAUSE frames.
|
|
*/
|
|
if (hw->fc.requested_mode == ixgbe_fc_full) {
|
|
hw->fc.current_mode = ixgbe_fc_full;
|
|
DEBUGOUT("Flow Control = FULL.\n");
|
|
} else {
|
|
hw->fc.current_mode = ixgbe_fc_rx_pause;
|
|
DEBUGOUT("Flow Control=RX PAUSE frames only\n");
|
|
}
|
|
} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
|
|
(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
|
|
hw->fc.current_mode = ixgbe_fc_tx_pause;
|
|
DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
|
|
} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
|
|
!(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
|
|
hw->fc.current_mode = ixgbe_fc_rx_pause;
|
|
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
|
|
} else {
|
|
hw->fc.current_mode = ixgbe_fc_none;
|
|
DEBUGOUT("Flow Control = NONE.\n");
|
|
}
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Enable flow control according on 1 gig fiber.
|
|
**/
|
|
static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
|
|
{
|
|
u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
|
|
s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
|
|
|
|
/*
|
|
* On multispeed fiber at 1g, bail out if
|
|
* - link is up but AN did not complete, or if
|
|
* - link is up and AN completed but timed out
|
|
*/
|
|
|
|
linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
|
|
if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
|
|
(!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
|
|
DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
|
|
goto out;
|
|
}
|
|
|
|
pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
|
|
pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
|
|
|
|
ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
|
|
pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
|
|
IXGBE_PCS1GANA_ASM_PAUSE,
|
|
IXGBE_PCS1GANA_SYM_PAUSE,
|
|
IXGBE_PCS1GANA_ASM_PAUSE);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Enable flow control according to IEEE clause 37.
|
|
**/
|
|
static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
|
|
{
|
|
u32 links2, anlp1_reg, autoc_reg, links;
|
|
s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
|
|
|
|
/*
|
|
* On backplane, bail out if
|
|
* - backplane autoneg was not completed, or if
|
|
* - we are 82599 and link partner is not AN enabled
|
|
*/
|
|
links = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
|
|
DEBUGOUT("Auto-Negotiation did not complete\n");
|
|
goto out;
|
|
}
|
|
|
|
if (hw->mac.type == ixgbe_mac_82599EB) {
|
|
links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
|
|
if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
|
|
DEBUGOUT("Link partner is not AN enabled\n");
|
|
goto out;
|
|
}
|
|
}
|
|
/*
|
|
* Read the 10g AN autoc and LP ability registers and resolve
|
|
* local flow control settings accordingly
|
|
*/
|
|
autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
|
|
anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
|
|
|
|
ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
|
|
anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
|
|
IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Enable flow control according to IEEE clause 37.
|
|
**/
|
|
static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
|
|
{
|
|
u16 technology_ability_reg = 0;
|
|
u16 lp_technology_ability_reg = 0;
|
|
|
|
hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
|
|
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
|
|
&technology_ability_reg);
|
|
hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
|
|
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
|
|
&lp_technology_ability_reg);
|
|
|
|
return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
|
|
(u32)lp_technology_ability_reg,
|
|
IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
|
|
IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_fc_autoneg - Configure flow control
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Compares our advertised flow control capabilities to those advertised by
|
|
* our link partner, and determines the proper flow control mode to use.
|
|
**/
|
|
void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
|
|
{
|
|
s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
|
|
ixgbe_link_speed speed;
|
|
bool link_up;
|
|
|
|
DEBUGFUNC("ixgbe_fc_autoneg");
|
|
|
|
/*
|
|
* AN should have completed when the cable was plugged in.
|
|
* Look for reasons to bail out. Bail out if:
|
|
* - FC autoneg is disabled, or if
|
|
* - link is not up.
|
|
*/
|
|
if (hw->fc.disable_fc_autoneg) {
|
|
/* TODO: This should be just an informative log */
|
|
ERROR_REPORT1(IXGBE_ERROR_CAUTION,
|
|
"Flow control autoneg is disabled");
|
|
goto out;
|
|
}
|
|
|
|
hw->mac.ops.check_link(hw, &speed, &link_up, false);
|
|
if (!link_up) {
|
|
ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
|
|
goto out;
|
|
}
|
|
|
|
switch (hw->phy.media_type) {
|
|
/* Autoneg flow control on fiber adapters */
|
|
case ixgbe_media_type_fiber_fixed:
|
|
case ixgbe_media_type_fiber_qsfp:
|
|
case ixgbe_media_type_fiber:
|
|
if (speed == IXGBE_LINK_SPEED_1GB_FULL)
|
|
ret_val = ixgbe_fc_autoneg_fiber(hw);
|
|
break;
|
|
|
|
/* Autoneg flow control on backplane adapters */
|
|
case ixgbe_media_type_backplane:
|
|
ret_val = ixgbe_fc_autoneg_backplane(hw);
|
|
break;
|
|
|
|
/* Autoneg flow control on copper adapters */
|
|
case ixgbe_media_type_copper:
|
|
if (ixgbe_device_supports_autoneg_fc(hw))
|
|
ret_val = ixgbe_fc_autoneg_copper(hw);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
out:
|
|
if (ret_val == IXGBE_SUCCESS) {
|
|
hw->fc.fc_was_autonegged = true;
|
|
} else {
|
|
hw->fc.fc_was_autonegged = false;
|
|
hw->fc.current_mode = hw->fc.requested_mode;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* ixgbe_pcie_timeout_poll - Return number of times to poll for completion
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* System-wide timeout range is encoded in PCIe Device Control2 register.
|
|
*
|
|
* Add 10% to specified maximum and return the number of times to poll for
|
|
* completion timeout, in units of 100 microsec. Never return less than
|
|
* 800 = 80 millisec.
|
|
*/
|
|
static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
|
|
{
|
|
s16 devctl2;
|
|
u32 pollcnt;
|
|
|
|
devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
|
|
devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
|
|
|
|
switch (devctl2) {
|
|
case IXGBE_PCIDEVCTRL2_65_130ms:
|
|
pollcnt = 1300; /* 130 millisec */
|
|
break;
|
|
case IXGBE_PCIDEVCTRL2_260_520ms:
|
|
pollcnt = 5200; /* 520 millisec */
|
|
break;
|
|
case IXGBE_PCIDEVCTRL2_1_2s:
|
|
pollcnt = 20000; /* 2 sec */
|
|
break;
|
|
case IXGBE_PCIDEVCTRL2_4_8s:
|
|
pollcnt = 80000; /* 8 sec */
|
|
break;
|
|
case IXGBE_PCIDEVCTRL2_17_34s:
|
|
pollcnt = 34000; /* 34 sec */
|
|
break;
|
|
case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
|
|
case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
|
|
case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
|
|
case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
|
|
default:
|
|
pollcnt = 800; /* 80 millisec minimum */
|
|
break;
|
|
}
|
|
|
|
/* add 10% to spec maximum */
|
|
return (pollcnt * 11) / 10;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_disable_pcie_master - Disable PCI-express master access
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Disables PCI-Express master access and verifies there are no pending
|
|
* requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
|
|
* bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
|
|
* is returned signifying master requests disabled.
|
|
**/
|
|
s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
u32 i, poll;
|
|
u16 value;
|
|
|
|
DEBUGFUNC("ixgbe_disable_pcie_master");
|
|
|
|
/* Always set this bit to ensure any future transactions are blocked */
|
|
IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
|
|
|
|
/* Exit if master requests are blocked */
|
|
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
|
|
IXGBE_REMOVED(hw->hw_addr))
|
|
goto out;
|
|
|
|
/* Poll for master request bit to clear */
|
|
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
|
|
usec_delay(100);
|
|
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Two consecutive resets are required via CTRL.RST per datasheet
|
|
* 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
|
|
* of this need. The first reset prevents new master requests from
|
|
* being issued by our device. We then must wait 1usec or more for any
|
|
* remaining completions from the PCIe bus to trickle in, and then reset
|
|
* again to clear out any effects they may have had on our device.
|
|
*/
|
|
DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
|
|
hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
|
|
|
|
if (hw->mac.type >= ixgbe_mac_X550)
|
|
goto out;
|
|
|
|
/*
|
|
* Before proceeding, make sure that the PCIe block does not have
|
|
* transactions pending.
|
|
*/
|
|
poll = ixgbe_pcie_timeout_poll(hw);
|
|
for (i = 0; i < poll; i++) {
|
|
usec_delay(100);
|
|
value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
|
|
if (IXGBE_REMOVED(hw->hw_addr))
|
|
goto out;
|
|
if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
|
|
goto out;
|
|
}
|
|
|
|
ERROR_REPORT1(IXGBE_ERROR_POLLING,
|
|
"PCIe transaction pending bit also did not clear.\n");
|
|
status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
|
|
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
|
|
* @hw: pointer to hardware structure
|
|
* @mask: Mask to specify which semaphore to acquire
|
|
*
|
|
* Acquires the SWFW semaphore through the GSSR register for the specified
|
|
* function (CSR, PHY0, PHY1, EEPROM, Flash)
|
|
**/
|
|
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
|
|
{
|
|
u32 gssr = 0;
|
|
u32 swmask = mask;
|
|
u32 fwmask = mask << 5;
|
|
u32 timeout = 200;
|
|
u32 i;
|
|
|
|
DEBUGFUNC("ixgbe_acquire_swfw_sync");
|
|
|
|
for (i = 0; i < timeout; i++) {
|
|
/*
|
|
* SW NVM semaphore bit is used for access to all
|
|
* SW_FW_SYNC bits (not just NVM)
|
|
*/
|
|
if (ixgbe_get_eeprom_semaphore(hw))
|
|
return IXGBE_ERR_SWFW_SYNC;
|
|
|
|
gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
|
|
if (!(gssr & (fwmask | swmask))) {
|
|
gssr |= swmask;
|
|
IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
|
|
ixgbe_release_eeprom_semaphore(hw);
|
|
return IXGBE_SUCCESS;
|
|
} else {
|
|
/* Resource is currently in use by FW or SW */
|
|
ixgbe_release_eeprom_semaphore(hw);
|
|
msec_delay(5);
|
|
}
|
|
}
|
|
|
|
/* If time expired clear the bits holding the lock and retry */
|
|
if (gssr & (fwmask | swmask))
|
|
ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
|
|
|
|
msec_delay(5);
|
|
return IXGBE_ERR_SWFW_SYNC;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_release_swfw_sync - Release SWFW semaphore
|
|
* @hw: pointer to hardware structure
|
|
* @mask: Mask to specify which semaphore to release
|
|
*
|
|
* Releases the SWFW semaphore through the GSSR register for the specified
|
|
* function (CSR, PHY0, PHY1, EEPROM, Flash)
|
|
**/
|
|
void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
|
|
{
|
|
u32 gssr;
|
|
u32 swmask = mask;
|
|
|
|
DEBUGFUNC("ixgbe_release_swfw_sync");
|
|
|
|
ixgbe_get_eeprom_semaphore(hw);
|
|
|
|
gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
|
|
gssr &= ~swmask;
|
|
IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
|
|
|
|
ixgbe_release_eeprom_semaphore(hw);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_disable_sec_rx_path_generic - Stops the receive data path
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Stops the receive data path and waits for the HW to internally empty
|
|
* the Rx security block
|
|
**/
|
|
s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
|
|
{
|
|
#define IXGBE_MAX_SECRX_POLL 4000
|
|
|
|
int i;
|
|
int secrxreg;
|
|
|
|
DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
|
|
|
|
|
|
secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
|
|
secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
|
|
IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
|
|
for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
|
|
secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
|
|
if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
|
|
break;
|
|
else
|
|
/* Use interrupt-safe sleep just in case */
|
|
usec_delay(10);
|
|
}
|
|
|
|
/* For informational purposes only */
|
|
if (i >= IXGBE_MAX_SECRX_POLL)
|
|
DEBUGOUT("Rx unit being enabled before security "
|
|
"path fully disabled. Continuing with init.\n");
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
|
|
* @hw: pointer to hardware structure
|
|
* @locked: bool to indicate whether the SW/FW lock was taken
|
|
* @reg_val: Value we read from AUTOC
|
|
*
|
|
* The default case requires no protection so just to the register read.
|
|
*/
|
|
s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
|
|
{
|
|
*locked = false;
|
|
*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
|
|
* @hw: pointer to hardware structure
|
|
* @reg_val: value to write to AUTOC
|
|
* @locked: bool to indicate whether the SW/FW lock was already taken by
|
|
* previous read.
|
|
*
|
|
* The default case requires no protection so just to the register write.
|
|
*/
|
|
s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
|
|
{
|
|
UNREFERENCED_1PARAMETER(locked);
|
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_enable_sec_rx_path_generic - Enables the receive data path
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Enables the receive data path.
|
|
**/
|
|
s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u32 secrxreg;
|
|
|
|
DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
|
|
|
|
secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
|
|
secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
|
|
IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
|
|
* @hw: pointer to hardware structure
|
|
* @regval: register value to write to RXCTRL
|
|
*
|
|
* Enables the Rx DMA unit
|
|
**/
|
|
s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
|
|
{
|
|
DEBUGFUNC("ixgbe_enable_rx_dma_generic");
|
|
|
|
if (regval & IXGBE_RXCTRL_RXEN)
|
|
ixgbe_enable_rx(hw);
|
|
else
|
|
ixgbe_disable_rx(hw);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_blink_led_start_generic - Blink LED based on index.
|
|
* @hw: pointer to hardware structure
|
|
* @index: led number to blink
|
|
**/
|
|
s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
|
|
{
|
|
ixgbe_link_speed speed = 0;
|
|
bool link_up = 0;
|
|
u32 autoc_reg = 0;
|
|
u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
|
|
s32 ret_val = IXGBE_SUCCESS;
|
|
bool locked = false;
|
|
|
|
DEBUGFUNC("ixgbe_blink_led_start_generic");
|
|
|
|
if (index > 3)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
/*
|
|
* Link must be up to auto-blink the LEDs;
|
|
* Force it if link is down.
|
|
*/
|
|
hw->mac.ops.check_link(hw, &speed, &link_up, false);
|
|
|
|
if (!link_up) {
|
|
ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
|
|
if (ret_val != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
|
|
autoc_reg |= IXGBE_AUTOC_FLU;
|
|
|
|
ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
|
|
if (ret_val != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(10);
|
|
}
|
|
|
|
led_reg &= ~IXGBE_LED_MODE_MASK(index);
|
|
led_reg |= IXGBE_LED_BLINK(index);
|
|
IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
|
|
* @hw: pointer to hardware structure
|
|
* @index: led number to stop blinking
|
|
**/
|
|
s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
|
|
{
|
|
u32 autoc_reg = 0;
|
|
u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
|
|
s32 ret_val = IXGBE_SUCCESS;
|
|
bool locked = false;
|
|
|
|
DEBUGFUNC("ixgbe_blink_led_stop_generic");
|
|
|
|
if (index > 3)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
|
|
if (ret_val != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
autoc_reg &= ~IXGBE_AUTOC_FLU;
|
|
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
|
|
|
|
ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
|
|
if (ret_val != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
led_reg &= ~IXGBE_LED_MODE_MASK(index);
|
|
led_reg &= ~IXGBE_LED_BLINK(index);
|
|
led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
|
|
IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @san_mac_offset: SAN MAC address offset
|
|
*
|
|
* This function will read the EEPROM location for the SAN MAC address
|
|
* pointer, and returns the value at that location. This is used in both
|
|
* get and set mac_addr routines.
|
|
**/
|
|
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
|
|
u16 *san_mac_offset)
|
|
{
|
|
s32 ret_val;
|
|
|
|
DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
|
|
|
|
/*
|
|
* First read the EEPROM pointer to see if the MAC addresses are
|
|
* available.
|
|
*/
|
|
ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
|
|
san_mac_offset);
|
|
if (ret_val) {
|
|
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
|
|
"eeprom at offset %d failed",
|
|
IXGBE_SAN_MAC_ADDR_PTR);
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @san_mac_addr: SAN MAC address
|
|
*
|
|
* Reads the SAN MAC address from the EEPROM, if it's available. This is
|
|
* per-port, so set_lan_id() must be called before reading the addresses.
|
|
* set_lan_id() is called by identify_sfp(), but this cannot be relied
|
|
* upon for non-SFP connections, so we must call it here.
|
|
**/
|
|
s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
|
|
{
|
|
u16 san_mac_data, san_mac_offset;
|
|
u8 i;
|
|
s32 ret_val;
|
|
|
|
DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
|
|
|
|
/*
|
|
* First read the EEPROM pointer to see if the MAC addresses are
|
|
* available. If they're not, no point in calling set_lan_id() here.
|
|
*/
|
|
ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
|
|
if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
|
|
goto san_mac_addr_out;
|
|
|
|
/* make sure we know which port we need to program */
|
|
hw->mac.ops.set_lan_id(hw);
|
|
/* apply the port offset to the address offset */
|
|
(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
|
|
(san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
|
|
for (i = 0; i < 3; i++) {
|
|
ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
|
|
&san_mac_data);
|
|
if (ret_val) {
|
|
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
|
|
"eeprom read at offset %d failed",
|
|
san_mac_offset);
|
|
goto san_mac_addr_out;
|
|
}
|
|
san_mac_addr[i * 2] = (u8)(san_mac_data);
|
|
san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
|
|
san_mac_offset++;
|
|
}
|
|
return IXGBE_SUCCESS;
|
|
|
|
san_mac_addr_out:
|
|
/*
|
|
* No addresses available in this EEPROM. It's not an
|
|
* error though, so just wipe the local address and return.
|
|
*/
|
|
for (i = 0; i < 6; i++)
|
|
san_mac_addr[i] = 0xFF;
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @san_mac_addr: SAN MAC address
|
|
*
|
|
* Write a SAN MAC address to the EEPROM.
|
|
**/
|
|
s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
|
|
{
|
|
s32 ret_val;
|
|
u16 san_mac_data, san_mac_offset;
|
|
u8 i;
|
|
|
|
DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
|
|
|
|
/* Look for SAN mac address pointer. If not defined, return */
|
|
ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
|
|
if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
|
|
return IXGBE_ERR_NO_SAN_ADDR_PTR;
|
|
|
|
/* Make sure we know which port we need to write */
|
|
hw->mac.ops.set_lan_id(hw);
|
|
/* Apply the port offset to the address offset */
|
|
(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
|
|
(san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
|
|
san_mac_data |= (u16)(san_mac_addr[i * 2]);
|
|
hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
|
|
san_mac_offset++;
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Read PCIe configuration space, and get the MSI-X vector count from
|
|
* the capabilities table.
|
|
**/
|
|
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u16 msix_count = 1;
|
|
u16 max_msix_count;
|
|
u16 pcie_offset;
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
|
|
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
case ixgbe_mac_X550EM_a:
|
|
pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
|
|
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
|
|
break;
|
|
default:
|
|
return msix_count;
|
|
}
|
|
|
|
DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
|
|
msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
|
|
if (IXGBE_REMOVED(hw->hw_addr))
|
|
msix_count = 0;
|
|
msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
|
|
|
|
/* MSI-X count is zero-based in HW */
|
|
msix_count++;
|
|
|
|
if (msix_count > max_msix_count)
|
|
msix_count = max_msix_count;
|
|
|
|
return msix_count;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
|
|
* @hw: pointer to hardware structure
|
|
* @addr: Address to put into receive address register
|
|
* @vmdq: VMDq pool to assign
|
|
*
|
|
* Puts an ethernet address into a receive address register, or
|
|
* finds the rar that it is already in; adds to the pool list
|
|
**/
|
|
s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
|
|
{
|
|
static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
|
|
u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
|
|
u32 rar;
|
|
u32 rar_low, rar_high;
|
|
u32 addr_low, addr_high;
|
|
|
|
DEBUGFUNC("ixgbe_insert_mac_addr_generic");
|
|
|
|
/* swap bytes for HW little endian */
|
|
addr_low = addr[0] | (addr[1] << 8)
|
|
| (addr[2] << 16)
|
|
| (addr[3] << 24);
|
|
addr_high = addr[4] | (addr[5] << 8);
|
|
|
|
/*
|
|
* Either find the mac_id in rar or find the first empty space.
|
|
* rar_highwater points to just after the highest currently used
|
|
* rar in order to shorten the search. It grows when we add a new
|
|
* rar to the top.
|
|
*/
|
|
for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
|
|
rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
|
|
|
|
if (((IXGBE_RAH_AV & rar_high) == 0)
|
|
&& first_empty_rar == NO_EMPTY_RAR_FOUND) {
|
|
first_empty_rar = rar;
|
|
} else if ((rar_high & 0xFFFF) == addr_high) {
|
|
rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
|
|
if (rar_low == addr_low)
|
|
break; /* found it already in the rars */
|
|
}
|
|
}
|
|
|
|
if (rar < hw->mac.rar_highwater) {
|
|
/* already there so just add to the pool bits */
|
|
ixgbe_set_vmdq(hw, rar, vmdq);
|
|
} else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
|
|
/* stick it into first empty RAR slot we found */
|
|
rar = first_empty_rar;
|
|
ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
|
|
} else if (rar == hw->mac.rar_highwater) {
|
|
/* add it to the top of the list and inc the highwater mark */
|
|
ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
|
|
hw->mac.rar_highwater++;
|
|
} else if (rar >= hw->mac.num_rar_entries) {
|
|
return IXGBE_ERR_INVALID_MAC_ADDR;
|
|
}
|
|
|
|
/*
|
|
* If we found rar[0], make sure the default pool bit (we use pool 0)
|
|
* remains cleared to be sure default pool packets will get delivered
|
|
*/
|
|
if (rar == 0)
|
|
ixgbe_clear_vmdq(hw, rar, 0);
|
|
|
|
return rar;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
|
|
* @hw: pointer to hardware struct
|
|
* @rar: receive address register index to disassociate
|
|
* @vmdq: VMDq pool index to remove from the rar
|
|
**/
|
|
s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
|
|
{
|
|
u32 mpsar_lo, mpsar_hi;
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
|
DEBUGFUNC("ixgbe_clear_vmdq_generic");
|
|
|
|
/* Make sure we are using a valid rar index range */
|
|
if (rar >= rar_entries) {
|
|
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
|
|
"RAR index %d is out of range.\n", rar);
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
|
|
mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
|
|
|
|
if (IXGBE_REMOVED(hw->hw_addr))
|
|
goto done;
|
|
|
|
if (!mpsar_lo && !mpsar_hi)
|
|
goto done;
|
|
|
|
if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
|
|
if (mpsar_lo) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
|
|
mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
|
|
}
|
|
if (mpsar_hi) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
|
|
mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
|
|
}
|
|
} else if (vmdq < 32) {
|
|
mpsar_lo &= ~(1 << vmdq);
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
|
|
} else {
|
|
mpsar_hi &= ~(1 << (vmdq - 32));
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
|
|
}
|
|
|
|
/* was that the last pool using this rar? */
|
|
if (mpsar_lo == 0 && mpsar_hi == 0 &&
|
|
rar != 0 && rar != hw->mac.san_mac_rar_index)
|
|
hw->mac.ops.clear_rar(hw, rar);
|
|
done:
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
|
|
* @hw: pointer to hardware struct
|
|
* @rar: receive address register index to associate with a VMDq index
|
|
* @vmdq: VMDq pool index
|
|
**/
|
|
s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
|
|
{
|
|
u32 mpsar;
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
|
DEBUGFUNC("ixgbe_set_vmdq_generic");
|
|
|
|
/* Make sure we are using a valid rar index range */
|
|
if (rar >= rar_entries) {
|
|
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
|
|
"RAR index %d is out of range.\n", rar);
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (vmdq < 32) {
|
|
mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
|
|
mpsar |= 1 << vmdq;
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
|
|
} else {
|
|
mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
|
|
mpsar |= 1 << (vmdq - 32);
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
|
|
}
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* This function should only be involved in the IOV mode.
|
|
* In IOV mode, Default pool is next pool after the number of
|
|
* VFs advertized and not 0.
|
|
* MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
|
|
*
|
|
* ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
|
|
* @hw: pointer to hardware struct
|
|
* @vmdq: VMDq pool index
|
|
**/
|
|
s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
|
|
{
|
|
u32 rar = hw->mac.san_mac_rar_index;
|
|
|
|
DEBUGFUNC("ixgbe_set_vmdq_san_mac");
|
|
|
|
if (vmdq < 32) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
|
|
} else {
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
|
|
* @hw: pointer to hardware structure
|
|
**/
|
|
s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
|
|
{
|
|
int i;
|
|
|
|
DEBUGFUNC("ixgbe_init_uta_tables_generic");
|
|
DEBUGOUT(" Clearing UTA\n");
|
|
|
|
for (i = 0; i < 128; i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
|
|
* @hw: pointer to hardware structure
|
|
* @vlan: VLAN id to write to VLAN filter
|
|
* @vlvf_bypass: true to find vlanid only, false returns first empty slot if
|
|
* vlanid not found
|
|
*
|
|
*
|
|
* return the VLVF index where this VLAN id should be placed
|
|
*
|
|
**/
|
|
s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
|
|
{
|
|
s32 regindex, first_empty_slot;
|
|
u32 bits;
|
|
|
|
/* short cut the special case */
|
|
if (vlan == 0)
|
|
return 0;
|
|
|
|
/* if vlvf_bypass is set we don't want to use an empty slot, we
|
|
* will simply bypass the VLVF if there are no entries present in the
|
|
* VLVF that contain our VLAN
|
|
*/
|
|
first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
|
|
|
|
/* add VLAN enable bit for comparison */
|
|
vlan |= IXGBE_VLVF_VIEN;
|
|
|
|
/* Search for the vlan id in the VLVF entries. Save off the first empty
|
|
* slot found along the way.
|
|
*
|
|
* pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
|
|
*/
|
|
for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
|
|
bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
|
|
if (bits == vlan)
|
|
return regindex;
|
|
if (!first_empty_slot && !bits)
|
|
first_empty_slot = regindex;
|
|
}
|
|
|
|
/* If we are here then we didn't find the VLAN. Return first empty
|
|
* slot we found during our search, else error.
|
|
*/
|
|
if (!first_empty_slot)
|
|
ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
|
|
|
|
return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_vfta_generic - Set VLAN filter table
|
|
* @hw: pointer to hardware structure
|
|
* @vlan: VLAN id to write to VLAN filter
|
|
* @vind: VMDq output index that maps queue to VLAN id in VLVFB
|
|
* @vlan_on: boolean flag to turn on/off VLAN
|
|
* @vlvf_bypass: boolean flag indicating updating default pool is okay
|
|
*
|
|
* Turn on/off specified VLAN in the VLAN filter table.
|
|
**/
|
|
s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
|
|
bool vlan_on, bool vlvf_bypass)
|
|
{
|
|
u32 regidx, vfta_delta, vfta;
|
|
s32 ret_val;
|
|
|
|
DEBUGFUNC("ixgbe_set_vfta_generic");
|
|
|
|
if (vlan > 4095 || vind > 63)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
/*
|
|
* this is a 2 part operation - first the VFTA, then the
|
|
* VLVF and VLVFB if VT Mode is set
|
|
* We don't write the VFTA until we know the VLVF part succeeded.
|
|
*/
|
|
|
|
/* Part 1
|
|
* The VFTA is a bitstring made up of 128 32-bit registers
|
|
* that enable the particular VLAN id, much like the MTA:
|
|
* bits[11-5]: which register
|
|
* bits[4-0]: which bit in the register
|
|
*/
|
|
regidx = vlan / 32;
|
|
vfta_delta = 1 << (vlan % 32);
|
|
vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
|
|
|
|
/*
|
|
* vfta_delta represents the difference between the current value
|
|
* of vfta and the value we want in the register. Since the diff
|
|
* is an XOR mask we can just update the vfta using an XOR
|
|
*/
|
|
vfta_delta &= vlan_on ? ~vfta : vfta;
|
|
vfta ^= vfta_delta;
|
|
|
|
/* Part 2
|
|
* Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
|
|
*/
|
|
ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
|
|
vfta, vlvf_bypass);
|
|
if (ret_val != IXGBE_SUCCESS) {
|
|
if (vlvf_bypass)
|
|
goto vfta_update;
|
|
return ret_val;
|
|
}
|
|
|
|
vfta_update:
|
|
/* Update VFTA now that we are ready for traffic */
|
|
if (vfta_delta)
|
|
IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_vlvf_generic - Set VLAN Pool Filter
|
|
* @hw: pointer to hardware structure
|
|
* @vlan: VLAN id to write to VLAN filter
|
|
* @vind: VMDq output index that maps queue to VLAN id in VLVFB
|
|
* @vlan_on: boolean flag to turn on/off VLAN in VLVF
|
|
* @vfta_delta: pointer to the difference between the current value of VFTA
|
|
* and the desired value
|
|
* @vfta: the desired value of the VFTA
|
|
* @vlvf_bypass: boolean flag indicating updating default pool is okay
|
|
*
|
|
* Turn on/off specified bit in VLVF table.
|
|
**/
|
|
s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
|
|
bool vlan_on, u32 *vfta_delta, u32 vfta,
|
|
bool vlvf_bypass)
|
|
{
|
|
u32 bits;
|
|
s32 vlvf_index;
|
|
|
|
DEBUGFUNC("ixgbe_set_vlvf_generic");
|
|
|
|
if (vlan > 4095 || vind > 63)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
/* If VT Mode is set
|
|
* Either vlan_on
|
|
* make sure the vlan is in VLVF
|
|
* set the vind bit in the matching VLVFB
|
|
* Or !vlan_on
|
|
* clear the pool bit and possibly the vind
|
|
*/
|
|
if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
|
|
return IXGBE_SUCCESS;
|
|
|
|
vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
|
|
if (vlvf_index < 0)
|
|
return vlvf_index;
|
|
|
|
bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
|
|
|
|
/* set the pool bit */
|
|
bits |= 1 << (vind % 32);
|
|
if (vlan_on)
|
|
goto vlvf_update;
|
|
|
|
/* clear the pool bit */
|
|
bits ^= 1 << (vind % 32);
|
|
|
|
if (!bits &&
|
|
!IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
|
|
/* Clear VFTA first, then disable VLVF. Otherwise
|
|
* we run the risk of stray packets leaking into
|
|
* the PF via the default pool
|
|
*/
|
|
if (*vfta_delta)
|
|
IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
|
|
|
|
/* disable VLVF and clear remaining bit from pool */
|
|
IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/* If there are still bits set in the VLVFB registers
|
|
* for the VLAN ID indicated we need to see if the
|
|
* caller is requesting that we clear the VFTA entry bit.
|
|
* If the caller has requested that we clear the VFTA
|
|
* entry bit but there are still pools/VFs using this VLAN
|
|
* ID entry then ignore the request. We're not worried
|
|
* about the case where we're turning the VFTA VLAN ID
|
|
* entry bit on, only when requested to turn it off as
|
|
* there may be multiple pools and/or VFs using the
|
|
* VLAN ID entry. In that case we cannot clear the
|
|
* VFTA bit until all pools/VFs using that VLAN ID have also
|
|
* been cleared. This will be indicated by "bits" being
|
|
* zero.
|
|
*/
|
|
*vfta_delta = 0;
|
|
|
|
vlvf_update:
|
|
/* record pool change and enable VLAN ID if not already enabled */
|
|
IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
|
|
IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_clear_vfta_generic - Clear VLAN filter table
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Clears the VLAN filter table, and the VMDq index associated with the filter
|
|
**/
|
|
s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u32 offset;
|
|
|
|
DEBUGFUNC("ixgbe_clear_vfta_generic");
|
|
|
|
for (offset = 0; offset < hw->mac.vft_size; offset++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
|
|
|
|
for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Contains the logic to identify if we need to verify link for the
|
|
* crosstalk fix
|
|
**/
|
|
static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
|
|
{
|
|
|
|
/* Does FW say we need the fix */
|
|
if (!hw->need_crosstalk_fix)
|
|
return false;
|
|
|
|
/* Only consider SFP+ PHYs i.e. media type fiber */
|
|
switch (hw->mac.ops.get_media_type(hw)) {
|
|
case ixgbe_media_type_fiber:
|
|
case ixgbe_media_type_fiber_qsfp:
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_check_mac_link_generic - Determine link and speed status
|
|
* @hw: pointer to hardware structure
|
|
* @speed: pointer to link speed
|
|
* @link_up: true when link is up
|
|
* @link_up_wait_to_complete: bool used to wait for link up or not
|
|
*
|
|
* Reads the links register to determine if link is up and the current speed
|
|
**/
|
|
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
|
bool *link_up, bool link_up_wait_to_complete)
|
|
{
|
|
u32 links_reg, links_orig;
|
|
u32 i;
|
|
|
|
DEBUGFUNC("ixgbe_check_mac_link_generic");
|
|
|
|
/* If Crosstalk fix enabled do the sanity check of making sure
|
|
* the SFP+ cage is full.
|
|
*/
|
|
if (ixgbe_need_crosstalk_fix(hw)) {
|
|
u32 sfp_cage_full;
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82599EB:
|
|
sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
|
|
IXGBE_ESDP_SDP2;
|
|
break;
|
|
case ixgbe_mac_X550EM_x:
|
|
case ixgbe_mac_X550EM_a:
|
|
sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
|
|
IXGBE_ESDP_SDP0;
|
|
break;
|
|
default:
|
|
/* sanity check - No SFP+ devices here */
|
|
sfp_cage_full = false;
|
|
break;
|
|
}
|
|
|
|
if (!sfp_cage_full) {
|
|
*link_up = false;
|
|
*speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
}
|
|
|
|
/* clear the old state */
|
|
links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
|
|
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
|
|
if (links_orig != links_reg) {
|
|
DEBUGOUT2("LINKS changed from %08X to %08X\n",
|
|
links_orig, links_reg);
|
|
}
|
|
|
|
if (link_up_wait_to_complete) {
|
|
for (i = 0; i < hw->mac.max_link_up_time; i++) {
|
|
if (links_reg & IXGBE_LINKS_UP) {
|
|
*link_up = true;
|
|
break;
|
|
} else {
|
|
*link_up = false;
|
|
}
|
|
msec_delay(100);
|
|
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
}
|
|
} else {
|
|
if (links_reg & IXGBE_LINKS_UP) {
|
|
if (ixgbe_need_crosstalk_fix(hw)) {
|
|
/* Check the link state again after a delay
|
|
* to filter out spurious link up
|
|
* notifications.
|
|
*/
|
|
msec_delay(5);
|
|
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
if (!(links_reg & IXGBE_LINKS_UP)) {
|
|
*link_up = false;
|
|
*speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
}
|
|
*link_up = true;
|
|
} else {
|
|
*link_up = false;
|
|
}
|
|
}
|
|
|
|
switch (links_reg & IXGBE_LINKS_SPEED_82599) {
|
|
case IXGBE_LINKS_SPEED_10G_82599:
|
|
*speed = IXGBE_LINK_SPEED_10GB_FULL;
|
|
if (hw->mac.type >= ixgbe_mac_X550) {
|
|
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
|
|
*speed = IXGBE_LINK_SPEED_2_5GB_FULL;
|
|
}
|
|
break;
|
|
case IXGBE_LINKS_SPEED_1G_82599:
|
|
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
|
break;
|
|
case IXGBE_LINKS_SPEED_100_82599:
|
|
*speed = IXGBE_LINK_SPEED_100_FULL;
|
|
if (hw->mac.type == ixgbe_mac_X550) {
|
|
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
|
|
*speed = IXGBE_LINK_SPEED_5GB_FULL;
|
|
}
|
|
break;
|
|
case IXGBE_LINKS_SPEED_10_X550EM_A:
|
|
*speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
|
|
hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
|
|
*speed = IXGBE_LINK_SPEED_10_FULL;
|
|
break;
|
|
default:
|
|
*speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
|
|
* the EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @wwnn_prefix: the alternative WWNN prefix
|
|
* @wwpn_prefix: the alternative WWPN prefix
|
|
*
|
|
* This function will read the EEPROM from the alternative SAN MAC address
|
|
* block to check the support for the alternative WWNN/WWPN prefix support.
|
|
**/
|
|
s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
|
|
u16 *wwpn_prefix)
|
|
{
|
|
u16 offset, caps;
|
|
u16 alt_san_mac_blk_offset;
|
|
|
|
DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
|
|
|
|
/* clear output first */
|
|
*wwnn_prefix = 0xFFFF;
|
|
*wwpn_prefix = 0xFFFF;
|
|
|
|
/* check if alternative SAN MAC is supported */
|
|
offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
|
|
if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
|
|
goto wwn_prefix_err;
|
|
|
|
if ((alt_san_mac_blk_offset == 0) ||
|
|
(alt_san_mac_blk_offset == 0xFFFF))
|
|
goto wwn_prefix_out;
|
|
|
|
/* check capability in alternative san mac address block */
|
|
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
|
|
if (hw->eeprom.ops.read(hw, offset, &caps))
|
|
goto wwn_prefix_err;
|
|
if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
|
|
goto wwn_prefix_out;
|
|
|
|
/* get the corresponding prefix for WWNN/WWPN */
|
|
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
|
|
if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
|
|
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
|
|
"eeprom read at offset %d failed", offset);
|
|
}
|
|
|
|
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
|
|
if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
|
|
goto wwn_prefix_err;
|
|
|
|
wwn_prefix_out:
|
|
return IXGBE_SUCCESS;
|
|
|
|
wwn_prefix_err:
|
|
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
|
|
"eeprom read at offset %d failed", offset);
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
|
|
* @hw: pointer to hardware structure
|
|
* @bs: the fcoe boot status
|
|
*
|
|
* This function will read the FCOE boot status from the iSCSI FCOE block
|
|
**/
|
|
s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
|
|
{
|
|
u16 offset, caps, flags;
|
|
s32 status;
|
|
|
|
DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
|
|
|
|
/* clear output first */
|
|
*bs = ixgbe_fcoe_bootstatus_unavailable;
|
|
|
|
/* check if FCOE IBA block is present */
|
|
offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
|
|
status = hw->eeprom.ops.read(hw, offset, &caps);
|
|
if (status != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
|
|
goto out;
|
|
|
|
/* check if iSCSI FCOE block is populated */
|
|
status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
|
|
if (status != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
if ((offset == 0) || (offset == 0xFFFF))
|
|
goto out;
|
|
|
|
/* read fcoe flags in iSCSI FCOE block */
|
|
offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
|
|
status = hw->eeprom.ops.read(hw, offset, &flags);
|
|
if (status != IXGBE_SUCCESS)
|
|
goto out;
|
|
|
|
if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
|
|
*bs = ixgbe_fcoe_bootstatus_enabled;
|
|
else
|
|
*bs = ixgbe_fcoe_bootstatus_disabled;
|
|
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
|
|
* @hw: pointer to hardware structure
|
|
* @enable: enable or disable switch for MAC anti-spoofing
|
|
* @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
|
|
*
|
|
**/
|
|
void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
|
|
{
|
|
int vf_target_reg = vf >> 3;
|
|
int vf_target_shift = vf % 8;
|
|
u32 pfvfspoof;
|
|
|
|
if (hw->mac.type == ixgbe_mac_82598EB)
|
|
return;
|
|
|
|
pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
|
|
if (enable)
|
|
pfvfspoof |= (1 << vf_target_shift);
|
|
else
|
|
pfvfspoof &= ~(1 << vf_target_shift);
|
|
IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
|
|
* @hw: pointer to hardware structure
|
|
* @enable: enable or disable switch for VLAN anti-spoofing
|
|
* @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
|
|
*
|
|
**/
|
|
void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
|
|
{
|
|
int vf_target_reg = vf >> 3;
|
|
int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
|
|
u32 pfvfspoof;
|
|
|
|
if (hw->mac.type == ixgbe_mac_82598EB)
|
|
return;
|
|
|
|
pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
|
|
if (enable)
|
|
pfvfspoof |= (1 << vf_target_shift);
|
|
else
|
|
pfvfspoof &= ~(1 << vf_target_shift);
|
|
IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_device_caps_generic - Get additional device capabilities
|
|
* @hw: pointer to hardware structure
|
|
* @device_caps: the EEPROM word with the extra device capabilities
|
|
*
|
|
* This function will read the EEPROM location for the device capabilities,
|
|
* and return the word through device_caps.
|
|
**/
|
|
s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
|
|
{
|
|
DEBUGFUNC("ixgbe_get_device_caps_generic");
|
|
|
|
hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
**/
|
|
void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
|
|
{
|
|
u32 regval;
|
|
u32 i;
|
|
|
|
DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
|
|
|
|
/* Enable relaxed ordering */
|
|
for (i = 0; i < hw->mac.max_tx_queues; i++) {
|
|
regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
|
|
regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
|
|
IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
|
|
}
|
|
|
|
for (i = 0; i < hw->mac.max_rx_queues; i++) {
|
|
regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
|
|
regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
|
|
IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
|
|
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* ixgbe_calculate_checksum - Calculate checksum for buffer
|
|
* @buffer: pointer to EEPROM
|
|
* @length: size of EEPROM to calculate a checksum for
|
|
* Calculates the checksum for some buffer on a specified length. The
|
|
* checksum calculated is returned.
|
|
**/
|
|
u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
|
|
{
|
|
u32 i;
|
|
u8 sum = 0;
|
|
|
|
DEBUGFUNC("ixgbe_calculate_checksum");
|
|
|
|
if (!buffer)
|
|
return 0;
|
|
|
|
for (i = 0; i < length; i++)
|
|
sum += buffer[i];
|
|
|
|
return (u8) (0 - sum);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_hic_unlocked - Issue command to manageability block unlocked
|
|
* @hw: pointer to the HW structure
|
|
* @buffer: command to write and where the return status will be placed
|
|
* @length: length of buffer, must be multiple of 4 bytes
|
|
* @timeout: time in ms to wait for command completion
|
|
*
|
|
* Communicates with the manageability block. On success return IXGBE_SUCCESS
|
|
* else returns semaphore error when encountering an error acquiring
|
|
* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
|
|
*
|
|
* This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
|
|
* by the caller.
|
|
**/
|
|
s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
|
|
u32 timeout)
|
|
{
|
|
u32 hicr, i, fwsts;
|
|
u16 dword_len;
|
|
|
|
DEBUGFUNC("ixgbe_hic_unlocked");
|
|
|
|
if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
|
|
DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
|
|
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
|
|
}
|
|
|
|
/* Set bit 9 of FWSTS clearing FW reset indication */
|
|
fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
|
|
IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
|
|
|
|
/* Check that the host interface is enabled. */
|
|
hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
|
|
if (!(hicr & IXGBE_HICR_EN)) {
|
|
DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
|
|
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
|
|
}
|
|
|
|
/* Calculate length in DWORDs. We must be DWORD aligned */
|
|
if (length % sizeof(u32)) {
|
|
DEBUGOUT("Buffer length failure, not aligned to dword");
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
dword_len = length >> 2;
|
|
|
|
/* The device driver writes the relevant command block
|
|
* into the ram area.
|
|
*/
|
|
for (i = 0; i < dword_len; i++)
|
|
IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
|
|
i, IXGBE_CPU_TO_LE32(buffer[i]));
|
|
|
|
/* Setting this bit tells the ARC that a new command is pending. */
|
|
IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
|
|
|
|
for (i = 0; i < timeout; i++) {
|
|
hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
|
|
if (!(hicr & IXGBE_HICR_C))
|
|
break;
|
|
msec_delay(1);
|
|
}
|
|
|
|
/* For each command except "Apply Update" perform
|
|
* status checks in the HICR registry.
|
|
*/
|
|
if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) ==
|
|
IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD)
|
|
return IXGBE_SUCCESS;
|
|
|
|
/* Check command completion */
|
|
if ((timeout && i == timeout) ||
|
|
!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
|
|
ERROR_REPORT1(IXGBE_ERROR_CAUTION,
|
|
"Command has failed with no status valid.\n");
|
|
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_host_interface_command - Issue command to manageability block
|
|
* @hw: pointer to the HW structure
|
|
* @buffer: contains the command to write and where the return status will
|
|
* be placed
|
|
* @length: length of buffer, must be multiple of 4 bytes
|
|
* @timeout: time in ms to wait for command completion
|
|
* @return_data: read and return data from the buffer (true) or not (false)
|
|
* Needed because FW structures are big endian and decoding of
|
|
* these fields can be 8 bit or 16 bit based on command. Decoding
|
|
* is not easily understood without making a table of commands.
|
|
* So we will leave this up to the caller to read back the data
|
|
* in these cases.
|
|
*
|
|
* Communicates with the manageability block. On success return IXGBE_SUCCESS
|
|
* else returns semaphore error when encountering an error acquiring
|
|
* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
|
|
**/
|
|
s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
|
|
u32 length, u32 timeout, bool return_data)
|
|
{
|
|
u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
|
|
struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
|
|
u16 buf_len;
|
|
s32 status;
|
|
u32 bi;
|
|
u32 dword_len;
|
|
|
|
DEBUGFUNC("ixgbe_host_interface_command");
|
|
|
|
if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
|
|
DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
|
|
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
|
|
}
|
|
|
|
/* Take management host interface semaphore */
|
|
status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
|
|
if (status)
|
|
return status;
|
|
|
|
status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
|
|
if (status)
|
|
goto rel_out;
|
|
|
|
if (!return_data)
|
|
goto rel_out;
|
|
|
|
/* Calculate length in DWORDs */
|
|
dword_len = hdr_size >> 2;
|
|
|
|
/* first pull in the header so we know the buffer length */
|
|
for (bi = 0; bi < dword_len; bi++) {
|
|
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
|
|
IXGBE_LE32_TO_CPUS(&buffer[bi]);
|
|
}
|
|
|
|
/*
|
|
* If there is any thing in data position pull it in
|
|
* Read Flash command requires reading buffer length from
|
|
* two byes instead of one byte
|
|
*/
|
|
if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
|
|
resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
|
|
for (; bi < dword_len + 2; bi++) {
|
|
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
|
|
bi);
|
|
IXGBE_LE32_TO_CPUS(&buffer[bi]);
|
|
}
|
|
buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
|
|
& 0xF00) | resp->buf_len;
|
|
hdr_size += (2 << 2);
|
|
} else {
|
|
buf_len = resp->buf_len;
|
|
}
|
|
if (!buf_len)
|
|
goto rel_out;
|
|
|
|
if (length < buf_len + hdr_size) {
|
|
DEBUGOUT("Buffer not large enough for reply message.\n");
|
|
status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
|
|
goto rel_out;
|
|
}
|
|
|
|
/* Calculate length in DWORDs, add 3 for odd lengths */
|
|
dword_len = (buf_len + 3) >> 2;
|
|
|
|
/* Pull in the rest of the buffer (bi is where we left off) */
|
|
for (; bi <= dword_len; bi++) {
|
|
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
|
|
IXGBE_LE32_TO_CPUS(&buffer[bi]);
|
|
}
|
|
|
|
rel_out:
|
|
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
|
|
* @hw: pointer to the HW structure
|
|
* @maj: driver version major number
|
|
* @min: driver version minor number
|
|
* @build: driver version build number
|
|
* @sub: driver version sub build number
|
|
* @len: unused
|
|
* @driver_ver: unused
|
|
*
|
|
* Sends driver version number to firmware through the manageability
|
|
* block. On success return IXGBE_SUCCESS
|
|
* else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
|
|
* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
|
|
**/
|
|
s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
|
|
u8 build, u8 sub, u16 len,
|
|
const char *driver_ver)
|
|
{
|
|
struct ixgbe_hic_drv_info fw_cmd;
|
|
int i;
|
|
s32 ret_val = IXGBE_SUCCESS;
|
|
|
|
DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
|
|
UNREFERENCED_2PARAMETER(len, driver_ver);
|
|
|
|
fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
|
|
fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
|
|
fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
|
|
fw_cmd.port_num = (u8)hw->bus.func;
|
|
fw_cmd.ver_maj = maj;
|
|
fw_cmd.ver_min = min;
|
|
fw_cmd.ver_build = build;
|
|
fw_cmd.ver_sub = sub;
|
|
fw_cmd.hdr.checksum = 0;
|
|
fw_cmd.pad = 0;
|
|
fw_cmd.pad2 = 0;
|
|
fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
|
|
(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
|
|
|
|
for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
|
|
ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
|
|
sizeof(fw_cmd),
|
|
IXGBE_HI_COMMAND_TIMEOUT,
|
|
true);
|
|
if (ret_val != IXGBE_SUCCESS)
|
|
continue;
|
|
|
|
if (fw_cmd.hdr.cmd_or_resp.ret_status ==
|
|
FW_CEM_RESP_STATUS_SUCCESS)
|
|
ret_val = IXGBE_SUCCESS;
|
|
else
|
|
ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
|
|
|
|
break;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_rxpba_generic - Initialize Rx packet buffer
|
|
* @hw: pointer to hardware structure
|
|
* @num_pb: number of packet buffers to allocate
|
|
* @headroom: reserve n KB of headroom
|
|
* @strategy: packet buffer allocation strategy
|
|
**/
|
|
void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
|
|
int strategy)
|
|
{
|
|
u32 pbsize = hw->mac.rx_pb_size;
|
|
int i = 0;
|
|
u32 rxpktsize, txpktsize, txpbthresh;
|
|
|
|
/* Reserve headroom */
|
|
pbsize -= headroom;
|
|
|
|
if (!num_pb)
|
|
num_pb = 1;
|
|
|
|
/* Divide remaining packet buffer space amongst the number of packet
|
|
* buffers requested using supplied strategy.
|
|
*/
|
|
switch (strategy) {
|
|
case PBA_STRATEGY_WEIGHTED:
|
|
/* ixgbe_dcb_pba_80_48 strategy weight first half of packet
|
|
* buffer with 5/8 of the packet buffer space.
|
|
*/
|
|
rxpktsize = (pbsize * 5) / (num_pb * 4);
|
|
pbsize -= rxpktsize * (num_pb / 2);
|
|
rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
|
|
for (; i < (num_pb / 2); i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
|
|
/* configure remaining packet buffers */
|
|
/* FALLTHROUGH */
|
|
case PBA_STRATEGY_EQUAL:
|
|
rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
|
|
for (; i < num_pb; i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Only support an equally distributed Tx packet buffer strategy. */
|
|
txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
|
|
txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
|
|
for (i = 0; i < num_pb; i++) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
|
|
IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
|
|
}
|
|
|
|
/* Clear unused TCs, if any, to zero buffer size*/
|
|
for (; i < IXGBE_MAX_PB; i++) {
|
|
IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
|
|
* @hw: pointer to the hardware structure
|
|
*
|
|
* The 82599 and x540 MACs can experience issues if TX work is still pending
|
|
* when a reset occurs. This function prevents this by flushing the PCIe
|
|
* buffers on the system.
|
|
**/
|
|
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
|
|
{
|
|
u32 gcr_ext, hlreg0, i, poll;
|
|
u16 value;
|
|
|
|
/*
|
|
* If double reset is not requested then all transactions should
|
|
* already be clear and as such there is no work to do
|
|
*/
|
|
if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
|
|
return;
|
|
|
|
/*
|
|
* Set loopback enable to prevent any transmits from being sent
|
|
* should the link come up. This assumes that the RXCTRL.RXEN bit
|
|
* has already been cleared.
|
|
*/
|
|
hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
|
|
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
|
|
|
|
/* Wait for a last completion before clearing buffers */
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(3);
|
|
|
|
/*
|
|
* Before proceeding, make sure that the PCIe block does not have
|
|
* transactions pending.
|
|
*/
|
|
poll = ixgbe_pcie_timeout_poll(hw);
|
|
for (i = 0; i < poll; i++) {
|
|
usec_delay(100);
|
|
value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
|
|
if (IXGBE_REMOVED(hw->hw_addr))
|
|
goto out;
|
|
if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
/* initiate cleaning flow for buffers in the PCIe transaction layer */
|
|
gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
|
|
IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
|
|
gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
|
|
|
|
/* Flush all writes and allow 20usec for all transactions to clear */
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
usec_delay(20);
|
|
|
|
/* restore previous register values */
|
|
IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
|
|
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
|
|
}
|
|
|
|
static const u8 ixgbe_emc_temp_data[4] = {
|
|
IXGBE_EMC_INTERNAL_DATA,
|
|
IXGBE_EMC_DIODE1_DATA,
|
|
IXGBE_EMC_DIODE2_DATA,
|
|
IXGBE_EMC_DIODE3_DATA
|
|
};
|
|
static const u8 ixgbe_emc_therm_limit[4] = {
|
|
IXGBE_EMC_INTERNAL_THERM_LIMIT,
|
|
IXGBE_EMC_DIODE1_THERM_LIMIT,
|
|
IXGBE_EMC_DIODE2_THERM_LIMIT,
|
|
IXGBE_EMC_DIODE3_THERM_LIMIT
|
|
};
|
|
|
|
/**
|
|
* ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Returns the thermal sensor data structure
|
|
**/
|
|
s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
u16 ets_offset;
|
|
u16 ets_cfg;
|
|
u16 ets_sensor;
|
|
u8 num_sensors;
|
|
u8 sensor_index;
|
|
u8 sensor_location;
|
|
u8 i;
|
|
struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
|
|
|
|
DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
|
|
|
|
/* Only support thermal sensors attached to 82599 physical port 0 */
|
|
if ((hw->mac.type != ixgbe_mac_82599EB) ||
|
|
(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
|
|
status = IXGBE_NOT_IMPLEMENTED;
|
|
goto out;
|
|
}
|
|
|
|
status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
|
|
if (status)
|
|
goto out;
|
|
|
|
if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
|
|
status = IXGBE_NOT_IMPLEMENTED;
|
|
goto out;
|
|
}
|
|
|
|
status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
|
|
if (status)
|
|
goto out;
|
|
|
|
if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
|
|
!= IXGBE_ETS_TYPE_EMC) {
|
|
status = IXGBE_NOT_IMPLEMENTED;
|
|
goto out;
|
|
}
|
|
|
|
num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
|
|
if (num_sensors > IXGBE_MAX_SENSORS)
|
|
num_sensors = IXGBE_MAX_SENSORS;
|
|
|
|
for (i = 0; i < num_sensors; i++) {
|
|
status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
|
|
&ets_sensor);
|
|
if (status)
|
|
goto out;
|
|
|
|
sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
|
|
IXGBE_ETS_DATA_INDEX_SHIFT);
|
|
sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
|
|
IXGBE_ETS_DATA_LOC_SHIFT);
|
|
|
|
if (sensor_location != 0) {
|
|
status = hw->phy.ops.read_i2c_byte(hw,
|
|
ixgbe_emc_temp_data[sensor_index],
|
|
IXGBE_I2C_THERMAL_SENSOR_ADDR,
|
|
&data->sensor[i].temp);
|
|
if (status)
|
|
goto out;
|
|
}
|
|
}
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Inits the thermal sensor thresholds according to the NVM map
|
|
* and save off the threshold and location values into mac.thermal_sensor_data
|
|
**/
|
|
s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
|
|
{
|
|
s32 status = IXGBE_SUCCESS;
|
|
u16 offset;
|
|
u16 ets_offset;
|
|
u16 ets_cfg;
|
|
u16 ets_sensor;
|
|
u8 low_thresh_delta;
|
|
u8 num_sensors;
|
|
u8 sensor_index;
|
|
u8 sensor_location;
|
|
u8 therm_limit;
|
|
u8 i;
|
|
struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
|
|
|
|
DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
|
|
|
|
memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
|
|
|
|
/* Only support thermal sensors attached to 82599 physical port 0 */
|
|
if ((hw->mac.type != ixgbe_mac_82599EB) ||
|
|
(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
|
|
return IXGBE_NOT_IMPLEMENTED;
|
|
|
|
offset = IXGBE_ETS_CFG;
|
|
if (hw->eeprom.ops.read(hw, offset, &ets_offset))
|
|
goto eeprom_err;
|
|
if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
|
|
return IXGBE_NOT_IMPLEMENTED;
|
|
|
|
offset = ets_offset;
|
|
if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
|
|
goto eeprom_err;
|
|
if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
|
|
!= IXGBE_ETS_TYPE_EMC)
|
|
return IXGBE_NOT_IMPLEMENTED;
|
|
|
|
low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
|
|
IXGBE_ETS_LTHRES_DELTA_SHIFT);
|
|
num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
|
|
|
|
for (i = 0; i < num_sensors; i++) {
|
|
offset = ets_offset + 1 + i;
|
|
if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
|
|
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
|
|
"eeprom read at offset %d failed",
|
|
offset);
|
|
continue;
|
|
}
|
|
sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
|
|
IXGBE_ETS_DATA_INDEX_SHIFT);
|
|
sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
|
|
IXGBE_ETS_DATA_LOC_SHIFT);
|
|
therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
|
|
|
|
hw->phy.ops.write_i2c_byte(hw,
|
|
ixgbe_emc_therm_limit[sensor_index],
|
|
IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
|
|
|
|
if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
|
|
data->sensor[i].location = sensor_location;
|
|
data->sensor[i].caution_thresh = therm_limit;
|
|
data->sensor[i].max_op_thresh = therm_limit -
|
|
low_thresh_delta;
|
|
}
|
|
}
|
|
return status;
|
|
|
|
eeprom_err:
|
|
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
|
|
"eeprom read at offset %d failed", offset);
|
|
return IXGBE_NOT_IMPLEMENTED;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
|
|
*
|
|
* @hw: pointer to hardware structure
|
|
* @cmd: Command we send to the FW
|
|
* @status: The reply from the FW
|
|
*
|
|
* Bit-bangs the cmd to the by_pass FW status points to what is returned.
|
|
**/
|
|
#define IXGBE_BYPASS_BB_WAIT 1
|
|
s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
|
|
{
|
|
int i;
|
|
u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;
|
|
u32 esdp;
|
|
|
|
if (!status)
|
|
return IXGBE_ERR_PARAM;
|
|
|
|
*status = 0;
|
|
|
|
/* SDP vary by MAC type */
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82599EB:
|
|
sck = IXGBE_ESDP_SDP7;
|
|
sdi = IXGBE_ESDP_SDP0;
|
|
sdo = IXGBE_ESDP_SDP6;
|
|
dir_sck = IXGBE_ESDP_SDP7_DIR;
|
|
dir_sdi = IXGBE_ESDP_SDP0_DIR;
|
|
dir_sdo = IXGBE_ESDP_SDP6_DIR;
|
|
break;
|
|
case ixgbe_mac_X540:
|
|
sck = IXGBE_ESDP_SDP2;
|
|
sdi = IXGBE_ESDP_SDP0;
|
|
sdo = IXGBE_ESDP_SDP1;
|
|
dir_sck = IXGBE_ESDP_SDP2_DIR;
|
|
dir_sdi = IXGBE_ESDP_SDP0_DIR;
|
|
dir_sdo = IXGBE_ESDP_SDP1_DIR;
|
|
break;
|
|
default:
|
|
return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
|
|
}
|
|
|
|
/* Set SDP pins direction */
|
|
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
|
|
esdp |= dir_sck; /* SCK as output */
|
|
esdp |= dir_sdi; /* SDI as output */
|
|
esdp &= ~dir_sdo; /* SDO as input */
|
|
esdp |= sck;
|
|
esdp |= sdi;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
|
|
/* Generate start condition */
|
|
esdp &= ~sdi;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
|
|
esdp &= ~sck;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
|
|
/* Clock out the new control word and clock in the status */
|
|
for (i = 0; i < 32; i++) {
|
|
if ((cmd >> (31 - i)) & 0x01) {
|
|
esdp |= sdi;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
} else {
|
|
esdp &= ~sdi;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
}
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
|
|
esdp |= sck;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
|
|
esdp &= ~sck;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
|
|
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
|
|
if (esdp & sdo)
|
|
*status = (*status << 1) | 0x01;
|
|
else
|
|
*status = (*status << 1) | 0x00;
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
}
|
|
|
|
/* stop condition */
|
|
esdp |= sck;
|
|
esdp &= ~sdi;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
msec_delay(IXGBE_BYPASS_BB_WAIT);
|
|
|
|
esdp |= sdi;
|
|
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
|
|
IXGBE_WRITE_FLUSH(hw);
|
|
|
|
/* set the page bits to match the cmd that the status it belongs to */
|
|
*status = (*status & 0x3fffffff) | (cmd & 0xc0000000);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
|
|
*
|
|
* If we send a write we can't be sure it took until we can read back
|
|
* that same register. It can be a problem as some of the fields may
|
|
* for valid reasons change inbetween the time wrote the register and
|
|
* we read it again to verify. So this function check everything we
|
|
* can check and then assumes it worked.
|
|
*
|
|
* @u32 in_reg - The register cmd for the bit-bang read.
|
|
* @u32 out_reg - The register returned from a bit-bang read.
|
|
**/
|
|
bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
|
|
{
|
|
u32 mask;
|
|
|
|
/* Page must match for all control pages */
|
|
if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))
|
|
return false;
|
|
|
|
switch (in_reg & BYPASS_PAGE_M) {
|
|
case BYPASS_PAGE_CTL0:
|
|
/* All the following can't change since the last write
|
|
* - All the event actions
|
|
* - The timeout value
|
|
*/
|
|
mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |
|
|
BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |
|
|
BYPASS_WDTIMEOUT_M |
|
|
BYPASS_WDT_VALUE_M;
|
|
if ((out_reg & mask) != (in_reg & mask))
|
|
return false;
|
|
|
|
/* 0x0 is never a valid value for bypass status */
|
|
if (!(out_reg & BYPASS_STATUS_OFF_M))
|
|
return false;
|
|
break;
|
|
case BYPASS_PAGE_CTL1:
|
|
/* All the following can't change since the last write
|
|
* - time valid bit
|
|
* - time we last sent
|
|
*/
|
|
mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;
|
|
if ((out_reg & mask) != (in_reg & mask))
|
|
return false;
|
|
break;
|
|
case BYPASS_PAGE_CTL2:
|
|
/* All we can check in this page is control number
|
|
* which is already done above.
|
|
*/
|
|
break;
|
|
}
|
|
|
|
/* We are as sure as we can be return true */
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
|
|
*
|
|
* @hw: pointer to hardware structure
|
|
* @cmd: The control word we are setting.
|
|
* @event: The event we are setting in the FW. This also happens to
|
|
* be the mask for the event we are setting (handy)
|
|
* @action: The action we set the event to in the FW. This is in a
|
|
* bit field that happens to be what we want to put in
|
|
* the event spot (also handy)
|
|
**/
|
|
s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
|
|
u32 action)
|
|
{
|
|
u32 by_ctl = 0;
|
|
u32 cmd, verify;
|
|
u32 count = 0;
|
|
|
|
/* Get current values */
|
|
cmd = ctrl; /* just reading only need control number */
|
|
if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
|
|
/* Set to new action */
|
|
cmd = (by_ctl & ~event) | BYPASS_WE | action;
|
|
if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
|
|
/* Page 0 force a FW eeprom write which is slow so verify */
|
|
if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {
|
|
verify = BYPASS_PAGE_CTL0;
|
|
do {
|
|
if (count++ > 5)
|
|
return IXGBE_BYPASS_FW_WRITE_FAILURE;
|
|
|
|
if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
} while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));
|
|
} else {
|
|
/* We have give the FW time for the write to stick */
|
|
msec_delay(100);
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres.
|
|
*
|
|
* @hw: pointer to hardware structure
|
|
* @addr: The bypass eeprom address to read.
|
|
* @value: The 8b of data at the address above.
|
|
**/
|
|
s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
|
|
{
|
|
u32 cmd;
|
|
u32 status;
|
|
|
|
|
|
/* send the request */
|
|
cmd = BYPASS_PAGE_CTL2 | BYPASS_WE;
|
|
cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;
|
|
if (ixgbe_bypass_rw_generic(hw, cmd, &status))
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
|
|
/* We have give the FW time for the write to stick */
|
|
msec_delay(100);
|
|
|
|
/* now read the results */
|
|
cmd &= ~BYPASS_WE;
|
|
if (ixgbe_bypass_rw_generic(hw, cmd, &status))
|
|
return IXGBE_ERR_INVALID_ARGUMENT;
|
|
|
|
*value = status & BYPASS_CTL2_DATA_M;
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_orom_version - Return option ROM from EEPROM
|
|
*
|
|
* @hw: pointer to hardware structure
|
|
* @nvm_ver: pointer to output structure
|
|
*
|
|
* if valid option ROM version, nvm_ver->or_valid set to true
|
|
* else nvm_ver->or_valid is false.
|
|
**/
|
|
void ixgbe_get_orom_version(struct ixgbe_hw *hw,
|
|
struct ixgbe_nvm_version *nvm_ver)
|
|
{
|
|
u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
|
|
|
|
nvm_ver->or_valid = false;
|
|
/* Option Rom may or may not be present. Start with pointer */
|
|
hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
|
|
|
|
/* make sure offset is valid */
|
|
if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
|
|
return;
|
|
|
|
hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
|
|
hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
|
|
|
|
/* option rom exists and is valid */
|
|
if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
|
|
eeprom_cfg_blkl == NVM_VER_INVALID ||
|
|
eeprom_cfg_blkh == NVM_VER_INVALID)
|
|
return;
|
|
|
|
nvm_ver->or_valid = true;
|
|
nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
|
|
nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
|
|
(eeprom_cfg_blkh >> NVM_OROM_SHIFT);
|
|
nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_oem_prod_version - Return OEM Product version
|
|
*
|
|
* @hw: pointer to hardware structure
|
|
* @nvm_ver: pointer to output structure
|
|
*
|
|
* if valid OEM product version, nvm_ver->oem_valid set to true
|
|
* else nvm_ver->oem_valid is false.
|
|
**/
|
|
void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
|
|
struct ixgbe_nvm_version *nvm_ver)
|
|
{
|
|
u16 rel_num, prod_ver, mod_len, cap, offset;
|
|
|
|
nvm_ver->oem_valid = false;
|
|
hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
|
|
|
|
/* Return if offset to OEM Product Version block is invalid */
|
|
if (offset == 0x0 || offset == NVM_INVALID_PTR)
|
|
return;
|
|
|
|
/* Read product version block */
|
|
hw->eeprom.ops.read(hw, offset, &mod_len);
|
|
hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
|
|
|
|
/* Return if OEM product version block is invalid */
|
|
if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
|
|
(cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
|
|
return;
|
|
|
|
hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
|
|
hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
|
|
|
|
/* Return if version is invalid */
|
|
if ((rel_num | prod_ver) == 0x0 ||
|
|
rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
|
|
return;
|
|
|
|
nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
|
|
nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
|
|
nvm_ver->oem_release = rel_num;
|
|
nvm_ver->oem_valid = true;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_get_etk_id - Return Etrack ID from EEPROM
|
|
*
|
|
* @hw: pointer to hardware structure
|
|
* @nvm_ver: pointer to output structure
|
|
*
|
|
* word read errors will return 0xFFFF
|
|
**/
|
|
void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
|
|
{
|
|
u16 etk_id_l, etk_id_h;
|
|
|
|
if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
|
|
etk_id_l = NVM_VER_INVALID;
|
|
if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
|
|
etk_id_h = NVM_VER_INVALID;
|
|
|
|
/* The word order for the version format is determined by high order
|
|
* word bit 15.
|
|
*/
|
|
if ((etk_id_h & NVM_ETK_VALID) == 0) {
|
|
nvm_ver->etk_id = etk_id_h;
|
|
nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
|
|
} else {
|
|
nvm_ver->etk_id = etk_id_l;
|
|
nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
|
|
* @hw: pointer to hardware structure
|
|
* @map: pointer to u8 arr for returning map
|
|
*
|
|
* Read the rtrup2tc HW register and resolve its content into map
|
|
**/
|
|
void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
|
|
{
|
|
u32 reg, i;
|
|
|
|
reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
|
|
for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
|
|
map[i] = IXGBE_RTRUP2TC_UP_MASK &
|
|
(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
|
|
return;
|
|
}
|
|
|
|
void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u32 pfdtxgswc;
|
|
u32 rxctrl;
|
|
|
|
rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
|
|
if (rxctrl & IXGBE_RXCTRL_RXEN) {
|
|
if (hw->mac.type != ixgbe_mac_82598EB) {
|
|
pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
|
|
if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
|
|
pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
|
|
IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
|
|
hw->mac.set_lben = true;
|
|
} else {
|
|
hw->mac.set_lben = false;
|
|
}
|
|
}
|
|
rxctrl &= ~IXGBE_RXCTRL_RXEN;
|
|
IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
|
|
}
|
|
}
|
|
|
|
void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
|
|
{
|
|
u32 pfdtxgswc;
|
|
u32 rxctrl;
|
|
|
|
rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
|
|
IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
|
|
|
|
if (hw->mac.type != ixgbe_mac_82598EB) {
|
|
if (hw->mac.set_lben) {
|
|
pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
|
|
pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
|
|
IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
|
|
hw->mac.set_lben = false;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ixgbe_mng_present - returns true when management capability is present
|
|
* @hw: pointer to hardware structure
|
|
*/
|
|
bool ixgbe_mng_present(struct ixgbe_hw *hw)
|
|
{
|
|
u32 fwsm;
|
|
|
|
if (hw->mac.type < ixgbe_mac_82599EB)
|
|
return false;
|
|
|
|
fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
|
|
|
|
return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_mng_enabled - Is the manageability engine enabled?
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Returns true if the manageability engine is enabled.
|
|
**/
|
|
bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
|
|
{
|
|
u32 fwsm, manc, factps;
|
|
|
|
fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
|
|
if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
|
|
return false;
|
|
|
|
manc = IXGBE_READ_REG(hw, IXGBE_MANC);
|
|
if (!(manc & IXGBE_MANC_RCV_TCO_EN))
|
|
return false;
|
|
|
|
if (hw->mac.type <= ixgbe_mac_X540) {
|
|
factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
|
|
if (factps & IXGBE_FACTPS_MNGCG)
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
|
|
* @hw: pointer to hardware structure
|
|
* @speed: new link speed
|
|
* @autoneg_wait_to_complete: true when waiting for completion is needed
|
|
*
|
|
* Set the link speed in the MAC and/or PHY register and restarts link.
|
|
**/
|
|
s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
|
|
ixgbe_link_speed speed,
|
|
bool autoneg_wait_to_complete)
|
|
{
|
|
ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
s32 status = IXGBE_SUCCESS;
|
|
u32 speedcnt = 0;
|
|
u32 i = 0;
|
|
bool autoneg, link_up = false;
|
|
|
|
DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
|
|
|
|
/* Mask off requested but non-supported speeds */
|
|
status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
|
|
if (status != IXGBE_SUCCESS)
|
|
return status;
|
|
|
|
speed &= link_speed;
|
|
|
|
/* Try each speed one by one, highest priority first. We do this in
|
|
* software because 10Gb fiber doesn't support speed autonegotiation.
|
|
*/
|
|
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
|
|
speedcnt++;
|
|
highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
|
|
|
|
/* Set the module link speed */
|
|
switch (hw->phy.media_type) {
|
|
case ixgbe_media_type_fiber_fixed:
|
|
case ixgbe_media_type_fiber:
|
|
ixgbe_set_rate_select_speed(hw,
|
|
IXGBE_LINK_SPEED_10GB_FULL);
|
|
break;
|
|
case ixgbe_media_type_fiber_qsfp:
|
|
/* QSFP module automatically detects MAC link speed */
|
|
break;
|
|
default:
|
|
DEBUGOUT("Unexpected media type.\n");
|
|
break;
|
|
}
|
|
|
|
/* Allow module to change analog characteristics (1G->10G) */
|
|
msec_delay(40);
|
|
|
|
status = ixgbe_setup_mac_link(hw,
|
|
IXGBE_LINK_SPEED_10GB_FULL,
|
|
autoneg_wait_to_complete);
|
|
if (status != IXGBE_SUCCESS)
|
|
return status;
|
|
|
|
/* Flap the Tx laser if it has not already been done */
|
|
ixgbe_flap_tx_laser(hw);
|
|
|
|
/* Wait for the controller to acquire link. Per IEEE 802.3ap,
|
|
* Section 73.10.2, we may have to wait up to 1000ms if KR is
|
|
* attempted. 82599 uses the same timing for 10g SFI.
|
|
*/
|
|
for (i = 0; i < 10; i++) {
|
|
/* Wait for the link partner to also set speed */
|
|
msec_delay(100);
|
|
|
|
/* If we have link, just jump out */
|
|
status = ixgbe_check_link(hw, &link_speed,
|
|
&link_up, false);
|
|
if (status != IXGBE_SUCCESS)
|
|
return status;
|
|
|
|
if (link_up)
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
|
|
speedcnt++;
|
|
if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
|
|
highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
|
|
|
|
/* Set the module link speed */
|
|
switch (hw->phy.media_type) {
|
|
case ixgbe_media_type_fiber_fixed:
|
|
case ixgbe_media_type_fiber:
|
|
ixgbe_set_rate_select_speed(hw,
|
|
IXGBE_LINK_SPEED_1GB_FULL);
|
|
break;
|
|
case ixgbe_media_type_fiber_qsfp:
|
|
/* QSFP module automatically detects link speed */
|
|
break;
|
|
default:
|
|
DEBUGOUT("Unexpected media type.\n");
|
|
break;
|
|
}
|
|
|
|
/* Allow module to change analog characteristics (10G->1G) */
|
|
msec_delay(40);
|
|
|
|
status = ixgbe_setup_mac_link(hw,
|
|
IXGBE_LINK_SPEED_1GB_FULL,
|
|
autoneg_wait_to_complete);
|
|
if (status != IXGBE_SUCCESS)
|
|
return status;
|
|
|
|
/* Flap the Tx laser if it has not already been done */
|
|
ixgbe_flap_tx_laser(hw);
|
|
|
|
/* Wait for the link partner to also set speed */
|
|
msec_delay(100);
|
|
|
|
/* If we have link, just jump out */
|
|
status = ixgbe_check_link(hw, &link_speed, &link_up, false);
|
|
if (status != IXGBE_SUCCESS)
|
|
return status;
|
|
|
|
if (link_up)
|
|
goto out;
|
|
}
|
|
|
|
/* We didn't get link. Configure back to the highest speed we tried,
|
|
* (if there was more than one). We call ourselves back with just the
|
|
* single highest speed that the user requested.
|
|
*/
|
|
if (speedcnt > 1)
|
|
status = ixgbe_setup_mac_link_multispeed_fiber(hw,
|
|
highest_link_speed,
|
|
autoneg_wait_to_complete);
|
|
|
|
out:
|
|
/* Set autoneg_advertised value based on input link speed */
|
|
hw->phy.autoneg_advertised = 0;
|
|
|
|
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
|
|
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
|
|
|
|
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
|
|
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_soft_rate_select_speed - Set module link speed
|
|
* @hw: pointer to hardware structure
|
|
* @speed: link speed to set
|
|
*
|
|
* Set module link speed via the soft rate select.
|
|
*/
|
|
void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
|
|
ixgbe_link_speed speed)
|
|
{
|
|
s32 status;
|
|
u8 rs, eeprom_data;
|
|
|
|
switch (speed) {
|
|
case IXGBE_LINK_SPEED_10GB_FULL:
|
|
/* one bit mask same as setting on */
|
|
rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
|
|
break;
|
|
case IXGBE_LINK_SPEED_1GB_FULL:
|
|
rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
|
|
break;
|
|
default:
|
|
DEBUGOUT("Invalid fixed module speed\n");
|
|
return;
|
|
}
|
|
|
|
/* Set RS0 */
|
|
status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
|
|
IXGBE_I2C_EEPROM_DEV_ADDR2,
|
|
&eeprom_data);
|
|
if (status) {
|
|
DEBUGOUT("Failed to read Rx Rate Select RS0\n");
|
|
goto out;
|
|
}
|
|
|
|
eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
|
|
|
|
status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
|
|
IXGBE_I2C_EEPROM_DEV_ADDR2,
|
|
eeprom_data);
|
|
if (status) {
|
|
DEBUGOUT("Failed to write Rx Rate Select RS0\n");
|
|
goto out;
|
|
}
|
|
|
|
/* Set RS1 */
|
|
status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
|
|
IXGBE_I2C_EEPROM_DEV_ADDR2,
|
|
&eeprom_data);
|
|
if (status) {
|
|
DEBUGOUT("Failed to read Rx Rate Select RS1\n");
|
|
goto out;
|
|
}
|
|
|
|
eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
|
|
|
|
status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
|
|
IXGBE_I2C_EEPROM_DEV_ADDR2,
|
|
eeprom_data);
|
|
if (status) {
|
|
DEBUGOUT("Failed to write Rx Rate Select RS1\n");
|
|
goto out;
|
|
}
|
|
out:
|
|
return;
|
|
}
|