714 lines
17 KiB
C
714 lines
17 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Microsoft Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef _MANA_H
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#define _MANA_H
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#include <sys/types.h>
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#include <sys/proc.h>
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#include <sys/socket.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <sys/counter.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <netinet/tcp_lro.h>
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#include "gdma.h"
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#include "hw_channel.h"
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/* Microsoft Azure Network Adapter (MANA)'s definitions
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*
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* Structures labeled with "HW DATA" are exchanged with the hardware. All of
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* them are naturally aligned and hence don't need __packed.
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*/
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/* MANA protocol version */
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#define MANA_MAJOR_VERSION 0
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#define MANA_MINOR_VERSION 1
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#define MANA_MICRO_VERSION 1
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#define DRV_MODULE_NAME "mana"
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#ifndef DRV_MODULE_VERSION
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#define DRV_MODULE_VERSION \
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__XSTRING(MANA_MAJOR_VERSION) "." \
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__XSTRING(MANA_MINOR_VERSION) "." \
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__XSTRING(MANA_MICRO_VERSION)
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#endif
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#define DEVICE_NAME "Microsoft Azure Network Adapter (MANA)"
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#define DEVICE_DESC "MANA adapter"
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/*
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* Supported PCI vendor and devices IDs
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*/
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#ifndef PCI_VENDOR_ID_MICROSOFT
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#define PCI_VENDOR_ID_MICROSOFT 0x1414
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#endif
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#define PCI_DEV_ID_MANA_VF 0x00ba
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typedef struct _mana_vendor_id_t {
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uint16_t vendor_id;
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uint16_t device_id;
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} mana_vendor_id_t;
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typedef uint64_t mana_handle_t;
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#define INVALID_MANA_HANDLE ((mana_handle_t)-1)
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enum TRI_STATE {
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TRI_STATE_UNKNOWN = -1,
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TRI_STATE_FALSE = 0,
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TRI_STATE_TRUE = 1
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};
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/* Number of entries for hardware indirection table must be in power of 2 */
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#define MANA_INDIRECT_TABLE_SIZE 64
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#define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1)
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/* The Toeplitz hash key's length in bytes: should be multiple of 8 */
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#define MANA_HASH_KEY_SIZE 40
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#define COMP_ENTRY_SIZE 64
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#define MIN_FRAME_SIZE 146
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#define ADAPTER_MTU_SIZE 1500
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#define DEFAULT_FRAME_SIZE (ADAPTER_MTU_SIZE + 14)
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#define MAX_FRAME_SIZE 4096
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#define RX_BUFFERS_PER_QUEUE 512
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#define MAX_SEND_BUFFERS_PER_QUEUE 256
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#define EQ_SIZE (8 * PAGE_SIZE)
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#define LOG2_EQ_THROTTLE 3
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#define MAX_PORTS_IN_MANA_DEV 8
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struct mana_send_buf_info {
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struct mbuf *mbuf;
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bus_dmamap_t dma_map;
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/* Required to store the result of mana_gd_post_work_request.
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* gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the
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* work queue when the WQE is consumed.
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*/
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struct gdma_posted_wqe_info wqe_inf;
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};
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struct mana_stats {
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counter_u64_t packets; /* rx, tx */
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counter_u64_t bytes; /* rx, tx */
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counter_u64_t stop; /* tx */
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counter_u64_t wakeup; /* tx */
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counter_u64_t collapse; /* tx */
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counter_u64_t collapse_err; /* tx */
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counter_u64_t dma_mapping_err; /* rx, tx */
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counter_u64_t mbuf_alloc_fail; /* rx */
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counter_u64_t alt_chg; /* tx */
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counter_u64_t alt_reset; /* tx */
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};
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struct mana_txq {
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struct gdma_queue *gdma_sq;
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union {
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uint32_t gdma_txq_id;
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struct {
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uint32_t reserved1 :10;
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uint32_t vsq_frame :14;
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uint32_t reserved2 :8;
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};
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};
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uint16_t vp_offset;
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if_t ndev;
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/* Store index to the array of tx_qp in port structure */
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int idx;
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/* The alternative txq idx when this txq is under heavy load */
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int alt_txq_idx;
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/* The mbufs are sent to the HW and we are waiting for the CQEs. */
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struct mana_send_buf_info *tx_buf_info;
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uint16_t next_to_use;
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uint16_t next_to_complete;
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atomic_t pending_sends;
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struct buf_ring *txq_br;
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struct mtx txq_mtx;
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char txq_mtx_name[16];
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struct task enqueue_task;
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struct taskqueue *enqueue_tq;
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struct mana_stats stats;
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};
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/*
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* Max WQE size is 512B. The first 8B is for GDMA Out of Band (OOB),
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* next is the Client OOB can be either 8B or 24B. Thus, the max
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* space for SGL entries in a singel WQE is 512 - 8 - 8 = 496B. Since each
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* SGL is 16B in size, the max number of SGLs in a WQE is 496/16 = 31.
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* Save one for emergency use, set the MAX_MBUF_FRAGS allowed to 30.
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*/
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#define MAX_MBUF_FRAGS 30
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#define MANA_TSO_MAXSEG_SZ PAGE_SIZE
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/* mbuf data and frags dma mappings */
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struct mana_mbuf_head {
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bus_addr_t dma_handle[MAX_MBUF_FRAGS + 1];
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uint32_t size[MAX_MBUF_FRAGS + 1];
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};
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#define MANA_HEADROOM sizeof(struct mana_mbuf_head)
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enum mana_tx_pkt_format {
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MANA_SHORT_PKT_FMT = 0,
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MANA_LONG_PKT_FMT = 1,
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};
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struct mana_tx_short_oob {
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uint32_t pkt_fmt :2;
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uint32_t is_outer_ipv4 :1;
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uint32_t is_outer_ipv6 :1;
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uint32_t comp_iphdr_csum :1;
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uint32_t comp_tcp_csum :1;
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uint32_t comp_udp_csum :1;
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uint32_t supress_txcqe_gen :1;
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uint32_t vcq_num :24;
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uint32_t trans_off :10; /* Transport header offset */
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uint32_t vsq_frame :14;
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uint32_t short_vp_offset :8;
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}; /* HW DATA */
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struct mana_tx_long_oob {
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uint32_t is_encap :1;
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uint32_t inner_is_ipv6 :1;
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uint32_t inner_tcp_opt :1;
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uint32_t inject_vlan_pri_tag :1;
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uint32_t reserved1 :12;
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uint32_t pcp :3; /* 802.1Q */
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uint32_t dei :1; /* 802.1Q */
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uint32_t vlan_id :12; /* 802.1Q */
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uint32_t inner_frame_offset :10;
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uint32_t inner_ip_rel_offset :6;
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uint32_t long_vp_offset :12;
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uint32_t reserved2 :4;
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uint32_t reserved3;
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uint32_t reserved4;
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}; /* HW DATA */
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struct mana_tx_oob {
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struct mana_tx_short_oob s_oob;
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struct mana_tx_long_oob l_oob;
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}; /* HW DATA */
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enum mana_cq_type {
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MANA_CQ_TYPE_RX,
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MANA_CQ_TYPE_TX,
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};
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enum mana_cqe_type {
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CQE_INVALID = 0,
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CQE_RX_OKAY = 1,
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CQE_RX_COALESCED_4 = 2,
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CQE_RX_OBJECT_FENCE = 3,
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CQE_RX_TRUNCATED = 4,
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CQE_TX_OKAY = 32,
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CQE_TX_SA_DROP = 33,
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CQE_TX_MTU_DROP = 34,
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CQE_TX_INVALID_OOB = 35,
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CQE_TX_INVALID_ETH_TYPE = 36,
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CQE_TX_HDR_PROCESSING_ERROR = 37,
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CQE_TX_VF_DISABLED = 38,
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CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39,
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CQE_TX_VPORT_DISABLED = 40,
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CQE_TX_VLAN_TAGGING_VIOLATION = 41,
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};
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#define MANA_CQE_COMPLETION 1
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struct mana_cqe_header {
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uint32_t cqe_type :6;
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uint32_t client_type :2;
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uint32_t vendor_err :24;
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}; /* HW DATA */
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/* NDIS HASH Types */
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#define NDIS_HASH_IPV4 BIT(0)
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#define NDIS_HASH_TCP_IPV4 BIT(1)
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#define NDIS_HASH_UDP_IPV4 BIT(2)
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#define NDIS_HASH_IPV6 BIT(3)
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#define NDIS_HASH_TCP_IPV6 BIT(4)
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#define NDIS_HASH_UDP_IPV6 BIT(5)
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#define NDIS_HASH_IPV6_EX BIT(6)
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#define NDIS_HASH_TCP_IPV6_EX BIT(7)
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#define NDIS_HASH_UDP_IPV6_EX BIT(8)
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#define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX)
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#define MANA_HASH_L4 \
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(NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \
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NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX)
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#define NDIS_HASH_IPV4_L3_MASK (NDIS_HASH_IPV4)
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#define NDIS_HASH_IPV4_L4_MASK (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4)
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#define NDIS_HASH_IPV6_L3_MASK (NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX)
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#define NDIS_HASH_IPV6_L4_MASK \
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(NDIS_HASH_TCP_IPV6 | NDIS_HASH_UDP_IPV6 | \
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NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX)
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#define NDIS_HASH_IPV4_MASK \
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(NDIS_HASH_IPV4_L3_MASK | NDIS_HASH_IPV4_L4_MASK)
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#define NDIS_HASH_IPV6_MASK \
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(NDIS_HASH_IPV6_L3_MASK | NDIS_HASH_IPV6_L4_MASK)
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struct mana_rxcomp_perpkt_info {
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uint32_t pkt_len :16;
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uint32_t reserved1 :16;
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uint32_t reserved2;
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uint32_t pkt_hash;
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}; /* HW DATA */
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#define MANA_RXCOMP_OOB_NUM_PPI 4
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/* Receive completion OOB */
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struct mana_rxcomp_oob {
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struct mana_cqe_header cqe_hdr;
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uint32_t rx_vlan_id :12;
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uint32_t rx_vlantag_present :1;
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uint32_t rx_outer_iphdr_csum_succeed :1;
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uint32_t rx_outer_iphdr_csum_fail :1;
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uint32_t reserved1 :1;
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uint32_t rx_hashtype :9;
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uint32_t rx_iphdr_csum_succeed :1;
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uint32_t rx_iphdr_csum_fail :1;
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uint32_t rx_tcp_csum_succeed :1;
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uint32_t rx_tcp_csum_fail :1;
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uint32_t rx_udp_csum_succeed :1;
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uint32_t rx_udp_csum_fail :1;
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uint32_t reserved2 :1;
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struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI];
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uint32_t rx_wqe_offset;
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}; /* HW DATA */
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struct mana_tx_comp_oob {
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struct mana_cqe_header cqe_hdr;
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uint32_t tx_data_offset;
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uint32_t tx_sgl_offset :5;
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uint32_t tx_wqe_offset :27;
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uint32_t reserved[12];
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}; /* HW DATA */
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struct mana_rxq;
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#define CQE_POLLING_BUFFER 512
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struct mana_cq {
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struct gdma_queue *gdma_cq;
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/* Cache the CQ id (used to verify if each CQE comes to the right CQ. */
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uint32_t gdma_id;
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/* Type of the CQ: TX or RX */
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enum mana_cq_type type;
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/* Pointer to the mana_rxq that is pushing RX CQEs to the queue.
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* Only and must be non-NULL if type is MANA_CQ_TYPE_RX.
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*/
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struct mana_rxq *rxq;
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/* Pointer to the mana_txq that is pushing TX CQEs to the queue.
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* Only and must be non-NULL if type is MANA_CQ_TYPE_TX.
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*/
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struct mana_txq *txq;
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/* Taskqueue and related structs */
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struct task cleanup_task;
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struct taskqueue *cleanup_tq;
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int cpu;
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bool do_not_ring_db;
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/* Budget for one cleanup task */
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int work_done;
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int budget;
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/* Buffer which the CQ handler can copy the CQE's into. */
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struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER];
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};
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struct mana_recv_buf_oob {
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/* A valid GDMA work request representing the data buffer. */
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struct gdma_wqe_request wqe_req;
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struct mbuf *mbuf;
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bus_dmamap_t dma_map;
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/* SGL of the buffer going to be sent as part of the work request. */
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uint32_t num_sge;
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struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES];
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/* Required to store the result of mana_gd_post_work_request.
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* gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the
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* work queue when the WQE is consumed.
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*/
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struct gdma_posted_wqe_info wqe_inf;
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};
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struct mana_rxq {
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struct gdma_queue *gdma_rq;
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/* Cache the gdma receive queue id */
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uint32_t gdma_id;
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/* Index of RQ in the vPort, not gdma receive queue id */
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uint32_t rxq_idx;
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uint32_t datasize;
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mana_handle_t rxobj;
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struct completion fence_event;
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struct mana_cq rx_cq;
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if_t ndev;
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struct lro_ctrl lro;
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/* Total number of receive buffers to be allocated */
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uint32_t num_rx_buf;
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uint32_t buf_index;
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struct mana_stats stats;
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/* MUST BE THE LAST MEMBER:
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* Each receive buffer has an associated mana_recv_buf_oob.
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*/
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struct mana_recv_buf_oob rx_oobs[];
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};
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struct mana_tx_qp {
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struct mana_txq txq;
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struct mana_cq tx_cq;
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mana_handle_t tx_object;
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};
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struct mana_port_stats {
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counter_u64_t rx_packets;
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counter_u64_t tx_packets;
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counter_u64_t rx_bytes;
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counter_u64_t tx_bytes;
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counter_u64_t rx_drops;
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counter_u64_t tx_drops;
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counter_u64_t stop_queue;
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counter_u64_t wake_queue;
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};
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struct mana_context {
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struct gdma_dev *gdma_dev;
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uint16_t num_ports;
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struct mana_eq *eqs;
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if_t ports[MAX_PORTS_IN_MANA_DEV];
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};
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struct mana_port_context {
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struct mana_context *ac;
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if_t ndev;
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struct ifmedia media;
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struct sx apc_lock;
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/* DMA tag used for queue bufs of the entire port */
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bus_dma_tag_t rx_buf_tag;
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bus_dma_tag_t tx_buf_tag;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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enum TRI_STATE rss_state;
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mana_handle_t default_rxobj;
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bool tx_shortform_allowed;
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uint16_t tx_vp_offset;
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struct mana_tx_qp *tx_qp;
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/* Indirection Table for RX & TX. The values are queue indexes */
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uint32_t indir_table[MANA_INDIRECT_TABLE_SIZE];
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/* Indirection table containing RxObject Handles */
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mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE];
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/* Hash key used by the NIC */
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uint8_t hashkey[MANA_HASH_KEY_SIZE];
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/* This points to an array of num_queues of RQ pointers. */
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struct mana_rxq **rxqs;
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/* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */
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unsigned int max_queues;
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unsigned int num_queues;
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mana_handle_t port_handle;
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int vport_use_count;
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uint16_t port_idx;
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uint16_t frame_size;
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bool port_is_up;
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bool port_st_save; /* Saved port state */
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bool enable_tx_altq;
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bool bind_cleanup_thread_cpu;
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int last_tx_cq_bind_cpu;
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int last_rx_cq_bind_cpu;
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struct mana_port_stats port_stats;
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struct sysctl_oid_list *port_list;
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struct sysctl_ctx_list que_sysctl_ctx;
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};
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#define MANA_APC_LOCK_INIT(apc) \
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sx_init(&(apc)->apc_lock, "MANA port lock")
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#define MANA_APC_LOCK_DESTROY(apc) sx_destroy(&(apc)->apc_lock)
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#define MANA_APC_LOCK_LOCK(apc) sx_xlock(&(apc)->apc_lock)
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#define MANA_APC_LOCK_UNLOCK(apc) sx_unlock(&(apc)->apc_lock)
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int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx,
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bool update_hash, bool update_tab);
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int mana_alloc_queues(if_t ndev);
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int mana_attach(if_t ndev);
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int mana_detach(if_t ndev);
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int mana_probe(struct gdma_dev *gd);
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void mana_remove(struct gdma_dev *gd);
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struct mana_obj_spec {
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uint32_t queue_index;
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uint64_t gdma_region;
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uint32_t queue_size;
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uint32_t attached_eq;
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uint32_t modr_ctx_id;
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};
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|
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enum mana_command_code {
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MANA_QUERY_DEV_CONFIG = 0x20001,
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MANA_QUERY_GF_STAT = 0x20002,
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MANA_CONFIG_VPORT_TX = 0x20003,
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MANA_CREATE_WQ_OBJ = 0x20004,
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MANA_DESTROY_WQ_OBJ = 0x20005,
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MANA_FENCE_RQ = 0x20006,
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MANA_CONFIG_VPORT_RX = 0x20007,
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MANA_QUERY_VPORT_CONFIG = 0x20008,
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};
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/* Query Device Configuration */
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struct mana_query_device_cfg_req {
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struct gdma_req_hdr hdr;
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/* Driver Capability flags */
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uint64_t drv_cap_flags1;
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uint64_t drv_cap_flags2;
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|
uint64_t drv_cap_flags3;
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|
uint64_t drv_cap_flags4;
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|
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uint32_t proto_major_ver;
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|
uint32_t proto_minor_ver;
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|
uint32_t proto_micro_ver;
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|
|
|
uint32_t reserved;
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|
}; /* HW DATA */
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|
|
|
struct mana_query_device_cfg_resp {
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|
struct gdma_resp_hdr hdr;
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|
|
|
uint64_t pf_cap_flags1;
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|
uint64_t pf_cap_flags2;
|
|
uint64_t pf_cap_flags3;
|
|
uint64_t pf_cap_flags4;
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|
|
|
uint16_t max_num_vports;
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|
uint16_t reserved;
|
|
uint32_t max_num_eqs;
|
|
}; /* HW DATA */
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|
|
|
/* Query vPort Configuration */
|
|
struct mana_query_vport_cfg_req {
|
|
struct gdma_req_hdr hdr;
|
|
uint32_t vport_index;
|
|
}; /* HW DATA */
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|
|
|
struct mana_query_vport_cfg_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
uint32_t max_num_sq;
|
|
uint32_t max_num_rq;
|
|
uint32_t num_indirection_ent;
|
|
uint32_t reserved1;
|
|
uint8_t mac_addr[6];
|
|
uint8_t reserved2[2];
|
|
mana_handle_t vport;
|
|
}; /* HW DATA */
|
|
|
|
/* Configure vPort */
|
|
struct mana_config_vport_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t vport;
|
|
uint32_t pdid;
|
|
uint32_t doorbell_pageid;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_config_vport_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
uint16_t tx_vport_offset;
|
|
uint8_t short_form_allowed;
|
|
uint8_t reserved;
|
|
}; /* HW DATA */
|
|
|
|
/* Create WQ Object */
|
|
struct mana_create_wqobj_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t vport;
|
|
uint32_t wq_type;
|
|
uint32_t reserved;
|
|
uint64_t wq_gdma_region;
|
|
uint64_t cq_gdma_region;
|
|
uint32_t wq_size;
|
|
uint32_t cq_size;
|
|
uint32_t cq_moderation_ctx_id;
|
|
uint32_t cq_parent_qid;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_create_wqobj_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
uint32_t wq_id;
|
|
uint32_t cq_id;
|
|
mana_handle_t wq_obj;
|
|
}; /* HW DATA */
|
|
|
|
/* Destroy WQ Object */
|
|
struct mana_destroy_wqobj_req {
|
|
struct gdma_req_hdr hdr;
|
|
uint32_t wq_type;
|
|
uint32_t reserved;
|
|
mana_handle_t wq_obj_handle;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_destroy_wqobj_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
/* Fence RQ */
|
|
struct mana_fence_rq_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t wq_obj_handle;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_fence_rq_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
/* Configure vPort Rx Steering */
|
|
struct mana_cfg_rx_steer_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t vport;
|
|
uint16_t num_indir_entries;
|
|
uint16_t indir_tab_offset;
|
|
uint32_t rx_enable;
|
|
uint32_t rss_enable;
|
|
uint8_t update_default_rxobj;
|
|
uint8_t update_hashkey;
|
|
uint8_t update_indir_tab;
|
|
uint8_t reserved;
|
|
mana_handle_t default_rxobj;
|
|
uint8_t hashkey[MANA_HASH_KEY_SIZE];
|
|
}; /* HW DATA */
|
|
|
|
struct mana_cfg_rx_steer_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
#define MANA_MAX_NUM_QUEUES 16
|
|
|
|
#define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1)
|
|
|
|
struct mana_tx_package {
|
|
struct gdma_wqe_request wqe_req;
|
|
struct gdma_sge sgl_array[MAX_MBUF_FRAGS];
|
|
|
|
struct mana_tx_oob tx_oob;
|
|
|
|
struct gdma_posted_wqe_info wqe_info;
|
|
};
|
|
|
|
int mana_restart(struct mana_port_context *apc);
|
|
|
|
int mana_create_wq_obj(struct mana_port_context *apc,
|
|
mana_handle_t vport,
|
|
uint32_t wq_type, struct mana_obj_spec *wq_spec,
|
|
struct mana_obj_spec *cq_spec,
|
|
mana_handle_t *wq_obj);
|
|
|
|
void mana_destroy_wq_obj(struct mana_port_context *apc, uint32_t wq_type,
|
|
mana_handle_t wq_obj);
|
|
|
|
int mana_cfg_vport(struct mana_port_context *apc, uint32_t protection_dom_id,
|
|
uint32_t doorbell_pg_id);
|
|
|
|
void mana_uncfg_vport(struct mana_port_context *apc);
|
|
#endif /* _MANA_H */
|