Previously every file that included mpi3mr_app.h but did not use
mpi3mr_mgmt_info reported error: 'mpi3mr_mgmt_info' defined but not
used.
Fixes: 2d1d418e1e
("mpi3mr: 3rd Generation Tri-Mode NVMe/SAS/SATA...")
Reported by: amd64-gcc12 Cirrus-CI job
Sponsored by: The FreeBSD Foundation
292 lines
7.2 KiB
C
292 lines
7.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020-2023, Broadcom Inc. All rights reserved.
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* Support: <fbsd-storage-driver.pdl@broadcom.com>
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*
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* Authors: Sumit Saxena <sumit.saxena@broadcom.com>
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* Chandrakanth Patil <chandrakanth.patil@broadcom.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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* 3. Neither the name of the Broadcom Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation are
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* those of the authors and should not be interpreted as representing
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* official policies,either expressed or implied, of the FreeBSD Project.
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*
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* Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
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*
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* Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
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*/
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#include "mpi3mr.h"
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#ifndef _MPI3MR_APP_H_
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#define _MPI3MR_APP_H_
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#define MPI3MR_IOCTL_ADPTYPE_AVGFAMILY 1
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#define MPI3MR_IOCTL_VERSION 0x06
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#define MPI3MRDRVCMD _IOWR('B', 1, struct mpi3mr_ioctl_drvcmd)
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#define MPI3MRMPTCMD _IOWR('B', 2, struct mpi3mr_ioctl_mptcmd)
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#define MPI3MR_IOCTL_DEFAULT_TIMEOUT (10)
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#define PEND_IOCTLS_COMP_WAIT_TIME (10)
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#define MPI3MR_IOCTL_LOGDATA_MAX_ENTRIES 400
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#define MPI3MR_IOCTL_LOGDATA_ENTRY_HEADER_SZ 0x5
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#define GET_IOC_STATUS(ioc_status) \
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ioc_status & MPI3_IOCSTATUS_STATUS_MASK
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/* Encapsulated NVMe command definitions */
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#define MPI3MR_NVME_PRP_SIZE 8
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#define MPI3MR_NVME_CMD_PRP1_OFFSET 24
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#define MPI3MR_NVME_CMD_PRP2_OFFSET 32
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#define MPI3MR_NVME_CMD_SGL_OFFSET 24
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#define MPI3MR_NVME_DATA_FORMAT_PRP 0
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#define MPI3MR_NVME_DATA_FORMAT_SGL1 1
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#define MPI3MR_NVME_DATA_FORMAT_SGL2 2
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#define MPI3MR_NVMESGL_DATA_SEGMENT 0x00
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#define MPI3MR_NVMESGL_LAST_SEGMENT 0x03
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int mpi3mr_app_attach(struct mpi3mr_softc *);
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void mpi3mr_app_detach(struct mpi3mr_softc *);
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enum mpi3mr_ioctl_adp_state {
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MPI3MR_IOCTL_ADP_STATE_UNKNOWN = 0,
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MPI3MR_IOCTL_ADP_STATE_OPERATIONAL = 1,
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MPI3MR_IOCTL_ADP_STATE_FAULT = 2,
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MPI3MR_IOCTL_ADP_STATE_IN_RESET = 3,
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MPI3MR_IOCTL_ADP_STATE_UNRECOVERABLE = 4,
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};
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enum mpi3mr_ioctl_data_dir {
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MPI3MR_APP_DDN,
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MPI3MR_APP_DDI,
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MPI3MR_APP_DDO,
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};
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enum mpi3mr_ioctl_drvcmds_opcode {
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MPI3MR_DRVRIOCTL_OPCODE_UNKNOWN = 0,
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MPI3MR_DRVRIOCTL_OPCODE_ADPINFO = 1,
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MPI3MR_DRVRIOCTL_OPCODE_ADPRESET = 2,
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MPI3MR_DRVRIOCTL_OPCODE_TGTDEVINFO = 3,
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MPI3MR_DRVRIOCTL_OPCODE_ALLTGTDEVINFO = 4,
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MPI3MR_DRVRIOCTL_OPCODE_GETCHGCNT = 5,
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MPI3MR_DRVRIOCTL_OPCODE_LOGDATAENABLE = 6,
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MPI3MR_DRVRIOCTL_OPCODE_PELENABLE = 7,
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MPI3MR_DRVRIOCTL_OPCODE_GETLOGDATA = 8,
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MPI3MR_DRVRIOCTL_OPCODE_GETPCIINFO = 100,
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};
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enum mpi3mr_ioctl_mpibuffer_type {
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MPI3MR_IOCTL_BUFTYPE_UNKNOWN,
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MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_CMD,
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MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_RESP,
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MPI3MR_IOCTL_BUFTYPE_DATA_IN,
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MPI3MR_IOCTL_BUFTYPE_DATA_OUT,
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MPI3MR_IOCTL_BUFTYPE_MPI_REPLY,
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MPI3MR_IOCTL_BUFTYPE_ERR_RESPONSE,
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};
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enum mpi3mr_ioctl_mpireply_type {
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MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_UNKNOWN,
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MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_STATUS,
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MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_ADDRESS,
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};
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enum mpi3mr_ioctl_reset_type {
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MPI3MR_IOCTL_ADPRESET_UNKNOWN,
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MPI3MR_IOCTL_ADPRESET_SOFT,
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MPI3MR_IOCTL_ADPRESET_DIAG_FAULT,
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};
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struct mpi3mr_ioctl_drvcmd {
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U8 mrioc_id;
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U8 opcode;
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U16 rsvd1;
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U32 rsvd2;
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void *data_in_buf;
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void *data_out_buf;
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U32 data_in_size;
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U32 data_out_size;
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};
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struct mpi3mr_ioctl_adpinfo {
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U32 adp_type;
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U32 rsvd1;
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U32 pci_dev_id;
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U32 pci_dev_hw_rev;
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U32 pci_subsys_dev_id;
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U32 pci_subsys_ven_id;
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U32 pci_dev:5;
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U32 pci_func:3;
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U32 pci_bus:8;
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U32 rsvd2:16;
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U32 pci_seg_id;
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U32 ioctl_ver;
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U8 adp_state;
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U8 rsvd3;
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U16 rsvd4;
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U32 rsvd5[2];
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Mpi3DriverInfoLayout_t driver_info;
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};
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struct mpi3mr_ioctl_pciinfo {
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U32 config_space[64];
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};
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struct mpi3mr_ioctl_tgtinfo {
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U32 target_id;
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U8 bus_id;
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U8 rsvd1;
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U16 rsvd2;
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U16 dev_handle;
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U16 persistent_id;
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U32 seq_num;
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};
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struct mpi3mr_device_map_info {
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U16 handle;
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U16 per_id;
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U32 target_id;
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U8 bus_id;
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U8 rsvd1;
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U16 rsvd2;
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};
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struct mpi3mr_ioctl_all_tgtinfo {
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U16 num_devices;
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U16 rsvd1;
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U32 rsvd2;
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struct mpi3mr_device_map_info dmi[1];
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};
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struct mpi3mr_ioctl_chgcnt {
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U16 change_count;
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U16 rsvd;
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};
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struct mpi3mr_ioctl_adpreset {
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U8 reset_type;
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U8 rsvd1;
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U16 rsvd2;
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};
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struct mpi3mr_ioctl_mptcmd {
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U8 mrioc_id;
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U8 rsvd1;
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U16 timeout;
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U16 rsvd2;
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U16 mpi_msg_size;
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void *mpi_msg_buf;
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void *buf_entry_list;
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U32 buf_entry_list_size;
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};
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struct mpi3mr_buf_entry {
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U8 buf_type;
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U8 rsvd1;
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U16 rsvd2;
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U32 buf_len;
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void *buffer;
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};
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struct mpi3mr_ioctl_buf_entry_list {
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U8 num_of_buf_entries;
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U8 rsvd1;
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U16 rsvd2;
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U32 rsvd3;
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struct mpi3mr_buf_entry buf_entry[1];
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};
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struct mpi3mr_ioctl_mpt_dma_buffer {
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void *user_buf;
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void *kern_buf;
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U32 user_buf_len;
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U32 kern_buf_len;
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bus_addr_t kern_buf_dma;
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bus_dma_tag_t kern_buf_dmatag;
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bus_dmamap_t kern_buf_dmamap;
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U8 data_dir;
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U16 num_dma_desc;
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struct dma_memory_desc *dma_desc;
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};
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struct mpi3mr_ioctl_mpirepbuf {
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U8 mpirep_type;
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U8 rsvd1;
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U16 rsvd2;
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U8 repbuf[1];
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};
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struct mpi3mr_nvme_pt_sge {
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U64 base_addr;
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U32 length;
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U16 rsvd;
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U8 rsvd1;
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U8 sub_type:4;
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U8 type:4;
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};
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struct mpi3mr_log_data_entry {
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U8 valid_entry;
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U8 rsvd1;
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U16 rsvd2;
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U8 data[1];
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};
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struct mpi3mr_ioctl_logdata_enable {
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U16 max_entries;
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U16 rsvd;
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};
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struct mpi3mr_ioctl_pel_enable {
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U16 pel_locale;
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U8 pel_class;
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U8 rsvd;
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};
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int
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mpi3mr_pel_abort(struct mpi3mr_softc *sc);
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void
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mpi3mr_pel_getseq_complete(struct mpi3mr_softc *sc,
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struct mpi3mr_drvr_cmd *drvr_cmd);
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void
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mpi3mr_issue_pel_wait(struct mpi3mr_softc *sc,
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struct mpi3mr_drvr_cmd *drvr_cmd);
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void
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mpi3mr_pel_wait_complete(struct mpi3mr_softc *sc,
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struct mpi3mr_drvr_cmd *drvr_cmd);
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void
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mpi3mr_send_pel_getseq(struct mpi3mr_softc *sc,
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struct mpi3mr_drvr_cmd *drvr_cmd);
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void
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mpi3mr_app_send_aen(struct mpi3mr_softc *sc);
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#endif /* !_MPI3MR_API_H_ */
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