575 lines
17 KiB
C
575 lines
17 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2012-2014 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __NVME_PRIVATE_H__
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#define __NVME_PRIVATE_H__
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#include <sys/param.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/memdesc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/systm.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/bus.h>
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#include "nvme.h"
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#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
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MALLOC_DECLARE(M_NVME);
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#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
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#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
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#define NVME_ADMIN_TRACKERS (16)
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#define NVME_ADMIN_ENTRIES (128)
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/* min and max are defined in admin queue attributes section of spec */
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#define NVME_MIN_ADMIN_ENTRIES (2)
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#define NVME_MAX_ADMIN_ENTRIES (4096)
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/*
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* NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
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* queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
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* will allow outstanding on an I/O qpair at any time. The only advantage in
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* having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
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* the contents of the submission and completion queues, it will show a longer
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* history of data.
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*/
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#define NVME_IO_ENTRIES (256)
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#define NVME_IO_TRACKERS (128)
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#define NVME_MIN_IO_TRACKERS (4)
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#define NVME_MAX_IO_TRACKERS (1024)
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/*
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* NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
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* for each controller.
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*/
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#define NVME_INT_COAL_TIME (0) /* disabled */
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#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
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#define NVME_MAX_NAMESPACES (16)
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#define NVME_MAX_CONSUMERS (2)
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#define NVME_MAX_ASYNC_EVENTS (8)
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#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */
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#define NVME_MIN_TIMEOUT_PERIOD (5)
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#define NVME_MAX_TIMEOUT_PERIOD (120)
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#define NVME_DEFAULT_RETRY_COUNT (4)
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/* Maximum log page size to fetch for AERs. */
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#define NVME_MAX_AER_LOG_SIZE (4096)
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/*
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* Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
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* it.
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*/
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#ifndef CACHE_LINE_SIZE
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#define CACHE_LINE_SIZE (64)
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#endif
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#define NVME_GONE 0xfffffffful
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extern int32_t nvme_retry_count;
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extern bool nvme_verbose_cmd_dump;
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struct nvme_completion_poll_status {
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struct nvme_completion cpl;
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int done;
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};
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struct nvme_request {
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struct nvme_command cmd;
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struct nvme_qpair *qpair;
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struct memdesc payload;
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nvme_cb_fn_t cb_fn;
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void *cb_arg;
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int32_t retries;
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bool payload_valid;
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bool timeout;
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bool spare[2]; /* Future use */
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STAILQ_ENTRY(nvme_request) stailq;
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};
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struct nvme_async_event_request {
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struct nvme_controller *ctrlr;
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struct nvme_request *req;
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struct nvme_completion cpl;
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uint32_t log_page_id;
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uint32_t log_page_size;
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uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE];
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};
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struct nvme_tracker {
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TAILQ_ENTRY(nvme_tracker) tailq;
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struct nvme_request *req;
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struct nvme_qpair *qpair;
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sbintime_t deadline;
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bus_dmamap_t payload_dma_map;
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uint16_t cid;
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uint64_t *prp;
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bus_addr_t prp_bus_addr;
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};
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enum nvme_recovery {
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RECOVERY_NONE = 0, /* Normal operations */
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RECOVERY_START, /* Deadline has passed, start recovering */
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RECOVERY_RESET, /* This pass, initiate reset of controller */
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RECOVERY_WAITING, /* waiting for the reset to complete */
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};
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struct nvme_qpair {
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struct nvme_controller *ctrlr;
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uint32_t id;
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int domain;
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int cpu;
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uint16_t vector;
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int rid;
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struct resource *res;
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void *tag;
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struct callout timer;
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sbintime_t deadline;
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bool timer_armed;
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enum nvme_recovery recovery_state;
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uint32_t num_entries;
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uint32_t num_trackers;
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uint32_t sq_tdbl_off;
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uint32_t cq_hdbl_off;
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uint32_t phase;
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uint32_t sq_head;
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uint32_t sq_tail;
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uint32_t cq_head;
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int64_t num_cmds;
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int64_t num_intr_handler_calls;
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int64_t num_retries;
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int64_t num_failures;
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int64_t num_ignored;
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struct nvme_command *cmd;
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struct nvme_completion *cpl;
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bus_dma_tag_t dma_tag;
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bus_dma_tag_t dma_tag_payload;
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bus_dmamap_t queuemem_map;
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uint64_t cmd_bus_addr;
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uint64_t cpl_bus_addr;
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TAILQ_HEAD(, nvme_tracker) free_tr;
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TAILQ_HEAD(, nvme_tracker) outstanding_tr;
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STAILQ_HEAD(, nvme_request) queued_req;
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struct nvme_tracker **act_tr;
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struct mtx_padalign lock;
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} __aligned(CACHE_LINE_SIZE);
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struct nvme_namespace {
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struct nvme_controller *ctrlr;
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struct nvme_namespace_data data;
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uint32_t id;
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uint32_t flags;
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struct cdev *cdev;
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void *cons_cookie[NVME_MAX_CONSUMERS];
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uint32_t boundary;
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struct mtx lock;
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};
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/*
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* One of these per allocated PCI device.
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*/
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struct nvme_controller {
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device_t dev;
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struct mtx lock;
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int domain;
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uint32_t ready_timeout_in_ms;
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uint32_t quirks;
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#define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */
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#define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */
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#define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */
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#define QUIRK_AHCI 8 /* Attached via AHCI redirect */
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bus_space_tag_t bus_tag;
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bus_space_handle_t bus_handle;
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int resource_id;
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struct resource *resource;
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/*
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* The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
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* separate from the control registers which are in BAR 0/1. These
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* members track the mapping of BAR 4/5 for that reason.
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*/
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int bar4_resource_id;
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struct resource *bar4_resource;
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int msi_count;
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uint32_t enable_aborts;
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uint32_t num_io_queues;
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uint32_t max_hw_pend_io;
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/* Fields for tracking progress during controller initialization. */
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struct intr_config_hook config_hook;
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uint32_t ns_identified;
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uint32_t queues_created;
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struct task reset_task;
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struct task fail_req_task;
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struct taskqueue *taskqueue;
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/* For shared legacy interrupt. */
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int rid;
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struct resource *res;
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void *tag;
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/** maximum i/o size in bytes */
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uint32_t max_xfer_size;
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/** LO and HI capacity mask */
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uint32_t cap_lo;
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uint32_t cap_hi;
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/** Page size and log2(page_size) - 12 that we're currently using */
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uint32_t page_size;
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uint32_t mps;
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/** interrupt coalescing time period (in microseconds) */
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uint32_t int_coal_time;
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/** interrupt coalescing threshold */
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uint32_t int_coal_threshold;
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/** timeout period in seconds */
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uint32_t timeout_period;
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/** doorbell stride */
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uint32_t dstrd;
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struct nvme_qpair adminq;
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struct nvme_qpair *ioq;
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struct nvme_registers *regs;
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struct nvme_controller_data cdata;
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struct nvme_namespace ns[NVME_MAX_NAMESPACES];
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struct cdev *cdev;
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/** bit mask of event types currently enabled for async events */
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uint32_t async_event_config;
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uint32_t num_aers;
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struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
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void *cons_cookie[NVME_MAX_CONSUMERS];
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uint32_t is_resetting;
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uint32_t is_initialized;
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uint32_t notification_sent;
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bool is_failed;
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bool is_dying;
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STAILQ_HEAD(, nvme_request) fail_req;
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/* Host Memory Buffer */
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int hmb_nchunks;
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size_t hmb_chunk;
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bus_dma_tag_t hmb_tag;
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struct nvme_hmb_chunk {
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bus_dmamap_t hmbc_map;
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void *hmbc_vaddr;
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uint64_t hmbc_paddr;
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} *hmb_chunks;
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bus_dma_tag_t hmb_desc_tag;
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bus_dmamap_t hmb_desc_map;
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struct nvme_hmb_desc *hmb_desc_vaddr;
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uint64_t hmb_desc_paddr;
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};
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#define nvme_mmio_offsetof(reg) \
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offsetof(struct nvme_registers, reg)
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#define nvme_mmio_read_4(sc, reg) \
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bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg))
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#define nvme_mmio_write_4(sc, reg, val) \
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bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg), val)
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#define nvme_mmio_write_8(sc, reg, val) \
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do { \
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bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
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bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg)+4, \
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(val & 0xFFFFFFFF00000000ULL) >> 32); \
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} while (0);
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#define nvme_printf(ctrlr, fmt, args...) \
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device_printf(ctrlr->dev, fmt, ##args)
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void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
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void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
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void *payload,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
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uint32_t nsid, void *payload,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
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uint32_t microseconds,
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uint32_t threshold,
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
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struct nvme_error_information_entry *payload,
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uint32_t num_entries, /* 0 = max */
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
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uint32_t nsid,
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struct nvme_health_information_page *payload,
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
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struct nvme_firmware_page *payload,
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
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uint32_t num_queues, nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
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uint32_t state,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
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uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
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int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
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void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
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void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
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void nvme_ctrlr_reset(struct nvme_controller *ctrlr);
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/* ctrlr defined as void * to allow use with config_intrhook. */
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void nvme_ctrlr_start_config_hook(void *ctrlr_arg);
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void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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int nvme_qpair_construct(struct nvme_qpair *qpair,
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uint32_t num_entries, uint32_t num_trackers,
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struct nvme_controller *ctrlr);
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void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
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struct nvme_tracker *tr);
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bool nvme_qpair_process_completions(struct nvme_qpair *qpair);
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void nvme_qpair_submit_request(struct nvme_qpair *qpair,
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struct nvme_request *req);
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void nvme_qpair_reset(struct nvme_qpair *qpair);
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void nvme_qpair_fail(struct nvme_qpair *qpair);
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void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
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struct nvme_request *req,
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uint32_t sct, uint32_t sc);
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void nvme_admin_qpair_enable(struct nvme_qpair *qpair);
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void nvme_admin_qpair_disable(struct nvme_qpair *qpair);
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void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
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void nvme_io_qpair_enable(struct nvme_qpair *qpair);
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void nvme_io_qpair_disable(struct nvme_qpair *qpair);
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void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
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int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id,
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struct nvme_controller *ctrlr);
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void nvme_ns_destruct(struct nvme_namespace *ns);
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void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
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void nvme_qpair_print_command(struct nvme_qpair *qpair,
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struct nvme_command *cmd);
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void nvme_qpair_print_completion(struct nvme_qpair *qpair,
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struct nvme_completion *cpl);
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int nvme_attach(device_t dev);
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int nvme_shutdown(device_t dev);
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int nvme_detach(device_t dev);
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/*
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* Wait for a command to complete using the nvme_completion_poll_cb. Used in
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* limited contexts where the caller knows it's OK to block briefly while the
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* command runs. The ISR will run the callback which will set status->done to
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* true, usually within microseconds. If not, then after one second timeout
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* handler should reset the controller and abort all outstanding requests
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* including this polled one. If still not after ten seconds, then something is
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* wrong with the driver, and panic is the only way to recover.
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*
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* Most commands using this interface aren't actual I/O to the drive's media so
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* complete within a few microseconds. Adaptively spin for one tick to catch the
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* vast majority of these without waiting for a tick plus scheduling delays. Since
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* these are on startup, this drastically reduces startup time.
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*/
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static __inline
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void
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nvme_completion_poll(struct nvme_completion_poll_status *status)
|
|
{
|
|
int timeout = ticks + 10 * hz;
|
|
sbintime_t delta_t = SBT_1US;
|
|
|
|
while (!atomic_load_acq_int(&status->done)) {
|
|
if (timeout - ticks < 0)
|
|
panic("NVME polled command failed to complete within 10s.");
|
|
pause_sbt("nvme", delta_t, 0, C_PREL(1));
|
|
delta_t = min(SBT_1MS, delta_t * 3 / 2);
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
|
|
{
|
|
uint64_t *bus_addr = (uint64_t *)arg;
|
|
|
|
KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg));
|
|
if (error != 0)
|
|
printf("nvme_single_map err %d\n", error);
|
|
*bus_addr = seg[0].ds_addr;
|
|
}
|
|
|
|
static __inline struct nvme_request *
|
|
_nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg)
|
|
{
|
|
struct nvme_request *req;
|
|
|
|
req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO);
|
|
if (req != NULL) {
|
|
req->cb_fn = cb_fn;
|
|
req->cb_arg = cb_arg;
|
|
req->timeout = true;
|
|
}
|
|
return (req);
|
|
}
|
|
|
|
static __inline struct nvme_request *
|
|
nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
|
|
nvme_cb_fn_t cb_fn, void *cb_arg)
|
|
{
|
|
struct nvme_request *req;
|
|
|
|
req = _nvme_allocate_request(cb_fn, cb_arg);
|
|
if (req != NULL) {
|
|
req->payload = memdesc_vaddr(payload, payload_size);
|
|
req->payload_valid = true;
|
|
}
|
|
return (req);
|
|
}
|
|
|
|
static __inline struct nvme_request *
|
|
nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
|
|
{
|
|
struct nvme_request *req;
|
|
|
|
req = _nvme_allocate_request(cb_fn, cb_arg);
|
|
return (req);
|
|
}
|
|
|
|
static __inline struct nvme_request *
|
|
nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg)
|
|
{
|
|
struct nvme_request *req;
|
|
|
|
req = _nvme_allocate_request(cb_fn, cb_arg);
|
|
if (req != NULL) {
|
|
req->payload = memdesc_bio(bio);
|
|
req->payload_valid = true;
|
|
}
|
|
return (req);
|
|
}
|
|
|
|
static __inline struct nvme_request *
|
|
nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg)
|
|
{
|
|
struct nvme_request *req;
|
|
|
|
req = _nvme_allocate_request(cb_fn, cb_arg);
|
|
if (req != NULL) {
|
|
req->payload = memdesc_ccb(ccb);
|
|
req->payload_valid = true;
|
|
}
|
|
|
|
return (req);
|
|
}
|
|
|
|
#define nvme_free_request(req) free(req, M_NVME)
|
|
|
|
void nvme_notify_async_consumers(struct nvme_controller *ctrlr,
|
|
const struct nvme_completion *async_cpl,
|
|
uint32_t log_page_id, void *log_page_buffer,
|
|
uint32_t log_page_size);
|
|
void nvme_notify_fail_consumers(struct nvme_controller *ctrlr);
|
|
void nvme_notify_new_controller(struct nvme_controller *ctrlr);
|
|
void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid);
|
|
|
|
void nvme_ctrlr_shared_handler(void *arg);
|
|
void nvme_ctrlr_poll(struct nvme_controller *ctrlr);
|
|
|
|
int nvme_ctrlr_suspend(struct nvme_controller *ctrlr);
|
|
int nvme_ctrlr_resume(struct nvme_controller *ctrlr);
|
|
|
|
#endif /* __NVME_PRIVATE_H__ */
|