180 lines
4.7 KiB
C
180 lines
4.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Driver for Qualcomm IPQ4018 clock and reset device */
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/sglist.h>
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#include <sys/random.h>
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#include <sys/stdatomic.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "clkdev_if.h"
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#include "hwreset_if.h"
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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#include "qcom_gcc_ipq4018_var.h"
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static int qcom_gcc_ipq4018_modevent(module_t, int, void *);
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static int qcom_gcc_ipq4018_probe(device_t);
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static int qcom_gcc_ipq4018_attach(device_t);
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static int qcom_gcc_ipq4018_detach(device_t);
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static int
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qcom_gcc_ipq4018_modevent(module_t mod, int type, void *unused)
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{
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int error;
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switch (type) {
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case MOD_LOAD:
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case MOD_QUIESCE:
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case MOD_UNLOAD:
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case MOD_SHUTDOWN:
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error = 0;
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break;
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default:
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error = EOPNOTSUPP;
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break;
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}
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return (error);
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}
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static int
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qcom_gcc_ipq4018_probe(device_t dev)
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{
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if (! ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "qcom,gcc-ipq4019") == 0)
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return (ENXIO);
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return (0);
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}
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static int
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qcom_gcc_ipq4018_attach(device_t dev)
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{
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struct qcom_gcc_ipq4018_softc *sc;
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sc = device_get_softc(dev);
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/* Found a compatible device! */
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sc->dev = dev;
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sc->reg_rid = 0;
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sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY,
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&sc->reg_rid, 0x60000, RF_ACTIVE);
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if (sc->reg == NULL) {
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device_printf(dev, "Couldn't allocate memory resource!\n");
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return (ENXIO);
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}
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device_set_desc(dev, "Qualcomm IPQ4018 Clock/Reset Controller");
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mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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/*
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* Register as a reset provider.
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*/
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hwreset_register_ofw_provider(dev);
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/*
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* Setup and register as a clock provider.
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*/
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qcom_gcc_ipq4018_clock_setup(sc);
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return (0);
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}
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static int
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qcom_gcc_ipq4018_detach(device_t dev)
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{
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struct qcom_gcc_ipq4018_softc *sc;
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sc = device_get_softc(dev);
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/*
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* TBD - deregistering reset/clock resources.
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*/
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if (sc->reg != NULL) {
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bus_release_resource(sc->dev, SYS_RES_MEMORY,
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sc->reg_rid, sc->reg);
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}
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return (0);
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}
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static device_method_t qcom_gcc_ipq4018_methods[] = {
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/* Device methods. */
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DEVMETHOD(device_probe, qcom_gcc_ipq4018_probe),
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DEVMETHOD(device_attach, qcom_gcc_ipq4018_attach),
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DEVMETHOD(device_detach, qcom_gcc_ipq4018_detach),
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/* Reset interface */
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DEVMETHOD(hwreset_assert, qcom_gcc_ipq4018_hwreset_assert),
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DEVMETHOD(hwreset_is_asserted, qcom_gcc_ipq4018_hwreset_is_asserted),
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/* Clock interface */
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DEVMETHOD(clkdev_read_4, qcom_gcc_ipq4018_clock_read),
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DEVMETHOD(clkdev_write_4, qcom_gcc_ipq4018_clock_write),
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DEVMETHOD(clkdev_modify_4, qcom_gcc_ipq4018_clock_modify),
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DEVMETHOD(clkdev_device_lock, qcom_gcc_ipq4018_clock_lock),
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DEVMETHOD(clkdev_device_unlock, qcom_gcc_ipq4018_clock_unlock),
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DEVMETHOD_END
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};
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static driver_t qcom_gcc_ipq4018_driver = {
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"qcom_gcc",
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qcom_gcc_ipq4018_methods,
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sizeof(struct qcom_gcc_ipq4018_softc)
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};
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EARLY_DRIVER_MODULE(qcom_gcc_ipq4018, simplebus, qcom_gcc_ipq4018_driver,
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qcom_gcc_ipq4018_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
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EARLY_DRIVER_MODULE(qcom_gcc_ipq4018, ofwbus, qcom_gcc_ipq4018_driver,
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qcom_gcc_ipq4018_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
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MODULE_VERSION(qcom_gcc_ipq4018, 1);
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