304 lines
9.1 KiB
C
304 lines
9.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2016-2019 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DEV_XDMA_XDMA_H_
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#define _DEV_XDMA_XDMA_H_
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#include <sys/proc.h>
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#include <sys/vmem.h>
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#ifdef FDT
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#endif
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#include <vm/vm.h>
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#include <vm/pmap.h>
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enum xdma_direction {
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XDMA_MEM_TO_MEM,
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XDMA_MEM_TO_DEV,
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XDMA_DEV_TO_MEM,
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XDMA_DEV_TO_DEV,
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};
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enum xdma_operation_type {
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XDMA_MEMCPY,
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XDMA_CYCLIC,
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XDMA_FIFO,
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XDMA_SG,
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};
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enum xdma_request_type {
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XR_TYPE_PHYS,
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XR_TYPE_VIRT,
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XR_TYPE_MBUF,
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XR_TYPE_BIO,
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};
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enum xdma_command {
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XDMA_CMD_BEGIN,
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XDMA_CMD_PAUSE,
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XDMA_CMD_TERMINATE,
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};
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struct xdma_transfer_status {
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uint32_t transferred;
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int error;
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};
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typedef struct xdma_transfer_status xdma_transfer_status_t;
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struct xdma_controller {
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device_t dev; /* DMA consumer device_t. */
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device_t dma_dev; /* A real DMA device_t. */
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void *data; /* OFW MD part. */
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vmem_t *vmem; /* Bounce memory. */
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/* List of virtual channels allocated. */
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TAILQ_HEAD(xdma_channel_list, xdma_channel) channels;
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};
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typedef struct xdma_controller xdma_controller_t;
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struct xchan_buf {
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bus_dmamap_t map;
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uint32_t nsegs;
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uint32_t nsegs_left;
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vm_offset_t vaddr;
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vm_offset_t paddr;
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vm_size_t size;
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};
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struct xdma_request {
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struct mbuf *m;
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struct bio *bp;
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enum xdma_operation_type operation;
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enum xdma_request_type req_type;
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enum xdma_direction direction;
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bus_addr_t src_addr;
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bus_addr_t dst_addr;
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uint8_t src_width;
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uint8_t dst_width;
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bus_size_t block_num;
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bus_size_t block_len;
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xdma_transfer_status_t status;
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void *user;
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TAILQ_ENTRY(xdma_request) xr_next;
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struct xchan_buf buf;
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};
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struct xdma_sglist {
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bus_addr_t src_addr;
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bus_addr_t dst_addr;
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size_t len;
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uint8_t src_width;
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uint8_t dst_width;
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enum xdma_direction direction;
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bool first;
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bool last;
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};
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struct xdma_iommu {
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struct pmap p;
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vmem_t *vmem; /* VA space */
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device_t dev; /* IOMMU device */
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};
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struct xdma_channel {
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xdma_controller_t *xdma;
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vmem_t *vmem;
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uint32_t flags;
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#define XCHAN_BUFS_ALLOCATED (1 << 0)
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#define XCHAN_SGLIST_ALLOCATED (1 << 1)
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#define XCHAN_CONFIGURED (1 << 2)
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#define XCHAN_TYPE_CYCLIC (1 << 3)
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#define XCHAN_TYPE_MEMCPY (1 << 4)
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#define XCHAN_TYPE_FIFO (1 << 5)
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#define XCHAN_TYPE_SG (1 << 6)
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uint32_t caps;
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#define XCHAN_CAP_BUSDMA (1 << 0)
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#define XCHAN_CAP_NOSEG (1 << 1)
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#define XCHAN_CAP_BOUNCE (1 << 2)
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#define XCHAN_CAP_IOMMU (1 << 3)
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/* A real hardware driver channel. */
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void *chan;
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/* Interrupt handlers. */
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TAILQ_HEAD(, xdma_intr_handler) ie_handlers;
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TAILQ_ENTRY(xdma_channel) xchan_next;
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struct mtx mtx_lock;
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struct mtx mtx_qin_lock;
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struct mtx mtx_qout_lock;
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struct mtx mtx_bank_lock;
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struct mtx mtx_proc_lock;
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/* Request queue. */
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bus_dma_tag_t dma_tag_bufs;
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struct xdma_request *xr_mem;
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uint32_t xr_num;
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/* Bus dma tag options. */
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bus_size_t maxsegsize;
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bus_size_t maxnsegs;
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bus_size_t alignment;
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bus_addr_t boundary;
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bus_addr_t lowaddr;
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bus_addr_t highaddr;
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struct xdma_sglist *sg;
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TAILQ_HEAD(, xdma_request) bank;
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TAILQ_HEAD(, xdma_request) queue_in;
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TAILQ_HEAD(, xdma_request) queue_out;
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TAILQ_HEAD(, xdma_request) processing;
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/* iommu */
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struct xdma_iommu xio;
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};
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typedef struct xdma_channel xdma_channel_t;
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struct xdma_intr_handler {
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int (*cb)(void *cb_user, xdma_transfer_status_t *status);
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int flags;
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#define XDMA_INTR_NET (1 << 0)
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void *cb_user;
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TAILQ_ENTRY(xdma_intr_handler) ih_next;
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};
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static MALLOC_DEFINE(M_XDMA, "xdma", "xDMA framework");
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#define XCHAN_LOCK(xchan) mtx_lock(&(xchan)->mtx_lock)
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#define XCHAN_UNLOCK(xchan) mtx_unlock(&(xchan)->mtx_lock)
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#define XCHAN_ASSERT_LOCKED(xchan) \
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mtx_assert(&(xchan)->mtx_lock, MA_OWNED)
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#define QUEUE_IN_LOCK(xchan) mtx_lock(&(xchan)->mtx_qin_lock)
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#define QUEUE_IN_UNLOCK(xchan) mtx_unlock(&(xchan)->mtx_qin_lock)
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#define QUEUE_IN_ASSERT_LOCKED(xchan) \
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mtx_assert(&(xchan)->mtx_qin_lock, MA_OWNED)
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#define QUEUE_OUT_LOCK(xchan) mtx_lock(&(xchan)->mtx_qout_lock)
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#define QUEUE_OUT_UNLOCK(xchan) mtx_unlock(&(xchan)->mtx_qout_lock)
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#define QUEUE_OUT_ASSERT_LOCKED(xchan) \
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mtx_assert(&(xchan)->mtx_qout_lock, MA_OWNED)
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#define QUEUE_BANK_LOCK(xchan) mtx_lock(&(xchan)->mtx_bank_lock)
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#define QUEUE_BANK_UNLOCK(xchan) mtx_unlock(&(xchan)->mtx_bank_lock)
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#define QUEUE_BANK_ASSERT_LOCKED(xchan) \
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mtx_assert(&(xchan)->mtx_bank_lock, MA_OWNED)
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#define QUEUE_PROC_LOCK(xchan) mtx_lock(&(xchan)->mtx_proc_lock)
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#define QUEUE_PROC_UNLOCK(xchan) mtx_unlock(&(xchan)->mtx_proc_lock)
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#define QUEUE_PROC_ASSERT_LOCKED(xchan) \
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mtx_assert(&(xchan)->mtx_proc_lock, MA_OWNED)
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#define XDMA_SGLIST_MAXLEN 2048
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#define XDMA_MAX_SEG 128
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/* xDMA controller ops */
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xdma_controller_t *xdma_ofw_get(device_t dev, const char *prop);
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xdma_controller_t *xdma_get(device_t dev, device_t dma_dev);
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int xdma_put(xdma_controller_t *xdma);
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vmem_t * xdma_get_memory(device_t dev);
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void xdma_put_memory(vmem_t *vmem);
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#ifdef FDT
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int xdma_handle_mem_node(vmem_t *vmem, phandle_t memory);
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#endif
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/* xDMA channel ops */
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xdma_channel_t * xdma_channel_alloc(xdma_controller_t *, uint32_t caps);
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int xdma_channel_free(xdma_channel_t *);
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int xdma_request(xdma_channel_t *xchan, struct xdma_request *r);
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void xchan_set_memory(xdma_channel_t *xchan, vmem_t *vmem);
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/* SG interface */
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int xdma_prep_sg(xdma_channel_t *, uint32_t,
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bus_size_t, bus_size_t, bus_size_t, bus_addr_t, bus_addr_t, bus_addr_t);
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void xdma_channel_free_sg(xdma_channel_t *xchan);
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int xdma_queue_submit_sg(xdma_channel_t *xchan);
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void xchan_seg_done(xdma_channel_t *xchan, xdma_transfer_status_t *);
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/* Queue operations */
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int xdma_dequeue_mbuf(xdma_channel_t *xchan, struct mbuf **m,
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xdma_transfer_status_t *);
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int xdma_enqueue_mbuf(xdma_channel_t *xchan, struct mbuf **m, uintptr_t addr,
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uint8_t, uint8_t, enum xdma_direction dir);
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int xdma_dequeue_bio(xdma_channel_t *xchan, struct bio **bp,
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xdma_transfer_status_t *status);
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int xdma_enqueue_bio(xdma_channel_t *xchan, struct bio **bp, bus_addr_t addr,
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uint8_t, uint8_t, enum xdma_direction dir);
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int xdma_dequeue(xdma_channel_t *xchan, void **user,
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xdma_transfer_status_t *status);
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int xdma_enqueue(xdma_channel_t *xchan, uintptr_t src, uintptr_t dst,
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uint8_t, uint8_t, bus_size_t, enum xdma_direction dir, void *);
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int xdma_queue_submit(xdma_channel_t *xchan);
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/* Mbuf operations */
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uint32_t xdma_mbuf_defrag(xdma_channel_t *xchan, struct xdma_request *xr);
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uint32_t xdma_mbuf_chain_count(struct mbuf *m0);
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/* Channel Control */
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int xdma_control(xdma_channel_t *xchan, enum xdma_command cmd);
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/* Interrupt callback */
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int xdma_setup_intr(xdma_channel_t *xchan, int flags, int (*cb)(void *,
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xdma_transfer_status_t *), void *arg, void **);
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int xdma_teardown_intr(xdma_channel_t *xchan, struct xdma_intr_handler *ih);
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int xdma_teardown_all_intr(xdma_channel_t *xchan);
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void xdma_callback(struct xdma_channel *xchan, xdma_transfer_status_t *status);
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/* Sglist */
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int xchan_sglist_alloc(xdma_channel_t *xchan);
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void xchan_sglist_free(xdma_channel_t *xchan);
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int xdma_sglist_add(struct xdma_sglist *sg, struct bus_dma_segment *seg,
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uint32_t nsegs, struct xdma_request *xr);
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/* Requests bank */
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void xchan_bank_init(xdma_channel_t *xchan);
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int xchan_bank_free(xdma_channel_t *xchan);
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struct xdma_request * xchan_bank_get(xdma_channel_t *xchan);
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int xchan_bank_put(xdma_channel_t *xchan, struct xdma_request *xr);
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/* IOMMU */
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void xdma_iommu_add_entry(xdma_channel_t *xchan, vm_offset_t *va,
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vm_paddr_t pa, vm_size_t size, vm_prot_t prot);
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void xdma_iommu_remove_entry(xdma_channel_t *xchan, vm_offset_t va);
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int xdma_iommu_init(struct xdma_iommu *xio);
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int xdma_iommu_release(struct xdma_iommu *xio);
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#endif /* !_DEV_XDMA_XDMA_H_ */
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