396 lines
10 KiB
C
396 lines
10 KiB
C
/*-
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* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
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* Communications, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the following conditions are met:
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* 1. The materials contained herein are unmodified and are used
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* unmodified.
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* 2. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following NO
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* ''WARRANTY'' disclaimer below (''Disclaimer''), without
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* modification.
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* 3. Redistributions in binary form must reproduce at minimum a
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* disclaimer similar to the Disclaimer below and any redistribution
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* must be conditioned upon including a substantially similar
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* Disclaimer requirement for further binary redistribution.
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* 4. Neither the names of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote
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* product derived from this software without specific prior written
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* permission.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
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* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
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* FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES.
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*
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* $Id: ah_osdep.c,v 1.28 2003/11/01 01:43:21 sam Exp $
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*/
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#include "opt_ah.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <sys/bus.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <machine/stdarg.h>
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#include <net/ethernet.h> /* XXX for ether_sprintf */
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#include <contrib/dev/ath/ah.h>
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extern void ath_hal_printf(struct ath_hal *, const char*, ...)
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__printflike(2,3);
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extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
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__printflike(2, 0);
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extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
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extern void *ath_hal_malloc(size_t);
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extern void ath_hal_free(void *);
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#ifdef AH_ASSERT
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extern void ath_hal_assert_failed(const char* filename,
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int lineno, const char* msg);
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#endif
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#ifdef AH_DEBUG
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extern void HALDEBUG(struct ath_hal *ah, const char* fmt, ...);
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extern void HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...);
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#endif /* AH_DEBUG */
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/* NB: put this here instead of the driver to avoid circular references */
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SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
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SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
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#ifdef AH_DEBUG
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static int ath_hal_debug = 0; /* XXX */
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SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
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0, "Atheros HAL debugging printfs");
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#endif /* AH_DEBUG */
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SYSCTL_STRING(_hw_ath_hal, OID_AUTO, version, CTLFLAG_RD, ath_hal_version, 0,
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"Atheros HAL version");
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int ath_hal_dma_beacon_response_time = 2; /* in TU's */
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SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
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&ath_hal_dma_beacon_response_time, 0,
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"Atheros HAL DMA beacon response time");
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int ath_hal_sw_beacon_response_time = 10; /* in TU's */
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SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
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&ath_hal_sw_beacon_response_time, 0,
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"Atheros HAL software beacon response time");
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int ath_hal_additional_swba_backoff = 0; /* in TU's */
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SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
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&ath_hal_additional_swba_backoff, 0,
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"Atheros HAL additional SWBA backoff time");
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void*
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ath_hal_malloc(size_t size)
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{
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return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
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}
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void
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ath_hal_free(void* p)
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{
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return free(p, M_DEVBUF);
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}
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void
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ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
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{
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vprintf(fmt, ap);
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}
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void
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ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
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{
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va_list ap;
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va_start(ap, fmt);
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ath_hal_vprintf(ah, fmt, ap);
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va_end(ap);
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}
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const char*
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ath_hal_ether_sprintf(const u_int8_t *mac)
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{
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return ether_sprintf(mac);
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}
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#ifdef AH_DEBUG
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void
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HALDEBUG(struct ath_hal *ah, const char* fmt, ...)
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{
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if (ath_hal_debug) {
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__va_list ap;
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va_start(ap, fmt);
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ath_hal_vprintf(ah, fmt, ap);
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va_end(ap);
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}
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}
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void
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HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
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{
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if (ath_hal_debug >= level) {
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__va_list ap;
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va_start(ap, fmt);
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ath_hal_vprintf(ah, fmt, ap);
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va_end(ap);
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}
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}
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#endif /* AH_DEBUG */
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#ifdef AH_DEBUG_ALQ
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/*
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* ALQ register tracing support.
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*
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* Setting hw.ath.hal.alq=1 enables tracing of all register reads and
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* writes to the file /tmp/ath_hal.log. The file format is a simple
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* fixed-size array of records. When done logging set hw.ath.hal.alq=0
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* and then decode the file with the arcode program (that is part of the
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* HAL). If you start+stop tracing the data will be appended to an
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* existing file.
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*
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* NB: doesn't handle multiple devices properly; only one DEVICE record
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* is emitted and the different devices are not identified.
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*/
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#include <sys/alq.h>
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#include <sys/pcpu.h>
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#include <contrib/dev/ath/ah_decode.h>
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static struct alq *ath_hal_alq;
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static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
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static u_int ath_hal_alq_lost; /* count of lost records */
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static const char *ath_hal_logfile = "/tmp/ath_hal.log";
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static u_int ath_hal_alq_qsize = 64*1024;
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static int
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ath_hal_setlogging(int enable)
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{
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int error;
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if (enable) {
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error = suser(curthread);
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if (error == 0) {
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error = alq_open(&ath_hal_alq, ath_hal_logfile,
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curthread->td_ucred,
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sizeof (struct athregrec), ath_hal_alq_qsize);
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ath_hal_alq_lost = 0;
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ath_hal_alq_emitdev = 1;
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printf("ath_hal: logging to %s enabled\n",
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ath_hal_logfile);
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}
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} else {
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if (ath_hal_alq)
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alq_close(ath_hal_alq);
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ath_hal_alq = NULL;
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printf("ath_hal: logging disabled\n");
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error = 0;
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}
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return (error);
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}
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static int
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sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
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{
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int error, enable;
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enable = (ath_hal_alq != NULL);
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error = sysctl_handle_int(oidp, &enable, 0, req);
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if (error || !req->newptr)
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return (error);
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else
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return (ath_hal_setlogging(enable));
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}
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SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
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0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
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SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
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&ath_hal_alq_qsize, 0, "In-memory log size (#records)");
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SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
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&ath_hal_alq_lost, 0, "Register operations not logged");
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static struct ale *
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ath_hal_alq_get(struct ath_hal *ah)
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{
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struct ale *ale;
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if (ath_hal_alq_emitdev) {
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ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
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if (ale) {
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struct athregrec *r =
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(struct athregrec *) ale->ae_data;
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r->op = OP_DEVICE;
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r->reg = 0;
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r->val = ah->ah_devid;
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alq_post(ath_hal_alq, ale);
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ath_hal_alq_emitdev = 0;
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} else
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ath_hal_alq_lost++;
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}
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ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
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if (!ale)
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ath_hal_alq_lost++;
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return ale;
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}
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void
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ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
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{
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if (ath_hal_alq) {
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struct ale *ale = ath_hal_alq_get(ah);
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if (ale) {
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struct athregrec *r = (struct athregrec *) ale->ae_data;
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r->op = OP_WRITE;
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r->reg = reg;
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r->val = val;
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alq_post(ath_hal_alq, ale);
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}
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}
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val));
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else
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#endif
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bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val);
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}
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u_int32_t
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ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
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{
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u_int32_t val;
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val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg);
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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val = le32toh(val);
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#endif
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if (ath_hal_alq) {
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struct ale *ale = ath_hal_alq_get(ah);
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if (ale) {
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struct athregrec *r = (struct athregrec *) ale->ae_data;
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r->op = OP_READ;
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r->reg = reg;
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r->val = val;
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alq_post(ath_hal_alq, ale);
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}
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}
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return val;
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}
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void
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OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
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{
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if (ath_hal_alq) {
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struct ale *ale = ath_hal_alq_get(ah);
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if (ale) {
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struct athregrec *r = (struct athregrec *) ale->ae_data;
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r->op = OP_MARK;
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r->reg = id;
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r->val = v;
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alq_post(ath_hal_alq, ale);
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}
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}
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}
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#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
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/*
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* Memory-mapped device register read/write. These are here
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* as routines when debugging support is enabled and/or when
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* explicitly configured to use function calls. The latter is
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* for architectures that might need to do something before
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* referencing memory (e.g. remap an i/o window).
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*
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* NB: see the comments in ah_osdep.h about byte-swapping register
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* reads and writes to understand what's going on below.
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*/
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void
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ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
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{
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val));
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else
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#endif
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bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val);
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}
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u_int32_t
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ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
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{
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u_int32_t val;
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val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg);
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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val = le32toh(val);
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#endif
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return val;
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}
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#endif /* AH_DEBUG || AH_REGOPS_FUNC */
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#ifdef AH_ASSERT
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void
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ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
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{
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printf("Atheros HAL assertion failure: %s: line %u: %s\n",
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filename, lineno, msg);
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panic("ath_hal_assert");
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}
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#endif /* AH_ASSERT */
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/*
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* Delay n microseconds.
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*/
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void
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ath_hal_delay(int n)
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{
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DELAY(n);
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}
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u_int32_t
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ath_hal_getuptime(struct ath_hal *ah)
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{
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struct bintime bt;
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getbinuptime(&bt);
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return (bt.sec * 1000) +
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(((uint64_t)1000 * (uint32_t)(bt.frac >> 32)) >> 32);
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}
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/*
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* Module glue.
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*/
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static int
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ath_hal_modevent(module_t mod, int type, void *unused)
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{
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switch (type) {
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case MOD_LOAD:
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if (bootverbose)
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printf("ath_hal: <Atheros Hardware Access Layer>"
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"version %s\n", ath_hal_version);
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return 0;
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case MOD_UNLOAD:
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return 0;
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}
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return EINVAL;
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}
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static moduledata_t ath_hal_mod = {
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"ath_hal",
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ath_hal_modevent,
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0
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};
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DECLARE_MODULE(ath_hal, ath_hal_mod, SI_SUB_DRIVERS, SI_ORDER_ANY);
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MODULE_VERSION(ath_hal, 1);
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