61e9cdfe46
Compaq XP1000, AlphaServer DS20, AlphaServer DS10, and DP264 This has been tested *only* on XP1000's. I'll be interested to hear from owners of other types of DEC_ST6600 alphas. I'd like to thank Don Rice of Compaq for providing the documentation required to support this platform on FreeBSD. I'd also like to thank Doug Rabson for newbus, and for helping me get a multiple hoses working with newbus. Reviewed by: Doug Rabson <dfr@nlsystems.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/* $Id$ */
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/*
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* 21271 Chipset registers and constants.
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*
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* Taken from Tsunami/Typhoon Specification Rev. 1.2
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* and Compaq Professional Workstation XP1000: Technical
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* Information, both graciously provided by Don Rice
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*/
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typedef struct {
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volatile u_int64_t reg __attribute__((aligned(64)));
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} tsunami_reg;
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/* notes */
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typedef struct {
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tsunami_reg csc; /* rw */
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tsunami_reg mtr; /* rw */
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tsunami_reg misc; /* rw */
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tsunami_reg mpd; /* rw */
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tsunami_reg aar0; /* rw */
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tsunami_reg aar1; /* rw */
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tsunami_reg aar2; /* rw */
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tsunami_reg aar3; /* rw */
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tsunami_reg dim0; /* rw */
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tsunami_reg dim1; /* rw */
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tsunami_reg dir0; /* ro */
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tsunami_reg dir1; /* ro */
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tsunami_reg drir; /* ro */
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tsunami_reg prben; /* "special" */
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tsunami_reg iic0; /* rw */
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tsunami_reg iic1; /* rw */
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tsunami_reg mpr0; /* wo */
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tsunami_reg mpr1; /* wo */
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tsunami_reg mpr2; /* wo */
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tsunami_reg mpr3; /* wo */
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tsunami_reg mctl; /* rw, Tsunami only */
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tsunami_reg ttr; /* rw */
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tsunami_reg tdr; /* rw */
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tsunami_reg dim2; /* rw, Typhoon only */
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tsunami_reg dim3; /* rw, Typhoon only */
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tsunami_reg dir2; /* ro, Typhoon only */
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tsunami_reg dir3; /* ro, Typhoon only */
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tsunami_reg iic2; /* rw, Typhoon only */
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tsunami_reg iic3; /* rw, Typhoon only */
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tsunami_reg pwr; /* rw */
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} tsunami_cchip;
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typedef struct {
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tsunami_reg dsc;
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tsunami_reg str;
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tsunami_reg drev;
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} tsunami_dchip;
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typedef struct {
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tsunami_reg wsba[4]; /* rw */
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tsunami_reg wsm[4]; /* rw */
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tsunami_reg tba[4]; /* rw */
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tsunami_reg pctl; /* rw */
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tsunami_reg plat; /* ro */
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tsunami_reg reserved; /* rw */
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tsunami_reg perror; /* rw */
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tsunami_reg perrmask; /* rw */
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tsunami_reg perrset; /* wo */
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tsunami_reg tlbiv; /* wo */
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tsunami_reg tlbia; /* wo */
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tsunami_reg pmonctl; /* rw */
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tsunami_reg pmoncnt; /* rw */
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} tsunami_pchip;
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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#define cchip ((tsunami_cchip *)(KV(0x101A0000000UL)))
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#define dchip ((tsunami_dchip *)(KV(0x101B0000800UL)))
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#define pchip0 ((tsunami_pchip *)(KV(0x10180000000UL)))
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#define pchip1 ((tsunami_pchip *)(KV(0x10380000000UL)))
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/*
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* memory / i/o space macros
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*
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*/
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#define HOSE(h) (((unsigned long)(h)) << 33)
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#define TSUNAMI_MEM(h) (0x10000000000UL + HOSE(h))
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#define TSUNAMI_IACK_SC(h) (0x101F8000000UL + HOSE(h))
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#define TSUNAMI_IO(h) (0x101FC000000UL + HOSE(h))
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#define TSUNAMI_CONF(h) (0x101FE000000UL + HOSE(h))
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#define TSUNAMI_MAXHOSES 4
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