04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
511 lines
21 KiB
C
511 lines
21 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-tim-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon tim.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_TIM_TYPEDEFS_H__
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#define __CVMX_TIM_TYPEDEFS_H__
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#define CVMX_TIM_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180058001100ull))
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#define CVMX_TIM_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180058001108ull))
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#define CVMX_TIM_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180058001110ull))
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#define CVMX_TIM_MEM_RING0 (CVMX_ADD_IO_SEG(0x0001180058001000ull))
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#define CVMX_TIM_MEM_RING1 (CVMX_ADD_IO_SEG(0x0001180058001008ull))
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#define CVMX_TIM_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000080ull))
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#define CVMX_TIM_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180058000088ull))
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#define CVMX_TIM_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180058000000ull))
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#define CVMX_TIM_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180058000090ull))
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#define CVMX_TIM_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180058000008ull))
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/**
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* cvmx_tim_mem_debug0
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*
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* Notes:
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* Internal per-ring state intended for debug use only - tim.ctl[47:0]
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* This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
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* CSR read operations to this address can be performed.
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*/
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union cvmx_tim_mem_debug0
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{
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uint64_t u64;
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struct cvmx_tim_mem_debug0_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_48_63 : 16;
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uint64_t ena : 1; /**< Ring timer enable */
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uint64_t reserved_46_46 : 1;
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uint64_t count : 22; /**< Time offset for the ring
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Set to INTERVAL and counts down by 1 every 1024
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cycles when ENA==1. The HW forces a bucket
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traversal (and resets COUNT to INTERVAL) whenever
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the decrement would cause COUNT to go negative.
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COUNT is unpredictable whenever ENA==0.
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COUNT is reset to INTERVAL whenever TIM_MEM_RING1
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is written for the ring. */
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uint64_t reserved_22_23 : 2;
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uint64_t interval : 22; /**< Timer interval - 1 */
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#else
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uint64_t interval : 22;
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uint64_t reserved_22_23 : 2;
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uint64_t count : 22;
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uint64_t reserved_46_46 : 1;
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uint64_t ena : 1;
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uint64_t reserved_48_63 : 16;
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#endif
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} s;
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struct cvmx_tim_mem_debug0_s cn30xx;
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struct cvmx_tim_mem_debug0_s cn31xx;
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struct cvmx_tim_mem_debug0_s cn38xx;
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struct cvmx_tim_mem_debug0_s cn38xxp2;
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struct cvmx_tim_mem_debug0_s cn50xx;
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struct cvmx_tim_mem_debug0_s cn52xx;
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struct cvmx_tim_mem_debug0_s cn52xxp1;
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struct cvmx_tim_mem_debug0_s cn56xx;
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struct cvmx_tim_mem_debug0_s cn56xxp1;
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struct cvmx_tim_mem_debug0_s cn58xx;
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struct cvmx_tim_mem_debug0_s cn58xxp1;
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struct cvmx_tim_mem_debug0_s cn63xx;
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struct cvmx_tim_mem_debug0_s cn63xxp1;
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};
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typedef union cvmx_tim_mem_debug0 cvmx_tim_mem_debug0_t;
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/**
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* cvmx_tim_mem_debug1
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*
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* Notes:
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* Internal per-ring state intended for debug use only - tim.sta[63:0]
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* This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
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* CSR read operations to this address can be performed.
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*/
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union cvmx_tim_mem_debug1
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{
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uint64_t u64;
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struct cvmx_tim_mem_debug1_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t bucket : 13; /**< Current bucket[12:0]
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Reset to 0 whenever TIM_MEM_RING0 is written for
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the ring. Incremented (modulo BSIZE) once per
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bucket traversal.
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See TIM_MEM_DEBUG2[BUCKET]. */
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uint64_t base : 31; /**< Pointer[35:5] to bucket[0] */
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uint64_t bsize : 20; /**< Number of buckets - 1 */
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#else
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uint64_t bsize : 20;
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uint64_t base : 31;
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uint64_t bucket : 13;
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#endif
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} s;
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struct cvmx_tim_mem_debug1_s cn30xx;
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struct cvmx_tim_mem_debug1_s cn31xx;
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struct cvmx_tim_mem_debug1_s cn38xx;
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struct cvmx_tim_mem_debug1_s cn38xxp2;
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struct cvmx_tim_mem_debug1_s cn50xx;
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struct cvmx_tim_mem_debug1_s cn52xx;
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struct cvmx_tim_mem_debug1_s cn52xxp1;
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struct cvmx_tim_mem_debug1_s cn56xx;
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struct cvmx_tim_mem_debug1_s cn56xxp1;
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struct cvmx_tim_mem_debug1_s cn58xx;
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struct cvmx_tim_mem_debug1_s cn58xxp1;
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struct cvmx_tim_mem_debug1_s cn63xx;
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struct cvmx_tim_mem_debug1_s cn63xxp1;
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};
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typedef union cvmx_tim_mem_debug1 cvmx_tim_mem_debug1_t;
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/**
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* cvmx_tim_mem_debug2
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*
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* Notes:
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* Internal per-ring state intended for debug use only - tim.sta[95:64]
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* This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
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* CSR read operations to this address can be performed.
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*/
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union cvmx_tim_mem_debug2
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{
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uint64_t u64;
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struct cvmx_tim_mem_debug2_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_24_63 : 40;
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uint64_t cpool : 3; /**< Free list used to free chunks */
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uint64_t csize : 13; /**< Number of words per chunk */
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uint64_t reserved_7_7 : 1;
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uint64_t bucket : 7; /**< Current bucket[19:13]
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See TIM_MEM_DEBUG1[BUCKET]. */
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#else
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uint64_t bucket : 7;
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uint64_t reserved_7_7 : 1;
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uint64_t csize : 13;
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uint64_t cpool : 3;
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uint64_t reserved_24_63 : 40;
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#endif
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} s;
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struct cvmx_tim_mem_debug2_s cn30xx;
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struct cvmx_tim_mem_debug2_s cn31xx;
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struct cvmx_tim_mem_debug2_s cn38xx;
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struct cvmx_tim_mem_debug2_s cn38xxp2;
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struct cvmx_tim_mem_debug2_s cn50xx;
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struct cvmx_tim_mem_debug2_s cn52xx;
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struct cvmx_tim_mem_debug2_s cn52xxp1;
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struct cvmx_tim_mem_debug2_s cn56xx;
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struct cvmx_tim_mem_debug2_s cn56xxp1;
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struct cvmx_tim_mem_debug2_s cn58xx;
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struct cvmx_tim_mem_debug2_s cn58xxp1;
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struct cvmx_tim_mem_debug2_s cn63xx;
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struct cvmx_tim_mem_debug2_s cn63xxp1;
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};
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typedef union cvmx_tim_mem_debug2 cvmx_tim_mem_debug2_t;
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/**
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* cvmx_tim_mem_ring0
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*
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* Notes:
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* TIM_MEM_RING0 must not be written for a ring when TIM_MEM_RING1[ENA] is set for the ring.
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* Every write to TIM_MEM_RING0 clears the current bucket for the ring. (The current bucket is
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* readable via TIM_MEM_DEBUG2[BUCKET],TIM_MEM_DEBUG1[BUCKET].)
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* BASE is a 32-byte aligned pointer[35:0]. Only pointer[35:5] are stored because pointer[4:0] = 0.
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* This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
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* CSR read operations to this address can be performed.
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*/
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union cvmx_tim_mem_ring0
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{
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uint64_t u64;
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struct cvmx_tim_mem_ring0_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_55_63 : 9;
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uint64_t first_bucket : 31; /**< Pointer[35:5] to bucket[0] */
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uint64_t num_buckets : 20; /**< Number of buckets - 1 */
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uint64_t ring : 4; /**< Ring ID */
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#else
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uint64_t ring : 4;
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uint64_t num_buckets : 20;
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uint64_t first_bucket : 31;
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uint64_t reserved_55_63 : 9;
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#endif
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} s;
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struct cvmx_tim_mem_ring0_s cn30xx;
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struct cvmx_tim_mem_ring0_s cn31xx;
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struct cvmx_tim_mem_ring0_s cn38xx;
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struct cvmx_tim_mem_ring0_s cn38xxp2;
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struct cvmx_tim_mem_ring0_s cn50xx;
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struct cvmx_tim_mem_ring0_s cn52xx;
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struct cvmx_tim_mem_ring0_s cn52xxp1;
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struct cvmx_tim_mem_ring0_s cn56xx;
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struct cvmx_tim_mem_ring0_s cn56xxp1;
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struct cvmx_tim_mem_ring0_s cn58xx;
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struct cvmx_tim_mem_ring0_s cn58xxp1;
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struct cvmx_tim_mem_ring0_s cn63xx;
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struct cvmx_tim_mem_ring0_s cn63xxp1;
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};
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typedef union cvmx_tim_mem_ring0 cvmx_tim_mem_ring0_t;
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/**
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* cvmx_tim_mem_ring1
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*
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* Notes:
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* After a 1->0 transition on ENA, the HW will still complete a bucket traversal for the ring
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* if it was pending or active prior to the transition. (SW must delay to ensure the completion
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* of the traversal before reprogramming the ring.)
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* Every write to TIM_MEM_RING1 resets the current time offset for the ring to the INTERVAL value.
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* (The current time offset for the ring is readable via TIM_MEM_DEBUG0[COUNT].)
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* CSIZE must be at least 16. It is illegal to program CSIZE to a value that is less than 16.
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* This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
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* CSR read operations to this address can be performed.
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*/
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union cvmx_tim_mem_ring1
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{
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uint64_t u64;
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struct cvmx_tim_mem_ring1_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_43_63 : 21;
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uint64_t enable : 1; /**< Ring timer enable
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When clear, the ring is disabled and TIM
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will not traverse any new buckets for the ring. */
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uint64_t pool : 3; /**< Free list used to free chunks */
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uint64_t words_per_chunk : 13; /**< Number of words per chunk */
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uint64_t interval : 22; /**< Timer interval - 1, measured in 1024 cycle ticks */
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uint64_t ring : 4; /**< Ring ID */
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#else
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uint64_t ring : 4;
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uint64_t interval : 22;
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uint64_t words_per_chunk : 13;
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uint64_t pool : 3;
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uint64_t enable : 1;
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uint64_t reserved_43_63 : 21;
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#endif
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} s;
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struct cvmx_tim_mem_ring1_s cn30xx;
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struct cvmx_tim_mem_ring1_s cn31xx;
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struct cvmx_tim_mem_ring1_s cn38xx;
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struct cvmx_tim_mem_ring1_s cn38xxp2;
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struct cvmx_tim_mem_ring1_s cn50xx;
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struct cvmx_tim_mem_ring1_s cn52xx;
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struct cvmx_tim_mem_ring1_s cn52xxp1;
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struct cvmx_tim_mem_ring1_s cn56xx;
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struct cvmx_tim_mem_ring1_s cn56xxp1;
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struct cvmx_tim_mem_ring1_s cn58xx;
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struct cvmx_tim_mem_ring1_s cn58xxp1;
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struct cvmx_tim_mem_ring1_s cn63xx;
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struct cvmx_tim_mem_ring1_s cn63xxp1;
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};
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typedef union cvmx_tim_mem_ring1 cvmx_tim_mem_ring1_t;
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/**
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* cvmx_tim_reg_bist_result
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*
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* Notes:
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* Access to the internal BiST results
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* Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
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*/
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union cvmx_tim_reg_bist_result
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{
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uint64_t u64;
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struct cvmx_tim_reg_bist_result_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_4_63 : 60;
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uint64_t sta : 2; /**< BiST result of the STA memories (0=pass, !0=fail) */
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uint64_t ncb : 1; /**< BiST result of the NCB memories (0=pass, !0=fail) */
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uint64_t ctl : 1; /**< BiST result of the CTL memories (0=pass, !0=fail) */
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#else
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uint64_t ctl : 1;
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uint64_t ncb : 1;
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uint64_t sta : 2;
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uint64_t reserved_4_63 : 60;
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#endif
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} s;
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struct cvmx_tim_reg_bist_result_s cn30xx;
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struct cvmx_tim_reg_bist_result_s cn31xx;
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struct cvmx_tim_reg_bist_result_s cn38xx;
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struct cvmx_tim_reg_bist_result_s cn38xxp2;
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struct cvmx_tim_reg_bist_result_s cn50xx;
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struct cvmx_tim_reg_bist_result_s cn52xx;
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struct cvmx_tim_reg_bist_result_s cn52xxp1;
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struct cvmx_tim_reg_bist_result_s cn56xx;
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struct cvmx_tim_reg_bist_result_s cn56xxp1;
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struct cvmx_tim_reg_bist_result_s cn58xx;
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struct cvmx_tim_reg_bist_result_s cn58xxp1;
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struct cvmx_tim_reg_bist_result_s cn63xx;
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struct cvmx_tim_reg_bist_result_s cn63xxp1;
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};
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typedef union cvmx_tim_reg_bist_result cvmx_tim_reg_bist_result_t;
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/**
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* cvmx_tim_reg_error
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*
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* Notes:
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* A ring is in error if its interval has elapsed more than once without having been serviced.
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* During a CSR write to this register, the write data is used as a mask to clear the selected mask
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* bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]).
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*/
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union cvmx_tim_reg_error
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{
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uint64_t u64;
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struct cvmx_tim_reg_error_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_16_63 : 48;
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uint64_t mask : 16; /**< Bit mask indicating the rings in error */
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#else
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uint64_t mask : 16;
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uint64_t reserved_16_63 : 48;
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#endif
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} s;
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struct cvmx_tim_reg_error_s cn30xx;
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struct cvmx_tim_reg_error_s cn31xx;
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struct cvmx_tim_reg_error_s cn38xx;
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struct cvmx_tim_reg_error_s cn38xxp2;
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struct cvmx_tim_reg_error_s cn50xx;
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struct cvmx_tim_reg_error_s cn52xx;
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struct cvmx_tim_reg_error_s cn52xxp1;
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struct cvmx_tim_reg_error_s cn56xx;
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struct cvmx_tim_reg_error_s cn56xxp1;
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struct cvmx_tim_reg_error_s cn58xx;
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struct cvmx_tim_reg_error_s cn58xxp1;
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struct cvmx_tim_reg_error_s cn63xx;
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struct cvmx_tim_reg_error_s cn63xxp1;
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};
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typedef union cvmx_tim_reg_error cvmx_tim_reg_error_t;
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/**
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* cvmx_tim_reg_flags
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*
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* Notes:
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* TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all
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* rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.)
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* When ENA_TIM==0, the HW stops this shared periodic counter, so there are no more ticks, and there
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* are no more new bucket traversals (for any ring).
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*
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* If ENA_TIM transitions 1->0, TIM will no longer create new bucket traversals, but there may
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* have been previous ones. If there are ring bucket traversals that were already pending but
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* not currently active (i.e. bucket traversals that need to be done by the HW, but haven't been yet)
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* during this ENA_TIM 1->0 transition, then these bucket traversals will remain pending until
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* ENA_TIM is later set to one. Bucket traversals that were already in progress will complete
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* after the 1->0 ENA_TIM transition, though.
|
|
*/
|
|
union cvmx_tim_reg_flags
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_tim_reg_flags_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_3_63 : 61;
|
|
uint64_t reset : 1; /**< Reset oneshot pulse for free-running structures */
|
|
uint64_t enable_dwb : 1; /**< Enables non-zero DonwWriteBacks when set
|
|
When set, enables the use of
|
|
DontWriteBacks during the buffer freeing
|
|
operations. */
|
|
uint64_t enable_timers : 1; /**< Enables the TIM section when set
|
|
When set, TIM is in normal operation.
|
|
When clear, time is effectively stopped for all
|
|
rings in TIM. */
|
|
#else
|
|
uint64_t enable_timers : 1;
|
|
uint64_t enable_dwb : 1;
|
|
uint64_t reset : 1;
|
|
uint64_t reserved_3_63 : 61;
|
|
#endif
|
|
} s;
|
|
struct cvmx_tim_reg_flags_s cn30xx;
|
|
struct cvmx_tim_reg_flags_s cn31xx;
|
|
struct cvmx_tim_reg_flags_s cn38xx;
|
|
struct cvmx_tim_reg_flags_s cn38xxp2;
|
|
struct cvmx_tim_reg_flags_s cn50xx;
|
|
struct cvmx_tim_reg_flags_s cn52xx;
|
|
struct cvmx_tim_reg_flags_s cn52xxp1;
|
|
struct cvmx_tim_reg_flags_s cn56xx;
|
|
struct cvmx_tim_reg_flags_s cn56xxp1;
|
|
struct cvmx_tim_reg_flags_s cn58xx;
|
|
struct cvmx_tim_reg_flags_s cn58xxp1;
|
|
struct cvmx_tim_reg_flags_s cn63xx;
|
|
struct cvmx_tim_reg_flags_s cn63xxp1;
|
|
};
|
|
typedef union cvmx_tim_reg_flags cvmx_tim_reg_flags_t;
|
|
|
|
/**
|
|
* cvmx_tim_reg_int_mask
|
|
*
|
|
* Notes:
|
|
* Note that this CSR is present only in chip revisions beginning with pass2.
|
|
* When mask bit is set, the interrupt is enabled.
|
|
*/
|
|
union cvmx_tim_reg_int_mask
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_tim_reg_int_mask_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_16_63 : 48;
|
|
uint64_t mask : 16; /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */
|
|
#else
|
|
uint64_t mask : 16;
|
|
uint64_t reserved_16_63 : 48;
|
|
#endif
|
|
} s;
|
|
struct cvmx_tim_reg_int_mask_s cn30xx;
|
|
struct cvmx_tim_reg_int_mask_s cn31xx;
|
|
struct cvmx_tim_reg_int_mask_s cn38xx;
|
|
struct cvmx_tim_reg_int_mask_s cn38xxp2;
|
|
struct cvmx_tim_reg_int_mask_s cn50xx;
|
|
struct cvmx_tim_reg_int_mask_s cn52xx;
|
|
struct cvmx_tim_reg_int_mask_s cn52xxp1;
|
|
struct cvmx_tim_reg_int_mask_s cn56xx;
|
|
struct cvmx_tim_reg_int_mask_s cn56xxp1;
|
|
struct cvmx_tim_reg_int_mask_s cn58xx;
|
|
struct cvmx_tim_reg_int_mask_s cn58xxp1;
|
|
struct cvmx_tim_reg_int_mask_s cn63xx;
|
|
struct cvmx_tim_reg_int_mask_s cn63xxp1;
|
|
};
|
|
typedef union cvmx_tim_reg_int_mask cvmx_tim_reg_int_mask_t;
|
|
|
|
/**
|
|
* cvmx_tim_reg_read_idx
|
|
*
|
|
* Notes:
|
|
* Provides the read index during a CSR read operation to any of the CSRs that are physically stored
|
|
* as memories. The names of these CSRs begin with the prefix "TIM_MEM_".
|
|
* IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
|
|
* The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire
|
|
* contents of a CSR memory can be read with consecutive CSR read commands.
|
|
*/
|
|
union cvmx_tim_reg_read_idx
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_tim_reg_read_idx_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_16_63 : 48;
|
|
uint64_t inc : 8; /**< Increment to add to current index for next index */
|
|
uint64_t index : 8; /**< Index to use for next memory CSR read */
|
|
#else
|
|
uint64_t index : 8;
|
|
uint64_t inc : 8;
|
|
uint64_t reserved_16_63 : 48;
|
|
#endif
|
|
} s;
|
|
struct cvmx_tim_reg_read_idx_s cn30xx;
|
|
struct cvmx_tim_reg_read_idx_s cn31xx;
|
|
struct cvmx_tim_reg_read_idx_s cn38xx;
|
|
struct cvmx_tim_reg_read_idx_s cn38xxp2;
|
|
struct cvmx_tim_reg_read_idx_s cn50xx;
|
|
struct cvmx_tim_reg_read_idx_s cn52xx;
|
|
struct cvmx_tim_reg_read_idx_s cn52xxp1;
|
|
struct cvmx_tim_reg_read_idx_s cn56xx;
|
|
struct cvmx_tim_reg_read_idx_s cn56xxp1;
|
|
struct cvmx_tim_reg_read_idx_s cn58xx;
|
|
struct cvmx_tim_reg_read_idx_s cn58xxp1;
|
|
struct cvmx_tim_reg_read_idx_s cn63xx;
|
|
struct cvmx_tim_reg_read_idx_s cn63xxp1;
|
|
};
|
|
typedef union cvmx_tim_reg_read_idx cvmx_tim_reg_read_idx_t;
|
|
|
|
#endif
|