6fd807e4f4
Host ATM Research Platform (HARP), Network Computing Services, Inc. This software was developed with the support of the Defense Advanced Research Projects Agency (DARPA).
500 lines
16 KiB
C
500 lines
16 KiB
C
/*
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*
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* ===================================
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* HARP | Host ATM Research Platform
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* ===================================
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*
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*
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* This Host ATM Research Platform ("HARP") file (the "Software") is
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* made available by Network Computing Services, Inc. ("NetworkCS")
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* "AS IS". NetworkCS does not provide maintenance, improvements or
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* support of any kind.
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*
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* NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
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* INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
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* SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
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* In no event shall NetworkCS be responsible for any damages, including
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* but not limited to consequential damages, arising from or relating to
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* any use of the Software or related support.
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*
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* Copyright 1994-1998 Network Computing Services, Inc.
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*
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* Copies of this Software may be made, however, the above copyright
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* notice must be reproduced on all copies.
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*
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* @(#) $Id: eni.h,v 1.7 1998/06/29 19:45:14 jpt Exp $
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*
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*/
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/*
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* Efficient ENI Adapter Support
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*
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* Protocol and implementation definitions
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*
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*/
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#ifndef _ENI_ENI_H
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#define _ENI_ENI_H
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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/*
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* Physical device name - used to configure HARP devices
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*/
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#ifndef ENI_DEV_NAME
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#define ENI_DEV_NAME "hea" /* HARP Efficient ATM */
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#endif
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#define ENI_MAX_UNITS 4
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#define ENI_IFF_MTU 9188
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#define ENI_MAX_VCI 1023 /* 0 - 1023 */
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#define ENI_MAX_VPI 0
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#define ENI_IFQ_MAXLEN 1000 /* rx/tx queue lengths */
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#ifdef BSD
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/*
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* Size of small and large receive buffers
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*/
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#define ENI_SMALL_BSIZE 64
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#define ENI_LARGE_BSIZE MCLBYTES
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#endif /* BSD */
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/*
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* ENI memory map offsets IN WORDS, not bytes
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*
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* The Efficient Adapter implements a 4 MB address space. The lower
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* 2 MB are used by bootprom (E)EPROM and by chipset registers such
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* as the MIDWAY and SUNI chips. The (upto) upper 2 MB is used for
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* RAM. Of the RAM, the lower 28 KB is used for fixed tables - the
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* VCI table, the RX and TX DMA queues, and the Service List queue.
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* Memory above the 28 KB range is available for RX and TX buffers.
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*
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* NOTE: Access to anything other then the (E)EPROM MUST be as a 32 bit
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* access. Also note that Efficient uses both byte addresses and word
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* addresses when describing offsets. BE CAREFUL or you'll get confused!
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*/
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/*
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* Size of memory space reserved for registers and expansion (e)eprom.
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*/
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#define ENI_REG_SIZE 0x200000 /* Two megabytes */
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#define SUNI_OFFSET 0x008000 /* SUNI chip registers */
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#define MIDWAY_OFFSET 0x010000 /* MIDWAY chip registers */
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#define RAM_OFFSET 0x080000 /* Adapter RAM */
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#define VCITBL_OFFSET 0x080000 /* VCI Table offset */
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#define RXQUEUE_OFFSET 0x081000 /* RX DMA Queue offset */
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#define TXQUEUE_OFFSET 0x081400 /* TX DMA Queue offset */
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#define SVCLIST_OFFSET 0x081800 /* SVC List Queue offset */
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#define SEGBUF_BASE 0x007000 /* Base from start of RAM */
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#define DMA_LIST_SIZE 512 /* 1024 words / 2 words per entry */
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#define SVC_LIST_SIZE 1024 /* 1024 words / 1 word per entry */
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/*
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* Values for testing size of RAM on adapter
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*
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* Efficient has (at least) two different memory sizes available. One
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* is a client card which has either 128 KB or 512 KB RAM, the other
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* is a server card which has 2 MB RAM. The driver will size and test
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* the memory to correctly determine what's available.
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*/
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#define MAX_ENI_MEM 0x200000 /* 2 MB - max. mem supported */
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#define TEST_STEP 0x000400 /* Look at 1 KB steps */
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#define TEST_PAT 0xA5A5A5A5 /* Test pattern */
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/*
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* Values for memory allocator
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*/
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#define ENI_BUF_PGSZ 1024 /* Allocation unit of buffers */
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#define ENI_BUF_NBIT 8 /* Number of bits to get from */
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/* min buffer (1KB) to max (128KB) */
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/*
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* Values for allocating TX buffers
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*/
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#define MAX_CLIENT_RAM 512 /* Most RAM a client card will have */
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#define TX_SMALL_BSIZE 32 /* Small buffer - 32KB */
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#define TX_LARGE_BSIZE 128 /* Large buffer - 128KB */
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/*
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* Values for allocating RX buffers
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*/
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#define RX_SIG_BSIZE 4 /* Signalling buffer - 4KB */
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#define RX_CLIENT_BSIZE 16 /* Client buffer - 16KB */
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#define RX_SERVER_BSIZE 32 /* Server buffer - 32KB */
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/*
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* Adapter bases all addresses off of some power from 1KB. Thus, it
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* only needs to store the most sigificant bits and can drop the lower
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* 10 bits.
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*/
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#define ENI_LOC_PREDIV 10 /* Bits location is shifted */
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/* Location is prescaled by 1KB */
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/* before use in various places */
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#define MIDWAY_DELAY 10 /* Time to wait for Midway finish */
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/*
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* Define the MIDWAY register offsets and any interesting bits within
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* the register
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*/
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#define MIDWAY_ID 0x00 /* ID/Reset register */
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#define MIDWAY_RESET 0 /* iWrite of any value */
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#define ID_SHIFT 27 /* Midway ID version */
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#define ID_MASK 0x1F /* ID mask */
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#define MID_SHIFT 7 /* Mother board ID */
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#define MID_MASK 0x7 /* MID mask */
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#define DID_SHIFT 0 /* Daughter board ID */
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#define DID_MASK 0x1F /* DID mask */
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/*
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* Efficient defines the following IDs for their adapters:
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* 0x420/0x620 - SONET MMF, client memory size
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* 0x430/0x630 - SONET MMF, server memory size
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* 0x424/0x624 - UTP-5, client memory size
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* 0x434/0x634 - UTP-5, server memory size
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*/
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#define MEDIA_MASK 0x04 /* Mask off UTP-5/MMF media */
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#define MIDWAY_ISA 0x01 /* Interrupt Status Ack. */
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/* Reading this register */
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/* also acknowledges the */
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/* posted interrupt(s) */
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#define MIDWAY_IS 0x02 /* Interrupt Status */
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/* Reading this register */
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/* does NOT acknowledge the */
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/* posted interrupt(s) */
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/* Interrupt names */
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#define ENI_INT_STAT 0x00000001
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#define ENI_INT_SUNI 0x00000002
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#define ENI_INT_SERVICE 0x00000004
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#define ENI_INT_TX_DMA 0x00000008
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#define ENI_INT_RX_DMA 0x00000010
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#define ENI_INT_DMA_ERR 0x00000020
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#define ENI_INT_DMA_LERR 0x00000040
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#define ENI_INT_IDEN 0x00000080
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#define ENI_INT_DMA_OVFL 0x00000100
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#define ENI_INT_TX_MASK 0x0001FE00
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#define MIDWAY_IE 0x03 /* Interrupt Enable register */
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/* Interrupt enable bits are the same as the Interrupt names */
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#define MIDWAY_MASTER 0x04 /* Master Control */
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/* Master control bits */
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#define ENI_M_WAIT500 0x00000001 /* Disable interrupts .5 ms */
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#define ENI_M_WAIT1 0x00000002 /* Disable interrupts 1 ms */
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#define ENI_M_RXENABLE 0x00000004 /* Enable RX engine */
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#define ENI_M_TXENABLE 0x00000008 /* Enable TX engine */
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#define ENI_M_DMAENABLE 0x00000010 /* Enable DMA */
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#define ENI_M_TXLOCK 0x00000020 /* 0: Streaming, 1: Lock */
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#define ENI_M_INTSEL 0x000001C0 /* Int Select mask */
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#define ENI_ISEL_SHIFT 6 /* Bits to shift ISEL value */
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#define MIDWAY_STAT 0x05 /* Statistics register */
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#define MIDWAY_SVCWR 0x06 /* Svc List write pointer */
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#define SVC_SIZE_MASK 0x3FF /* Valid bits in svc pointer */
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#define MIDWAY_DMAADDR 0x07 /* Current virtual DMA addr */
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#define MIDWAY_RX_WR 0x08 /* Write ptr to RX DMA queue */
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#define MIDWAY_RX_RD 0x09 /* Read ptr to RX DMA queue */
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#define MIDWAY_TX_WR 0x0A /* Write ptr to TX DMA queue */
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#define MIDWAY_TX_RD 0x0B /* Read ptr to TX DMA queue */
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/*
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* Registers 0x0C - 0x0F are unused
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*/
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/*
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* MIDWAY supports 8 transmit channels. Each channel has 3 registers
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* to control operation. Each new channel starts on N * 4 set. Thus,
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* channel 0 uses register 0x10 - 0x13, channel 1 uses 0x14 - 0x17, etc.
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* Register 0x13 + N * 4 is unused.
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*/
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#define MIDWAY_TXPLACE 0x10 /* Channel N TX location */
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#define TXSIZE_SHIFT 11 /* Bits to shift size by */
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#define TX_PLACE_MASK 0x7FF /* Valid bits in TXPLACE */
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#define MIDWAY_RDPTR 0x11 /* Channel N Read ptr */
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#define MIDWAY_DESCR 0x12 /* Channel N Descr ptr */
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/*
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* Register 0x30 on up are unused
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*/
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/*
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* Part of PCI configuration registers but not defined in <pci/pcireg.h>
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*/
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#define PCI_CONTROL_REG 0x60
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#define ENDIAN_SWAP_DMA 0x80 /* Enable endian swaps on DMA */
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/*
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* The Efficient adapter references adapter RAM through the use of
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* location and size values. Eight sizes are defined. When allocating
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* buffers, there size must be rounded up to the next size which will
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* hold the requested size. Buffers are allocated on 'SIZE' boundaries.
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* See eni_buffer.c for more info.
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*/
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/*
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* Buffer SIZE definitions - in words, so from 1 KB to 128 KB
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*/
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#define SIZE_256 0x00
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#define SIZE_512 0x01
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#define SIZE_1K 0x02
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#define SIZE_2K 0x03
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#define SIZE_4K 0x04
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#define SIZE_8K 0x05
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#define SIZE_16K 0x06
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#define SIZE_32K 0x07
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/*
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* Define values for DMA type - DMA descriptors include a type field and a
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* count field except in the special case of JK (just-kidding). With type JK,
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* the count field should be set to the address which will be loaded
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* into the pointer, ie. where the pointer should next point to, since
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* JK doesn't have a "size" associated with it. JK DMA is used to skip
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* over descriptor words, and to strip off padding of AAL5 PDUs. The
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* DMA_nWORDM types will do a n word DMA burst, but the count field
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* does not have to equal n. Any difference results in garbage filling
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* the remaining words of the DMA. These types could be used where a
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* particular burst size yields better DMA performance.
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*/
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#define DMA_WORD 0x00
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#define DMA_BYTE 0x01
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#define DMA_HWORD 0x02
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#define DMA_JK 0x03
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#define DMA_4WORD 0x04
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#define DMA_8WORD 0x05
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#define DMA_16WORD 0x06
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#define DMA_2WORD 0x07
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#define DMA_4WORDM 0x0C
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#define DMA_8WORDM 0x0D
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#define DMA_16WORDM 0x0E
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#define DMA_2WORDM 0x0F
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/*
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* Define the size of the local DMA list we'll build before
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* giving up on the PDU.
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*/
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#define TEMP_DMA_SIZE 120 /* Enough for 58/59 buffers */
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#define DMA_COUNT_SHIFT 16 /* Number of bits to shift count */
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/* in DMA descriptor word */
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#define DMA_VCC_SHIFT 6 /* Number of bits to shift RX VCC or */
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/* TX channel in DMA descriptor word */
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#define DMA_END_BIT 0x20 /* Signal end of DMA list */
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/*
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* Defines for VCI table
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*
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* The VCI table is a 1K by 4 word table allowing up to 1024 (0-1023)
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* VCIs. Entries into the table use the VCI number as the index.
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*/
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struct vci_table {
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u_long vci_control; /* Control word */
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u_long vci_descr; /* Descr/ReadPtr */
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u_long vci_write; /* WritePtr/State/Cell count */
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u_long vci_crc; /* ongoing CRC calculation */
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};
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typedef volatile struct vci_table VCI_Table;
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#define VCI_MODE_SHIFT 30 /* Shift to get MODE field */
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#define VCI_MODE_MASK 0x3FFFFFFF /* Bits to strip MODE off */
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#define VCI_PTI_SHIFT 29 /* Shift to get PTI mode field */
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#define VCI_LOC_SHIFT 18 /* Shift to get location field */
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#define VCI_LOC_MASK 0x7FF /* Valid bits in location field */
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#define VCI_SIZE_SHIFT 15 /* Shift to get size field */
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#define VCI_SIZE_MASK 7 /* Valid bits in size field */
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#define VCI_IN_SERVICE 1 /* Mask for IN_SERVICE field */
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/*
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* Defines for VC mode
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*/
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#define VCI_MODE_TRASH 0x00 /* Trash all cells for this VC */
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#define VCI_MODE_AAL0 0x01 /* Reassemble as AAL_0 PDU */
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#define VCI_MODE_AAL5 0x02 /* Reassemble as AAL_5 PDU */
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/*
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* Defines for handling cells with PTI(2) set to 1.
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*/
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#define PTI_MODE_TRASH 0x00 /* Trash cell */
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#define PTI_MODE_PRESV 0x01 /* Send cell to OAM channel */
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/*
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* Current state of VC
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*/
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#define VCI_STATE_IDLE 0x00 /* VC is idle */
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#define VCI_STATE_REASM 0x01 /* VC is reassembling PDU */
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#define VCI_STATE_TRASH 0x03 /* VC is trashing cells */
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/*
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* RX Descriptor word values
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*/
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#define DESCR_TRASH_BIT 0x1000 /* VCI was trashing cells */
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#define DESCR_CRC_ERR 0x0800 /* PDU has CRC error */
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#define DESCR_CELL_COUNT 0x07FF /* Mask to get cell count */
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/*
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* TX Descriptor word values
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*/
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#define TX_IDEN_SHIFT 28 /* Unique identifier location */
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#define TX_MODE_SHIFT 27 /* AAL5 or AAL0 */
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#define TX_VCI_SHIFT 4 /* Bits to shift VCI value */
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/*
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* When setting up descriptor words (at head of segmentation queues), there
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* is a unique identifier used to help detect sync problems.
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*/
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#define MIDWAY_UNQ_ID 0x0B
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/*
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* Defines for cell sizes
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*/
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#define BYTES_PER_CELL 48 /* Number of data bytes per cell */
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#define WORDS_PER_CELL 12 /* Number of data words per cell */
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/*
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* Access to Serial EEPROM [as opposed to expansion (E)PROM].
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*
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* This is a ATMEL AT24C01 serial EEPROM part.
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* See http://www.atmel.com/atmel/products/prod162.htm for timimg diagrams
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* for START/STOP/ACK/READ cycles.
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*/
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#define SEEPROM PCI_CONTROL_REG /* Serial EEPROM is accessed thru */
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/* PCI control register */
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#define SEPROM_DATA 0x02 /* SEEPROM DATA line */
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#define SEPROM_CLK 0x01 /* SEEPROM CLK line */
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#define SEPROM_SIZE 128 /* Size of Serial EEPROM */
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#define SEPROM_MAC_OFF 64 /* Offset to MAC address */
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#define SEPROM_SN_OFF 112 /* Offset to serial number */
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#define SEPROM_DELAY 10 /* Delay when strobing CLK/DATA lines */
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/*
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* Host protocol control blocks
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*
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*/
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/*
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* Device VCC Entry
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*
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* Contains the common and ENI-specific information for each VCC
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* which is opened through a ENI device.
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*/
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struct eni_vcc {
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struct cmn_vcc ev_cmn; /* Common VCC stuff */
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caddr_t ev_rxbuf; /* Receive buffer */
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u_long ev_rxpos; /* Adapter buffer read pointer */
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};
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typedef struct eni_vcc Eni_vcc;
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#define ev_next ev_cmn.cv_next
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#define ev_toku ev_cmn.cv_toku
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#define ev_upper ev_cmn.cv_upper
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#define ev_connvc ev_cmn.cv_connvc
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#define ev_state ev_cmn.cv_state
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typedef volatile unsigned long * Eni_mem;
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/*
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* Define the ID's we'll look for in the PCI config
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* register when deciding if we'll support this device.
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* The DEV_ID will need to be turned into an array of
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* ID's in order to support multiple adapters with
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* the same driver.
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*/
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#define EFF_VENDOR_ID 0x111A
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#define EFF_DEV_ID 0x0002
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/*
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* Memory allocator defines and buffer descriptors
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*/
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#define MEM_FREE 0
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#define MEM_INUSE 1
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typedef struct mbd Mbd;
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struct mbd {
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Mbd *prev;
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Mbd *next;
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caddr_t base; /* Adapter base address */
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int size; /* Size of buffer */
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int state; /* INUSE or FREE */
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};
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/*
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* We use a hack to allocate a smaller RX buffer for signalling
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* channels as they tend to have small MTU lengths.
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*/
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#define UNI_SIG_VCI 5
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/*
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* Device Unit Structure
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*
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* Contains all the information for a single device (adapter).
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*/
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struct eni_unit {
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Cmn_unit eu_cmn; /* Common unit stuff */
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pcici_t eu_pcitag; /* PCI tag */
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Eni_mem eu_base; /* Adapter memory base */
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Eni_mem eu_ram; /* Adapter RAM */
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u_long eu_ramsize;
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Eni_mem eu_suni; /* SUNI registers */
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Eni_mem eu_midway; /* MIDWAY registers */
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VCI_Table *eu_vcitbl; /* VCI Table */
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Eni_mem eu_rxdma; /* Receive DMA queue */
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Eni_mem eu_txdma; /* Transmit DMA queue */
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Eni_mem eu_svclist; /* Service list */
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u_long eu_servread; /* Read pointer into Service list */
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caddr_t eu_txbuf; /* One large TX buff for everything */
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u_long eu_txsize; /* Size of TX buffer */
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u_long eu_txpos; /* Current word being stored in RAM */
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u_long eu_txfirst; /* First word of unack'ed data */
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u_long eu_trash;
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u_long eu_ovfl;
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struct ifqueue eu_txqueue;
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u_long eu_txdmawr;
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struct ifqueue eu_rxqueue;
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u_long eu_rxdmawr; /* DMA list write pointer */
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u_char eu_seeprom[SEPROM_SIZE]; /* Serial EEPROM contents */
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u_int eu_sevar; /* Unique (per unit) seeprom var. */
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Mbd *eu_memmap; /* Adapter RAM memory allocator map */
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int eu_memclicks[ENI_BUF_NBIT];/* Count of INUSE buffers */
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Eni_stats eu_stats; /* Statistics */
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};
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typedef struct eni_unit Eni_unit;
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#define eu_pif eu_cmn.cu_pif
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#define eu_unit eu_cmn.cu_unit
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#define eu_flags eu_cmn.cu_flags
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#define eu_mtu eu_cmn.cu_mtu
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#define eu_open_vcc eu_cmn.cu_open_vcc
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#define eu_vcc eu_cmn.cu_vcc
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#define eu_vcc_pool eu_cmn.cu_vcc_pool
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#define eu_nif_pool eu_cmn.cu_nif_pool
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#define eu_ioctl eu_cmn.cu_ioctl
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#define eu_instvcc eu_cmn.cu_instvcc
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#define eu_openvcc eu_cmn.cu_openvcc
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#define eu_closevcc eu_cmn.cu_closevcc
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#define eu_output eu_cmn.cu_output
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#define eu_config eu_cmn.cu_config
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#endif /* _ENI_ENI_H */
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