45cd4c8cef
fully-pessimized implementation that requires a type to be aligned to its natural size. On armv6+ the compiler might generate load-/store-multiple instructions which require 4-byte alignment even though the source code is only accessing individual uint32_t values in a way that doesn't require any particular alignment at all. The compiler apparently feels free to combine multiple accesses into a single instruction that requires a more-strict alignment, and no set of compiler flags seems to disable this behavior (at least in clang 3.8). This fixes alignment faults on arm systems using wifi adapters. The wifi code uses ALIGNED_POINTER(p, uint32_t) to decide whether it needs to copy-align tcp headers. Because clang is combining several uint32_t accesses into a single ldm instruction, we need to say that accessing a uint32_t requires 4-byte alignment. Approved by: re(gjb) |
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| .. | ||
| allwinner | ||
| altera/socfpga | ||
| amlogic/aml8726 | ||
| annapurna/alpine | ||
| arm | ||
| at91 | ||
| broadcom/bcm2835 | ||
| cavium/cns11xx | ||
| conf | ||
| freescale | ||
| include | ||
| lpc | ||
| mv | ||
| nvidia | ||
| qemu | ||
| rockchip | ||
| samsung/exynos | ||
| ti | ||
| versatile | ||
| xilinx | ||
| xscale | ||