117 lines
3.1 KiB
C
117 lines
3.1 KiB
C
/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_RISCV_OPCODE_H_
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#define _MACHINE_RISCV_OPCODE_H_
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/*
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* Define the instruction formats and opcode values for the
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* RISC-V instruction set.
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*/
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#include <machine/endian.h>
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/*
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* Define the instruction formats.
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*/
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typedef union {
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unsigned word;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 5;
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unsigned funct7: 7;
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} RType;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 6;
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unsigned funct7: 6;
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} R2Type;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned imm: 12;
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} IType;
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struct {
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unsigned opcode: 7;
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unsigned imm0_4: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 5;
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unsigned imm5_11: 7;
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} SType;
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struct {
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unsigned opcode: 7;
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unsigned imm11: 1;
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unsigned imm1_4: 4;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 5;
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unsigned imm5_10: 6;
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unsigned imm12: 1;
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} SBType;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned imm12_31: 20;
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} UType;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned imm12_19: 8;
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unsigned imm11: 1;
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unsigned imm1_10: 10;
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unsigned imm20: 1;
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} UJType;
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} InstFmt;
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#define RISCV_OPCODE(r) (r & 0x7f)
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#endif /* !_MACHINE_RISCV_OPCODE_H_ */
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