f71ac6d60a
controllers may be configured as legacy IDE mode by modifying subclass and progif without actually changing PCI device IDs. Instead of complicating code, we always force AHCI mode while probing. Also we restore AHCI mode while resuming per ATI/AMD register programming/requirement guides. - Fix SB700/800 "combined" mode. Unlike SB600, this PATA controller can combine two SATA ports and emulate one PATA channel as primary or secondary depending on BIOS configuration. When the combined mode is disabled, this channel disappears and it works just like SB600 PATA controller, however. - Add more PCI device IDs for SB700/800 and adjust device descriptions. SB800 shares the same PCI device IDs and added two more SATA IDs.
262 lines
8.3 KiB
C
262 lines
8.3 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/pciio.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_ati_chipinit(device_t dev);
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static void ata_ati_setmode(device_t dev, int mode);
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static void ata_ati_ahci_enable(device_t dev);
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static int ata_ati_ahci_chipinit(device_t dev);
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static int ata_ati_ahci_resume(device_t dev);
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/* misc defines */
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#define ATI_PATA 0x01
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#define ATI_SATA 0x02
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#define ATI_AHCI 0x04
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#define SII_MEMIO 1
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#define SII_BUG 0x04
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/* Misc Control Register */
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#define ATI_PCI_MISC_CTRL 0x40
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#define ATI_PCI_MISCCTRL_ENABLE_WR 0x00000001
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/* Watchdog Control/Status Register */
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#define ATI_PCI_WD_CTRL 0x44
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#define ATI_PCI_WDCTRL_ENABLE 0x0001
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/*
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* ATI chipset support functions
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*/
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static int
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ata_ati_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static struct ata_chip_id ids[] =
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{{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" },
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{ ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" },
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{ ATA_ATI_IXP300_S1, 0x00, ATI_SATA, 0, ATA_SA150, "IXP300" },
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{ ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" },
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{ ATA_ATI_IXP400_S1, 0x00, ATI_SATA, 0, ATA_SA150, "IXP400" },
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{ ATA_ATI_IXP400_S2, 0x00, ATI_SATA, 0, ATA_SA150, "IXP400" },
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{ ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" },
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{ ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" },
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{ ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" },
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{ ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
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{ ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
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{ ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
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{ ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
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{ ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
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{ ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
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{ 0, 0, 0, 0, 0, 0}};
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if (pci_get_vendor(dev) != ATA_ATI_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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switch (ctlr->chip->cfg1) {
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case ATI_PATA:
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ctlr->chipinit = ata_ati_chipinit;
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break;
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case ATI_SATA:
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/*
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* the ATI SATA controller is actually a SiI 3112 controller
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* cfg values below much match those in ata-siliconimage.c
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*/
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ctlr->chip->cfg1 = SII_MEMIO;
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ctlr->chip->cfg2 = SII_BUG;
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ctlr->chipinit = ata_sii_chipinit;
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break;
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case ATI_AHCI:
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/*
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* Force AHCI mode if IDE mode is set from BIOS.
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*/
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if ((ctlr->chip->chipid == ATA_ATI_IXP600_S1 ||
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ctlr->chip->chipid == ATA_ATI_IXP700_S1) &&
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pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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cfg->subclass = PCIS_STORAGE_SATA;
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cfg->progif = PCIP_STORAGE_SATA_AHCI_1_0;
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ata_ati_ahci_enable(dev);
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}
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ctlr->chipinit = ata_ati_ahci_chipinit;
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break;
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}
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return 0;
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}
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static int
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ata_ati_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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/* IXP600 only has 1 PATA channel */
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if (ctlr->chip->chipid == ATA_ATI_IXP600)
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ctlr->channels = 1;
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ctlr->setmode = ata_ati_setmode;
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return 0;
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}
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static void
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ata_ati_setmode(device_t dev, int mode)
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{
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device_t gparent = GRANDPARENT(dev);
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struct ata_pci_controller *ctlr = device_get_softc(gparent);
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struct ata_channel *ch = device_get_softc(device_get_parent(dev));
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struct ata_device *atadev = device_get_softc(dev);
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int devno = (ch->unit << 1) + atadev->unit;
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int offset = (devno ^ 0x01) << 3;
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int error;
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u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
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u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
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mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
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mode = ata_check_80pin(dev, mode);
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error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
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if (bootverbose)
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device_printf(dev, "%ssetting %s on %s chip\n",
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(error) ? "FAILURE " : "",
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ata_mode2str(mode), ctlr->chip->text);
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if (!error) {
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if (mode >= ATA_UDMA0) {
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pci_write_config(gparent, 0x56,
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(pci_read_config(gparent, 0x56, 2) &
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~(0xf << (devno << 2))) |
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((mode & ATA_MODE_MASK) << (devno << 2)), 2);
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pci_write_config(gparent, 0x54,
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pci_read_config(gparent, 0x54, 1) |
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(0x01 << devno), 1);
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pci_write_config(gparent, 0x44,
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(pci_read_config(gparent, 0x44, 4) &
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~(0xff << offset)) |
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(dmatimings[2] << offset), 4);
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}
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else if (mode >= ATA_WDMA0) {
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pci_write_config(gparent, 0x54,
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pci_read_config(gparent, 0x54, 1) &
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~(0x01 << devno), 1);
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pci_write_config(gparent, 0x44,
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(pci_read_config(gparent, 0x44, 4) &
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~(0xff << offset)) |
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(dmatimings[mode & ATA_MODE_MASK] << offset), 4);
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}
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else
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pci_write_config(gparent, 0x54,
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pci_read_config(gparent, 0x54, 1) &
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~(0x01 << devno), 1);
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pci_write_config(gparent, 0x4a,
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(pci_read_config(gparent, 0x4a, 2) &
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~(0xf << (devno << 2))) |
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(((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
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pci_write_config(gparent, 0x40,
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(pci_read_config(gparent, 0x40, 4) &
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~(0xff << offset)) |
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(piotimings[ata_mode2idx(mode)] << offset), 4);
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atadev->mode = mode;
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}
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}
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static void
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ata_ati_ahci_enable(device_t dev)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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uint32_t ctrl;
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ctrl = pci_read_config(dev, ATI_PCI_MISC_CTRL, 4);
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pci_write_config(dev, ATI_PCI_MISC_CTRL,
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ctrl | ATI_PCI_MISCCTRL_ENABLE_WR, 4);
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pci_write_config(dev, PCIR_SUBCLASS, cfg->subclass, 1);
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pci_write_config(dev, PCIR_PROGIF, cfg->progif, 1);
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pci_write_config(dev, ATI_PCI_WD_CTRL,
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pci_read_config(dev, ATI_PCI_WD_CTRL, 2) | ATI_PCI_WDCTRL_ENABLE, 2);
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pci_write_config(dev, ATI_PCI_MISC_CTRL,
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ctrl & ~ATI_PCI_MISCCTRL_ENABLE_WR, 4);
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}
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static int
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ata_ati_ahci_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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int error;
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error = ata_ahci_chipinit(dev);
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ctlr->resume = ata_ati_ahci_resume;
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return (error);
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}
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static int
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ata_ati_ahci_resume(device_t dev)
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{
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ata_ati_ahci_enable(dev);
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return (ata_ahci_ctlr_reset(dev));
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}
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ATA_DECLARE_DRIVER(ata_ati);
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MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1);
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MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);
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