fc0dd0d307
timecounter instead of the GPT timer, freeing up the more flexible GPT hardware for other uses. The EPIT driver is a standard (always in the kernel) driver, and the existing GPT driver is now optional and included only if you ask for device imx_gpt.
134 lines
4.9 KiB
C
134 lines
4.9 KiB
C
/*-
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* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef IMX6_CCMREG_H
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#define IMX6_CCMREG_H
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#define CCM_CACCR 0x010
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#define CCM_CBCDR 0x014
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#define CBCDR_MMDC_CH1_AXI_PODF_SHIFT 3
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#define CBCDR_MMDC_CH1_AXI_PODF_MASK (7 << 3)
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#define CCM_CSCMR1 0x01C
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#define SSI1_CLK_SEL_S 10
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#define SSI2_CLK_SEL_S 12
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#define SSI3_CLK_SEL_S 14
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#define SSI_CLK_SEL_M 0x3
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#define SSI_CLK_SEL_508_PFD 0
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#define SSI_CLK_SEL_454_PFD 1
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#define SSI_CLK_SEL_PLL4 2
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#define CCM_CSCMR2 0x020
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#define CSCMR2_LDB_DI0_IPU_DIV_SHIFT 10
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#define CCM_CS1CDR 0x028
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#define SSI1_CLK_PODF_SHIFT 0
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#define SSI1_CLK_PRED_SHIFT 6
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#define SSI3_CLK_PODF_SHIFT 16
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#define SSI3_CLK_PRED_SHIFT 22
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#define SSI_CLK_PODF_MASK 0x3f
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#define SSI_CLK_PRED_MASK 0x7
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#define CCM_CS2CDR 0x02C
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#define SSI2_CLK_PODF_SHIFT 0
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#define SSI2_CLK_PRED_SHIFT 6
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#define LDB_DI0_CLK_SEL_SHIFT 9
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#define LDB_DI0_CLK_SEL_MASK (3 << LDB_DI0_CLK_SEL_SHIFT)
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#define CCM_CHSCCDR 0x034
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#define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
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#define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT 6
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#define CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
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#define CHSCCDR_IPU1_DI0_PODF_SHIFT 3
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#define CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
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#define CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT 0
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#define CHSCCDR_CLK_SEL_LDB_DI0 3
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#define CHSCCDR_PODF_DIVIDE_BY_3 2
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#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
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#define CCM_CSCDR2 0x038
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#define CCM_CLPCR 0x054
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#define CCM_CLPCR_LPM_MASK 0x03
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#define CCM_CLPCR_LPM_RUN 0x00
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#define CCM_CLPCR_LPM_WAIT 0x01
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#define CCM_CLPCR_LPM_STOP 0x02
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#define CCM_CGPR 0x064
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#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17)
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#define CCM_CCGR0 0x068
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#define CCGR0_AIPS_TZ1 (0x3 << 0)
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#define CCGR0_AIPS_TZ2 (0x3 << 2)
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#define CCGR0_ABPHDMA (0x3 << 4)
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#define CCM_CCGR1 0x06C
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#define CCGR1_ENET (0x3 << 10)
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#define CCGR1_EPIT1 (0x3 << 12)
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#define CCGR1_EPIT2 (0x3 << 14)
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#define CCGR1_GPT (0x3 << 20)
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#define CCGR1_GPT_SERIAL (0x3 << 22)
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#define CCM_CCGR2 0x070
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#define CCGR2_HDMI_TX (0x3 << 0)
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#define CCGR2_HDMI_TX_ISFR (0x3 << 4)
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#define CCGR2_I2C1 (0x3 << 6)
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#define CCGR2_I2C2 (0x3 << 8)
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#define CCGR2_I2C3 (0x3 << 10)
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#define CCGR2_IIM (0x3 << 12)
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#define CCGR2_IOMUX_IPT (0x3 << 14)
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#define CCGR2_IPMUX1 (0x3 << 16)
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#define CCGR2_IPMUX2 (0x3 << 18)
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#define CCGR2_IPMUX3 (0x3 << 20)
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#define CCGR2_IPSYNC_IP2APB_TZASC1 (0x3 << 22)
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#define CCGR2_IPSYNC_IP2APB_TZASC2 (0x3 << 24)
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#define CCGR2_IPSYNC_VDOA (0x3 << 26)
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#define CCM_CCGR3 0x074
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#define CCGR3_IPU1_IPU (0x3 << 0)
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#define CCGR3_IPU1_DI0 (0x3 << 2)
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#define CCGR3_IPU1_DI1 (0x3 << 4)
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#define CCGR3_IPU2_IPU (0x3 << 6)
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#define CCGR3_IPU2_DI0 (0x3 << 8)
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#define CCGR3_IPU2_DI1 (0x3 << 10)
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#define CCGR3_LDB_DI0 (0x3 << 12)
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#define CCGR3_LDB_DI1 (0x3 << 14)
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#define CCGR3_MMDC_CORE_ACLK_FAST (0x3 << 20)
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#define CCGR3_CG11 (0x3 << 22)
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#define CCGR3_MMDC_CORE_IPG (0x3 << 24)
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#define CCGR3_CG13 (0x3 << 26)
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#define CCGR3_OCRAM (0x3 << 28)
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#define CCM_CCGR4 0x078
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#define CCGR4_PL301_MX6QFAST1_S133 (0x3 << 8)
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#define CCGR4_PL301_MX6QPER1_BCH (0x3 << 12)
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#define CCGR4_PL301_MX6QPER2_MAIN (0x3 << 14)
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#define CCM_CCGR5 0x07C
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#define CCGR5_SDMA (0x3 << 6)
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#define CCGR5_SSI1 (0x3 << 18)
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#define CCGR5_SSI2 (0x3 << 20)
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#define CCGR5_SSI3 (0x3 << 22)
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#define CCGR5_UART (0x3 << 24)
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#define CCGR5_UART_SERIAL (0x3 << 26)
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#define CCM_CCGR6 0x080
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#define CCGR6_USBOH3 (0x3 << 0)
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#define CCGR6_USDHC1 (0x3 << 2)
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#define CCGR6_USDHC2 (0x3 << 4)
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#define CCGR6_USDHC3 (0x3 << 6)
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#define CCGR6_USDHC4 (0x3 << 8)
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#define CCM_CMEOR 0x088
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#endif
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