1d80cb1b37
for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
367 lines
9.6 KiB
C
367 lines
9.6 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: FreeBSD: src/sys/alpha/isa/isa.c,v 1.26 2001/07/11
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*
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* $FreeBSD$
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*/
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#include "opt_ofw_pci.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/interrupt.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <isa/isa_common.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <ofw/ofw_pci.h>
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#include <ofw/openfirm.h>
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#include <machine/intr_machdep.h>
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#include <machine/ofw_bus.h>
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#include <machine/resource.h>
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#include <sparc64/pci/ofw_pci.h>
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#include <sparc64/isa/ofw_isa.h>
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/* There can be only one ISA bus, so it is safe to use globals. */
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bus_space_tag_t isa_io_bt = NULL;
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bus_space_handle_t isa_io_hdl;
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bus_space_tag_t isa_mem_bt = NULL;
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bus_space_handle_t isa_mem_hdl;
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u_int64_t isa_io_base;
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u_int64_t isa_io_limit;
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u_int64_t isa_mem_base;
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u_int64_t isa_mem_limit;
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device_t isa_bus_device;
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static phandle_t isab_node;
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static ofw_pci_intr_t isa_ino[8];
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#ifdef OFW_NEWPCI
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struct ofw_bus_iinfo isa_iinfo;
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#endif
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/*
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* XXX: This is really partly partly PCI-specific, but unfortunately is
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* differently enough to have to duplicate it here...
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*/
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#define ISAB_RANGE_PHYS(r) \
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(((u_int64_t)(r)->phys_mid << 32) | (u_int64_t)(r)->phys_lo)
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#define ISAB_RANGE_SPACE(r) (((r)->phys_hi >> 24) & 0x03)
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#define ISAR_SPACE_IO 0x01
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#define ISAR_SPACE_MEM 0x02
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#define INRANGE(x, start, end) ((x) >= (start) && (x) <= (end))
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static int isa_route_intr_res(device_t, u_long, u_long);
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intrmask_t
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isa_irq_pending(void)
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{
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intrmask_t pending;
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int i;
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/* XXX: Is this correct? */
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for (i = 7, pending = 0; i >= 0; i--) {
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pending <<= 1;
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if (isa_ino[i] != PCI_INVALID_IRQ) {
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pending |= (OFW_PCI_INTR_PENDING(isa_bus_device,
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isa_ino[i]) == 0) ? 0 : 1;
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}
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}
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return (pending);
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}
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void
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isa_init(device_t dev)
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{
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device_t bridge;
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phandle_t node;
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ofw_isa_intr_t ino;
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#ifndef OFW_NEWPCI
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ofw_pci_intr_t rino;
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#endif
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struct isa_ranges *br;
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int nbr, i;
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/* The parent of the bus must be a PCI-ISA bridge. */
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bridge = device_get_parent(dev);
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#ifdef OFW_NEWPCI
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isab_node = ofw_pci_get_node(bridge);
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#else
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isab_node = ofw_pci_node(bridge);
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#endif
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nbr = OF_getprop_alloc(isab_node, "ranges", sizeof(*br), (void **)&br);
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if (nbr <= 0)
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panic("isa_init: cannot get bridge range property");
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#ifdef OFW_NEWPCI
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ofw_bus_setup_iinfo(isab_node, &isa_iinfo, sizeof(ofw_isa_intr_t));
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#endif
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/*
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* This is really a bad kludge; however, it is needed to provide
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* isa_irq_pending(), which is unfortunately still used by some
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* drivers.
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*/
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for (i = 0; i < 8; i++)
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isa_ino[i] = PCI_INVALID_IRQ;
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for (node = OF_child(isab_node); node != 0; node = OF_peer(node)) {
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if (OF_getprop(node, "interrupts", &ino, sizeof(ino)) == -1)
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continue;
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if (ino > 7)
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panic("isa_init: XXX: ino too large");
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#ifdef OFW_NEWPCI
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isa_ino[ino] = ofw_isa_route_intr(bridge, node, &isa_iinfo,
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ino);
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#else
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rino = ofw_bus_route_intr(node, ino, ofw_pci_orb_callback, dev);
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isa_ino[ino] = rino == ORIR_NOTFOUND ? PCI_INVALID_IRQ : rino;
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#endif
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}
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for (nbr -= 1; nbr >= 0; nbr--) {
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switch(ISAB_RANGE_SPACE(br + nbr)) {
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case ISAR_SPACE_IO:
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/* This is probably always 0. */
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isa_io_base = ISAB_RANGE_PHYS(&br[nbr]);
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isa_io_limit = br[nbr].size;
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isa_io_hdl = OFW_PCI_GET_BUS_HANDLE(bridge,
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SYS_RES_IOPORT, isa_io_base, &isa_io_bt);
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break;
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case ISAR_SPACE_MEM:
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/* This is probably always 0. */
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isa_mem_base = ISAB_RANGE_PHYS(&br[nbr]);
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isa_mem_limit = br[nbr].size;
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isa_mem_hdl = OFW_PCI_GET_BUS_HANDLE(bridge,
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SYS_RES_MEMORY, isa_mem_base, &isa_mem_bt);
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break;
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}
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}
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free(br, M_OFWPROP);
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}
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static int
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isa_route_intr_res(device_t bus, u_long start, u_long end)
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{
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int res;
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if (start != end) {
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panic("isa_route_intr_res: allocation of interrupt range not "
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"supported (0x%lx - 0x%lx)", start, end);
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}
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if (start > 7)
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panic("isa_route_intr_res: start out of isa range");
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res = isa_ino[start];
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if (res == PCI_INVALID_IRQ)
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device_printf(bus, "could not map interrupt %d\n", res);
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return (res);
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}
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struct resource *
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isa_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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/*
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* Consider adding a resource definition. We allow rid 0-1 for
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* irq and drq, 0-3 for memory and 0-7 for ports which is
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* sufficient for isapnp.
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*/
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int passthrough = (device_get_parent(child) != bus);
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int isdefault = (start == 0UL && end == ~0UL);
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struct isa_device* idev = DEVTOISA(child);
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struct resource_list *rl = &idev->id_resources;
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struct resource_list_entry *rle;
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u_long base, limit;
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if (!passthrough && !isdefault) {
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rle = resource_list_find(rl, type, *rid);
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if (!rle) {
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if (*rid < 0)
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return 0;
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switch (type) {
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case SYS_RES_IRQ:
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if (*rid >= ISA_NIRQ)
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return 0;
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break;
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case SYS_RES_DRQ:
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if (*rid >= ISA_NDRQ)
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return 0;
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break;
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case SYS_RES_MEMORY:
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if (*rid >= ISA_NMEM)
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return 0;
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break;
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case SYS_RES_IOPORT:
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if (*rid >= ISA_NPORT)
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return 0;
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break;
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default:
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return 0;
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}
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resource_list_add(rl, type, *rid, start, end, count);
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}
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}
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/*
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* Add the base, change default allocations to be between base and
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* limit, and reject allocations if a resource type is not enabled.
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*/
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base = limit = 0;
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switch(type) {
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case SYS_RES_MEMORY:
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if (isa_mem_bt == NULL)
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return (NULL);
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base = isa_mem_base;
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limit = base + isa_mem_limit;
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break;
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case SYS_RES_IOPORT:
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if (isa_io_bt == NULL)
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return (NULL);
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base = isa_io_base;
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limit = base + isa_io_limit;
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break;
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case SYS_RES_IRQ:
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if (isdefault && passthrough)
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panic("isa_alloc_resource: cannot pass through default "
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"irq allocation");
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if (!isdefault) {
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start = end = isa_route_intr_res(bus, start, end);
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if (start == PCI_INVALID_IRQ)
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return (NULL);
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}
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break;
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default:
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panic("isa_alloc_resource: unsupported resource type %d", type);
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}
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if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
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start = ulmin(start + base, limit);
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end = ulmin(end + base, limit);
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}
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/*
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* This inlines a modified resource_list_alloc(); this is needed
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* because the resources need to have offsets added to them, which
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* cannot be done beforehand without patching the resource list entries
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* (which is ugly).
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*/
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if (passthrough) {
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return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
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type, rid, start, end, count, flags));
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}
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rle = resource_list_find(rl, type, *rid);
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if (rle == NULL)
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return (NULL); /* no resource of that type/rid */
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if (rle->res != NULL)
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panic("isa_alloc_resource: resource entry is busy");
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if (isdefault) {
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start = rle->start;
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count = ulmax(count, rle->count);
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end = ulmax(rle->end, start + count - 1);
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switch (type) {
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case SYS_RES_MEMORY:
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case SYS_RES_IOPORT:
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start += base;
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end += base;
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if (!INRANGE(start, base, limit) ||
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!INRANGE(end, base, limit))
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return (NULL);
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break;
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case SYS_RES_IRQ:
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start = end = isa_route_intr_res(bus, start, end);
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if (start == PCI_INVALID_IRQ)
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return (NULL);
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break;
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}
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}
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rle->res = BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
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type, rid, start, end, count, flags);
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/*
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* Record the new range.
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*/
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if (rle->res != NULL) {
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rle->start = rman_get_start(rle->res) - base;
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rle->end = rman_get_end(rle->res) - base;
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rle->count = count;
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}
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return (rle->res);
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}
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int
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isa_release_resource(device_t bus, device_t child, int type, int rid,
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struct resource *res)
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{
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struct isa_device* idev = DEVTOISA(child);
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struct resource_list *rl = &idev->id_resources;
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return (resource_list_release(rl, bus, child, type, rid, res));
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}
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int
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isa_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep)
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{
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/*
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* Just pass through. This is going to be handled by either one of
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* the parent PCI buses or the nexus device.
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* The interrupt was routed at allocation time.
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*/
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return (BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, intr,
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arg, cookiep));
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}
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int
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isa_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie)
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{
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return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie));
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}
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