671bf2b8b2
related to "shared" CPLs. a) Combine t4_set_tcb_field and t4_set_tcb_field_rpl into a single function. Allow callers to direct the response to any iq. Tidy up set_ulp_mode_iscsi while there to use names from t4_tcb.h instead of magic constants. b) Remove all CPL handler tables from struct adapter. This reduces its size by around 2KB. All handlers are now registered at MOD_LOAD instead of attach or some kind of initialization/activation. The registration functions do not need an adapter parameter any more. c) Add per-iq handlers to deal with CPLs whose destination cannot be determined solely from the opcode. There are 2 such CPLs in use right now: SET_TCB_RPL and L2T_WRITE_RPL. The base driver continues to send filter and L2T_WRITEs over the mgmtq and solicits the reply on fwq. t4_tom (including the DDP code) now uses the port's ctrlq to send L2T_WRITEs and SET_TCB_FIELDs and solicits the reply on an ofld_rxq. fwq and ofld_rxq have different handlers that know what kind of tid to expect in the reply. Update t4_write_l2e and callers to to support any wrq/iq combination. Approved by: re@ (kib@) Sponsored by: Chelsio Communications
113 lines
4.2 KiB
C
113 lines
4.2 KiB
C
/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __T4_L2T_H
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#define __T4_L2T_H
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/* identifies sync vs async L2T_WRITE_REQs */
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#define S_SYNC_WR 12
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#define V_SYNC_WR(x) ((x) << S_SYNC_WR)
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#define F_SYNC_WR V_SYNC_WR(1)
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enum { L2T_SIZE = 4096 }; /* # of L2T entries */
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enum {
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L2T_STATE_VALID, /* entry is up to date */
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L2T_STATE_STALE, /* entry may be used but needs revalidation */
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L2T_STATE_RESOLVING, /* entry needs address resolution */
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L2T_STATE_FAILED, /* failed to resolve */
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L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */
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/* when state is one of the below the entry is not hashed */
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L2T_STATE_SWITCHING, /* entry is being used by a switching filter */
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L2T_STATE_UNUSED /* entry not in use */
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};
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/*
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* Each L2T entry plays multiple roles. First of all, it keeps state for the
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* corresponding entry of the HW L2 table and maintains a queue of offload
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* packets awaiting address resolution. Second, it is a node of a hash table
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* chain, where the nodes of the chain are linked together through their next
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* pointer. Finally, each node is a bucket of a hash table, pointing to the
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* first element in its chain through its first pointer.
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*/
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struct l2t_entry {
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uint16_t state; /* entry state */
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uint16_t idx; /* entry index */
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uint32_t addr[4]; /* next hop IP or IPv6 address */
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uint32_t iqid; /* iqid for reply to write_l2e */
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struct sge_wrq *wrq; /* queue to use for write_l2e */
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struct ifnet *ifp; /* outgoing interface */
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uint16_t smt_idx; /* SMT index */
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uint16_t vlan; /* VLAN TCI (id: 0-11, prio: 13-15) */
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struct l2t_entry *first; /* start of hash chain */
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struct l2t_entry *next; /* next l2t_entry on chain */
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STAILQ_HEAD(, wrqe) wr_list; /* list of WRs awaiting resolution */
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struct mtx lock;
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volatile int refcnt; /* entry reference count */
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uint16_t hash; /* hash bucket the entry is on */
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uint8_t ipv6; /* entry is for an IPv6 address */
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uint8_t lport; /* associated offload logical port */
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uint8_t dmac[ETHER_ADDR_LEN]; /* next hop's MAC address */
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};
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struct l2t_data {
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struct rwlock lock;
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u_int l2t_size;
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volatile int nfree; /* number of free entries */
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struct l2t_entry *rover;/* starting point for next allocation */
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struct l2t_entry l2tab[];
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};
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int t4_init_l2t(struct adapter *, int);
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int t4_free_l2t(struct l2t_data *);
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struct l2t_entry *t4_alloc_l2e(struct l2t_data *);
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struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *);
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int t4_l2t_set_switching(struct adapter *, struct l2t_entry *, uint16_t,
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uint8_t, uint8_t *);
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int t4_write_l2e(struct l2t_entry *, int);
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int do_l2t_write_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
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static inline void
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t4_l2t_release(struct l2t_entry *e)
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{
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struct l2t_data *d = __containerof(e, struct l2t_data, l2tab[e->idx]);
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if (atomic_fetchadd_int(&e->refcnt, -1) == 1)
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atomic_add_int(&d->nfree, 1);
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}
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#ifdef SBUF_DRAIN
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int sysctl_l2t(SYSCTL_HANDLER_ARGS);
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#endif
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#endif /* __T4_L2T_H */
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