Marius Strobl 15eddb68ee Interrupts must be disabled while handling a partial cache line flush, ... as otherwise the interrupt handling code may modify data in the non-DMA part of the cache line while we have it stashed away in the temporary stack buffer, then we end up restoring a stale value. PR: 160431 Submitted by: Ian Lepore MFC after: 1 week		2012-04-22 00:58:04 +00:00
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arm	Interrupts must be disabled while handling a partial cache line flush,	2012-04-22 00:58:04 +00:00
at91	- Add support for MCI1 revision 2xx controllers and a work-around for their	2012-04-22 00:43:32 +00:00
compile
conf	- Add kernel config file for QEMU-emulated gumstix board.	2012-04-07 23:48:51 +00:00
econa	Implement better support for USB controller suspend and resume.	2011-12-14 00:28:54 +00:00
include	Replace the C implementation of __aeabi_read_tp with an assembly version.	2012-04-16 09:38:20 +00:00
mv	Fix error check.	2012-03-15 21:48:27 +00:00
s3c2xx0	Get myself a brain, move the call to init_param1() before the first use in	2011-02-21 13:11:05 +00:00
sa11x0	Remove spurious 8bit chars, turning files into plain ASCII.	2012-01-15 13:23:33 +00:00
xscale	- Add new ARM kernel option QEMU_WORKAROUNDS which can be	2012-04-07 23:47:08 +00:00