871 lines
22 KiB
C
871 lines
22 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Based very closely on NetBSD version-
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*
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* Copyright (c) 1997 by Matthew Jacob
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* NASA AMES Research Center.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_simos.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/interrupt.h>
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#include <machine/swiz.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/resource.h>
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#include <machine/sgmap.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <alpha/tlsb/tlsbreg.h>
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#include <alpha/tlsb/tlsbvar.h>
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#include <alpha/tlsb/kftxxreg.h>
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#include <alpha/tlsb/kftxxvar.h>
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#include <alpha/tlsb/dwlpxreg.h>
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#include <alpha/tlsb/dwlpxvar.h>
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#include <alpha/pci/pcibus.h>
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#include <pci/pcivar.h>
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#include "alphapci_if.h"
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#include "pcib_if.h"
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static devclass_t dwlpx_devclass;
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static device_t dwlpxs[DWLPX_NIONODE][DWLPX_NHOSE];
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#define KV(pa) ((void *)ALPHA_PHYS_TO_K0SEG(pa))
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struct dwlpx_softc {
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struct dwlpx_softc *next;
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device_t dev; /* backpointer */
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u_int64_t sysbase; /* shorthand */
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vm_offset_t dmem_base; /* dense memory */
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vm_offset_t smem_base; /* sparse memory */
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vm_offset_t io_base; /* sparse i/o */
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struct swiz_space io_space; /* accessor for ports */
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struct swiz_space mem_space; /* accessor for memory */
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struct rman io_rman; /* resource manager for ports */
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struct rman mem_rman; /* resource manager for memory */
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int bushose; /* our bus && hose */
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u_int : 26,
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nhpc : 2, /* how many HPCs */
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dwlpb : 1, /* this is a DWLPB */
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sgmapsz : 3; /* Scatter Gather map size */
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};
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static driver_intr_t dwlpx_intr;
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static u_int32_t imaskcache[DWLPX_NIONODE][DWLPX_NHOSE][NHPC];
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static void dwlpx_eintr(unsigned long);
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/*
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* Direct-mapped window: 2G at 2G
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*/
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#define DWLPx_DIRECT_MAPPED_BASE (2UL*1024UL*1024UL*1024UL)
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#define DWLPx_DIRECT_MAPPED_SIZE (2UL*1024UL*1024UL*1024UL)
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#define DWLPx_DIRECT_MAPPED_WMASK PCIA_WMASK_2G
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/*
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* SGMAP window A: 256M at 1.75G or 1G at 1G
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*/
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#define DWLPx_SG_MAPPED_SIZE(x) ((x) * PAGE_SIZE)
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static void dwlpx_dma_init(struct dwlpx_softc *);
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#define DWLPX_SOFTC(dev) (struct dwlpx_softc *) device_get_softc(dev)
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static struct dwlpx_softc *dwlpx_root;
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static int
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dwlpx_probe(device_t dev)
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{
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device_t child;
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u_int32_t ctl;
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struct dwlpx_softc *xc, *sc = DWLPX_SOFTC(dev);
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unsigned long ls;
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int io, hose;
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io = kft_get_node(dev) - 4;
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hose = kft_get_hosenum(dev);
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sc->bushose = (io << 2) | hose;
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if (dwlpxs[io][hose]) {
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device_printf(dev, "already attached\n");
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return EEXIST;
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}
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if ((xc = dwlpx_root) == NULL) {
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dwlpx_root = sc;
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} else {
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while (xc->next)
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xc = xc->next;
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xc->next = sc;
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}
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sc->dev = dwlpxs[io][hose] = dev;
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ls = DWLPX_BASE(io + 4, hose);
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for (sc->nhpc = 1; sc->nhpc < NHPC; sc->nhpc++) {
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if (badaddr(KV(PCIA_CTL(sc->nhpc) + ls), sizeof (ctl))) {
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break;
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}
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}
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if (sc->nhpc != NHPC) {
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REGVAL(PCIA_ERR(0) + ls) = PCIA_ERR_ALLERR;
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}
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ctl = REGVAL(PCIA_PRESENT + ls);
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if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) {
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sc->dwlpb = 1;
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device_set_desc(dev, "DWLPB PCI adapter");
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} else {
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device_set_desc(dev, "DWLPA PCI adapter");
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}
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sc->sgmapsz = DWLPX_SG32K;
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if (device_get_unit(dev) == 0) {
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pci_init_resources();
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}
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child = device_add_child(dev, "pci", -1);
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device_set_ivars(child, &sc->bushose);
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return (0);
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}
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static int
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dwlpx_attach(device_t dev)
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{
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struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
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device_t parent = device_get_parent(dev);
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vm_offset_t regs;
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u_int32_t ctl;
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int i, io, hose;
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void *intr;
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io = kft_get_node(dev) - 4;
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hose = kft_get_hosenum(dev);
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sc->sysbase = DWLPX_BASE(io + 4, hose);
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regs = (vm_offset_t) KV(sc->sysbase);
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sc->dmem_base = regs + DWLPX_PCI_DENSE;
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sc->smem_base = regs + DWLPX_PCI_SPARSE;
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sc->io_base = regs + DWLPX_PCI_IOSPACE;
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/*
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* Maybe initialise busspace_isa_io and busspace_isa_mem
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* here. Does the 8200 actually have any ISA slots?
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*/
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swiz_init_space(&sc->io_space, sc->io_base);
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swiz_init_space(&sc->mem_space, sc->smem_base);
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sc->io_rman.rm_start = 0;
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sc->io_rman.rm_end = ~0u;
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sc->io_rman.rm_type = RMAN_ARRAY;
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sc->io_rman.rm_descr = "I/O ports";
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if (rman_init(&sc->io_rman)
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|| rman_manage_region(&sc->io_rman, 0x0, (1L << 32)))
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panic("dwlpx_attach: io_rman");
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sc->mem_rman.rm_start = 0;
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sc->mem_rman.rm_end = ~0u;
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sc->mem_rman.rm_type = RMAN_ARRAY;
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sc->mem_rman.rm_descr = "I/O memory";
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if (rman_init(&sc->mem_rman)
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|| rman_manage_region(&sc->mem_rman, 0x0, (1L << 32)))
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panic("dwlpx_attach: mem_rman");
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/*
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* Set up interrupt stuff for this DWLPX.
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*
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* Note that all PCI interrupt pins are disabled at this time.
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*
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* Do this even for all HPCs- even for the
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* nonexistent one on hose zero of a KFTIA.
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*/
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for (i = 0; i < NHPC; i++) {
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REGVAL(PCIA_IMASK(i) + sc->sysbase) = DWLPX_IMASK_DFLT;
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REGVAL(PCIA_ERRVEC(i) + sc->sysbase) =
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DWLPX_ERRVEC(io, hose);
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}
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for (i = 0; i < DWLPX_MAXDEV; i++) {
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u_int16_t vec;
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int ss, hpc;
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vec = DWLPX_MVEC(io, hose, i);
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ss = i;
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if (i < 4) {
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hpc = 0;
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} else if (i < 8) {
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ss -= 4;
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hpc = 1;
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} else {
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ss -= 8;
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hpc = 2;
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}
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REGVAL(PCIA_DEVVEC(hpc, ss, 1) + sc->sysbase) = vec;
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REGVAL(PCIA_DEVVEC(hpc, ss, 2) + sc->sysbase) = vec;
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REGVAL(PCIA_DEVVEC(hpc, ss, 3) + sc->sysbase) = vec;
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REGVAL(PCIA_DEVVEC(hpc, ss, 4) + sc->sysbase) = vec;
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}
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/*
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* Establish HAE values, as well as make sure of sanity elsewhere.
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*/
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for (i = 0; i < sc->nhpc; i++) {
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ctl = REGVAL(PCIA_CTL(i) + sc->sysbase);
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ctl &= 0x0fffffff;
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ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f));
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/*
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* I originally also had it or'ing in 3, which makes no sense.
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*/
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ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB;
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/*
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* Only valid if we're attached to a KFTIA or a KTHA.
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*/
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ctl |= PCIA_CTL_3UP;
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ctl |= PCIA_CTL_CUTENA;
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/*
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* Fit in appropriate S/G Map Ram size.
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*/
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if (sc->sgmapsz == DWLPX_SG32K)
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ctl |= PCIA_CTL_SG32K;
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else if (sc->sgmapsz == DWLPX_SG128K)
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ctl |= PCIA_CTL_SG128K;
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else
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ctl |= PCIA_CTL_SG32K;
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REGVAL(PCIA_CTL(i) + sc->sysbase) = ctl;
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}
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/*
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* Enable TBIT if required
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*/
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if (sc->sgmapsz == DWLPX_SG128K)
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REGVAL(PCIA_TBIT + sc->sysbase) = 1;
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alpha_mb();
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for (io = 0; io < DWLPX_NIONODE; io++) {
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for (hose = 0; hose < DWLPX_NHOSE; hose++) {
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for (i = 0; i < NHPC; i++) {
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imaskcache[io][hose][i] = DWLPX_IMASK_DFLT;
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}
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}
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}
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/*
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* Set up DMA stuff here.
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*/
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dwlpx_dma_init(sc);
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/*
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* Register our interrupt service requirements with our parent.
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*/
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i = BUS_SETUP_INTR(parent, dev, NULL,
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INTR_TYPE_MISC, dwlpx_intr, 0, &intr);
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if (i == 0) {
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bus_generic_attach(dev);
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}
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return (i);
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}
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static void dwlpx_enadis_intr(int, int, int);
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static void
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dwlpx_enadis_intr(int vector, int intpin, int onoff)
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{
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unsigned long paddr;
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u_int32_t val;
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int device, ionode, hose, hpc;
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ionode = DWLPX_MVEC_IONODE(vector);
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hose = DWLPX_MVEC_HOSE(vector);
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device = DWLPX_MVEC_PCISLOT(vector);
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paddr = (1LL << 39);
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paddr |= (unsigned long) ionode << 36;
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paddr |= (unsigned long) hose << 34;
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if (device < 4) {
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hpc = 0;
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} else if (device < 8) {
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hpc = 1;
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device -= 4;
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} else {
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hpc = 2;
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device -= 8;
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}
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intpin <<= (device << 2);
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mtx_lock_spin(&icu_lock);
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val = imaskcache[ionode][hose][hpc];
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if (onoff)
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val |= intpin;
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else
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val &= ~intpin;
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imaskcache[ionode][hose][hpc] = val;
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REGVAL(PCIA_IMASK(hpc) + paddr) = val;
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mtx_unlock_spin(&icu_lock);
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}
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static int
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dwlpx_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep)
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{
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struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
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int slot, ionode, hose, error, vector, intpin;
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error = rman_activate_resource(irq);
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if (error)
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return error;
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intpin = pci_get_intpin(child);
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slot = pci_get_slot(child);
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ionode = sc->bushose >> 2;
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hose = sc->bushose & 0x3;
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vector = DWLPX_MVEC(ionode, hose, slot);
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error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
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vector, intr, arg, flags, cookiep,
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&intrcnt[INTRCNT_KN8AE_IRQ], NULL, NULL);
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if (error)
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return error;
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dwlpx_enadis_intr(vector, intpin, 1);
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device_printf(child, "Node %d Hose %d Slot %d interrupting at TLSB "
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"vector 0x%x intpin %d\n", ionode+4, hose, slot, vector, intpin);
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return (0);
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}
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static int
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dwlpx_teardown_intr(device_t dev, device_t child, struct resource *irq, void *c)
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{
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struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
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int slot, ionode, hose, vector, intpin;
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intpin = pci_get_intpin(child);
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slot = pci_get_slot(child);
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ionode = sc->bushose >> 2;
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hose = sc->bushose & 0x3;
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vector = DWLPX_MVEC(ionode, hose, slot);
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dwlpx_enadis_intr(vector, intpin, 0);
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alpha_teardown_intr(c);
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return rman_deactivate_resource(irq);
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}
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static int
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dwlpx_read_ivar(device_t dev, device_t child, int which, u_long *result)
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{
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = 0;
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return 0;
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}
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return ENOENT;
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}
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static void *
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dwlpx_cvt_dense(device_t dev, vm_offset_t addr)
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{
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struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
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addr &= 0xffffffffUL;
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return (void *) KV(addr | sc->dmem_base);
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}
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static kobj_t
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dwlpx_get_bustag(device_t dev, int type)
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{
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struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
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switch (type) {
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case SYS_RES_IOPORT:
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return (kobj_t) &sc->io_space;
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case SYS_RES_MEMORY:
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return (kobj_t) &sc->mem_space;
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}
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return 0;
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}
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static struct rman *
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dwlpx_get_rman(device_t dev, int type)
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{
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struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
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switch (type) {
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case SYS_RES_IOPORT:
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return &sc->io_rman;
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case SYS_RES_MEMORY:
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return &sc->mem_rman;
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}
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return 0;
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}
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static int
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dwlpx_maxslots(device_t dev)
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{
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return (DWLPX_MAXDEV);
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}
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static u_int32_t
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dwlpx_read_config(device_t dev, int bus, int slot, int func,
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int off, int sz)
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{
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struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
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u_int32_t *dp, data, rvp, pci_idsel, hpcdev;
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unsigned long paddr;
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int hose, ionode;
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int secondary = 0, s = 0, i;
|
|
|
|
rvp = data = ~0;
|
|
|
|
ionode = ((sc->bushose >> 2) & 0x7);
|
|
hose = (sc->bushose & 0x3);
|
|
|
|
if (sc->nhpc < 1)
|
|
return (data);
|
|
else if (sc->nhpc < 2 && slot >= 4)
|
|
return (data);
|
|
else if (sc->nhpc < 3 && slot >= 8)
|
|
return (data);
|
|
else if (slot >= DWLPX_MAXDEV)
|
|
return (data);
|
|
hpcdev = slot >> 2;
|
|
pci_idsel = (1 << ((slot & 0x3) + 2));
|
|
paddr = (hpcdev << 22) | (pci_idsel << 16) | (func << 13);
|
|
|
|
if (secondary) {
|
|
paddr &= 0x1fffff;
|
|
paddr |= (secondary << 21);
|
|
|
|
#if 0
|
|
printf("read secondary %d reg %x (paddr %lx)",
|
|
secondary, offset, tag);
|
|
#endif
|
|
|
|
alpha_pal_draina();
|
|
s = splhigh();
|
|
/*
|
|
* Set up HPCs for type 1 cycles.
|
|
*/
|
|
for (i = 0; i < sc->nhpc; i++) {
|
|
rvp = REGVAL(PCIA_CTL(i)+sc->sysbase) | PCIA_CTL_T1CYC;
|
|
alpha_mb();
|
|
REGVAL(PCIA_CTL(i) + sc->sysbase) = rvp;
|
|
alpha_mb();
|
|
}
|
|
}
|
|
|
|
paddr |= ((unsigned long) ((off >> 2) << 7));
|
|
paddr |= ((sz - 1) << 3);
|
|
paddr |= DWLPX_PCI_CONF;
|
|
paddr |= ((unsigned long) hose) << 34;
|
|
paddr |= ((unsigned long) ionode) << 36;
|
|
paddr |= 1L << 39;
|
|
|
|
dp = (u_int32_t *)KV(paddr);
|
|
|
|
#if 0
|
|
printf("CFGREAD %d.%d.%d.%d.%d.%d.%d -> paddr 0x%lx",
|
|
ionode+4, hose, bus, slot, func, off, sz, paddr);
|
|
#endif
|
|
|
|
if (badaddr(dp, sizeof (*dp)) == 0) {
|
|
data = *dp;
|
|
}
|
|
|
|
if (secondary) {
|
|
alpha_pal_draina();
|
|
for (i = 0; i < sc->nhpc; i++) {
|
|
rvp = REGVAL(PCIA_CTL(i)+sc->sysbase) & ~PCIA_CTL_T1CYC;
|
|
alpha_mb();
|
|
REGVAL(PCIA_CTL(i) + sc->sysbase) = rvp;
|
|
alpha_mb();
|
|
}
|
|
(void) splx(s);
|
|
}
|
|
|
|
if (data != ~0) {
|
|
if (sz == 1) {
|
|
rvp = SPARSE_BYTE_EXTRACT(off, data);
|
|
} else if (sz == 2) {
|
|
rvp = SPARSE_WORD_EXTRACT(off, data);
|
|
} else {
|
|
rvp = data;
|
|
}
|
|
} else {
|
|
rvp = data;
|
|
}
|
|
|
|
#if 0
|
|
printf(" data 0x%x -> 0x%x\n", data, rvp);
|
|
#endif
|
|
return (rvp);
|
|
}
|
|
|
|
static void
|
|
dwlpx_write_config(device_t dev, int bus, int slot, int func,
|
|
int off, u_int32_t data, int sz)
|
|
{
|
|
struct dwlpx_softc *sc = DWLPX_SOFTC(dev);
|
|
int hose, ionode;
|
|
int secondary = 0, s = 0, i;
|
|
u_int32_t *dp, rvp, pci_idsel, hpcdev;
|
|
unsigned long paddr;
|
|
|
|
ionode = ((sc->bushose >> 2) & 0x7);
|
|
hose = (sc->bushose & 0x3);
|
|
|
|
if (sc->nhpc < 1)
|
|
return;
|
|
else if (sc->nhpc < 2 && slot >= 4)
|
|
return;
|
|
else if (sc->nhpc < 3 && slot >= 8)
|
|
return;
|
|
else if (slot >= DWLPX_MAXDEV)
|
|
return;
|
|
hpcdev = slot >> 2;
|
|
pci_idsel = (1 << ((slot & 0x3) + 2));
|
|
paddr = (hpcdev << 22) | (pci_idsel << 16) | (func << 13);
|
|
|
|
if (secondary) {
|
|
paddr &= 0x1fffff;
|
|
paddr |= (secondary << 21);
|
|
|
|
#if 0
|
|
printf("write secondary %d reg %x (paddr %lx)",
|
|
secondary, offset, tag);
|
|
#endif
|
|
|
|
alpha_pal_draina();
|
|
s = splhigh();
|
|
/*
|
|
* Set up HPCs for type 1 cycles.
|
|
*/
|
|
for (i = 0; i < sc->nhpc; i++) {
|
|
rvp = REGVAL(PCIA_CTL(i)+sc->sysbase) | PCIA_CTL_T1CYC;
|
|
alpha_mb();
|
|
REGVAL(PCIA_CTL(i) + sc->sysbase) = rvp;
|
|
alpha_mb();
|
|
}
|
|
}
|
|
|
|
paddr |= ((unsigned long) ((off >> 2) << 7));
|
|
paddr |= ((sz - 1) << 3);
|
|
paddr |= DWLPX_PCI_CONF;
|
|
paddr |= ((unsigned long) hose) << 34;
|
|
paddr |= ((unsigned long) ionode) << 36;
|
|
paddr |= 1L << 39;
|
|
|
|
dp = (u_int32_t *)KV(paddr);
|
|
if (badaddr(dp, sizeof (*dp)) == 0) {
|
|
u_int32_t new_data;
|
|
if (sz == 1) {
|
|
new_data = SPARSE_BYTE_INSERT(off, data);
|
|
} else if (sz == 2) {
|
|
new_data = SPARSE_WORD_INSERT(off, data);
|
|
} else {
|
|
new_data = data;
|
|
}
|
|
|
|
#if 0
|
|
printf("CFGWRITE %d.%d.%d.%d.%d.%d.%d paddr 0x%lx data 0x%x -> 0x%x\n",
|
|
ionode+4, hose, bus, slot, func, off, sz, paddr, data, new_data);
|
|
#endif
|
|
|
|
*dp = new_data;
|
|
}
|
|
if (secondary) {
|
|
alpha_pal_draina();
|
|
for (i = 0; i < sc->nhpc; i++) {
|
|
rvp = REGVAL(PCIA_CTL(i)+sc->sysbase) & ~PCIA_CTL_T1CYC;
|
|
alpha_mb();
|
|
REGVAL(PCIA_CTL(i) + sc->sysbase) = rvp;
|
|
alpha_mb();
|
|
}
|
|
(void) splx(s);
|
|
}
|
|
}
|
|
|
|
static void
|
|
dwlpx_dma_init(struct dwlpx_softc *sc)
|
|
{
|
|
u_int32_t *tbl, sgwmask, sgwbase, sgwend;
|
|
int i, lim;
|
|
|
|
/*
|
|
* Determine size of Window C based on the amount of SGMAP
|
|
* page table SRAM available.
|
|
*/
|
|
if (sc->sgmapsz == DWLPX_SG128K) {
|
|
lim = 128 * 1024;
|
|
sgwmask = PCIA_WMASK_1G;
|
|
sgwbase = 1UL*1024UL*1024UL*1024UL;
|
|
} else {
|
|
lim = 32 * 1024;
|
|
sgwmask = PCIA_WMASK_256M;
|
|
sgwbase = 1UL*1024UL*1024UL*1024UL+3UL*256UL*1024UL*1024UL;
|
|
}
|
|
sgwend = sgwbase + (lim * 8192) - 1;
|
|
|
|
/*
|
|
* A few notes about SGMAP-mapped DMA on the DWLPx:
|
|
*
|
|
* The DWLPx has PCIA-resident SRAM that is used for
|
|
* the SGMAP page table; there is no TLB. The DWLPA
|
|
* has room for 32K entries, yielding a total of 256M
|
|
* of sgva space. The DWLPB has 32K entries or 128K
|
|
* entries, depending on TBIT, yielding either 256M or
|
|
* 1G of sgva space.
|
|
*/
|
|
|
|
/*
|
|
* Initialize the page table.
|
|
*/
|
|
tbl = (u_int32_t *) ALPHA_PHYS_TO_K0SEG(PCIA_SGMAP_PT + sc->sysbase);
|
|
for (i = 0; i < lim; i++)
|
|
tbl[i] = 0;
|
|
|
|
#if 0
|
|
/* XXX NOT DONE YET XXX */
|
|
/*
|
|
* Initialize the SGMAP for window C:
|
|
*
|
|
* Size: 256M or 1GB
|
|
* Window base: 1GB
|
|
* SGVA base: 0
|
|
*/
|
|
chipset.sgmap = sgmap_map_create(sgwbase, sgwend, dwlpx_sgmap_map, tbl);
|
|
#endif
|
|
|
|
/*
|
|
* Set up DMA windows for this DWLPx.
|
|
*/
|
|
for (i = 0; i < sc->nhpc; i++) {
|
|
REGVAL(PCIA_WMASK_A(i) + sc->sysbase) =
|
|
DWLPx_DIRECT_MAPPED_WMASK;
|
|
REGVAL(PCIA_TBASE_A(i) + sc->sysbase) = 0;
|
|
REGVAL(PCIA_WBASE_A(i) + sc->sysbase) =
|
|
DWLPx_DIRECT_MAPPED_BASE | PCIA_WBASE_W_EN;
|
|
|
|
REGVAL(PCIA_WMASK_B(i) + sc->sysbase) = 0;
|
|
REGVAL(PCIA_TBASE_B(i) + sc->sysbase) = 0;
|
|
REGVAL(PCIA_WBASE_B(i) + sc->sysbase) = 0;
|
|
|
|
REGVAL(PCIA_WMASK_C(i) + sc->sysbase) = sgwmask;
|
|
REGVAL(PCIA_TBASE_C(i) + sc->sysbase) = 0;
|
|
REGVAL(PCIA_WBASE_C(i) + sc->sysbase) =
|
|
sgwbase | PCIA_WBASE_W_EN | PCIA_WBASE_SG_EN;
|
|
}
|
|
alpha_mb();
|
|
|
|
/* XXX XXX BEGIN XXX XXX */
|
|
{ /* XXX */
|
|
alpha_XXX_dmamap_or = DWLPx_DIRECT_MAPPED_BASE; /* XXX */
|
|
} /* XXX */
|
|
/* XXX XXX END XXX XXX */
|
|
}
|
|
|
|
/*
|
|
*/
|
|
|
|
static void
|
|
dwlpx_intr(void *arg)
|
|
{
|
|
#ifdef SIMOS
|
|
extern void simos_intr(int);
|
|
simos_intr(0);
|
|
#else
|
|
unsigned long vec = (unsigned long) arg;
|
|
if ((vec & DWLPX_VEC_EMARK) != 0) {
|
|
dwlpx_eintr(vec);
|
|
return;
|
|
}
|
|
if ((vec & DWLPX_VEC_MARK) == 0) {
|
|
panic("dwlpx_intr: bad vector %p", arg);
|
|
/* NOTREACHED */
|
|
}
|
|
alpha_dispatch_intr(NULL, vec);
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
dwlpx_eintr(unsigned long vec)
|
|
{
|
|
device_t dev;
|
|
struct dwlpx_softc *sc;
|
|
int ionode, hosenum, i;
|
|
struct {
|
|
u_int32_t err;
|
|
u_int32_t addr;
|
|
} hpcs[NHPC];
|
|
|
|
ionode = (vec >> 8) & 0xf;
|
|
hosenum = (vec >> 4) & 0x7;
|
|
if (ionode >= DWLPX_NIONODE || hosenum >= DWLPX_NHOSE) {
|
|
panic("dwlpx_iointr: mangled vector 0x%lx", vec);
|
|
/* NOTREACHED */
|
|
}
|
|
dev = dwlpxs[ionode][hosenum];
|
|
sc = DWLPX_SOFTC(dev);
|
|
for (i = 0; i < sc->nhpc; i++) {
|
|
hpcs[i].err = REGVAL(PCIA_ERR(i) + sc->sysbase);
|
|
hpcs[i].addr = REGVAL(PCIA_FADR(i) + sc->sysbase);
|
|
}
|
|
printf("%s: node %d hose %d error interrupt\n",
|
|
device_get_nameunit(dev), ionode + 4, hosenum);
|
|
|
|
for (i = 0; i < sc->nhpc; i++) {
|
|
if ((hpcs[i].err & PCIA_ERR_ERROR) == 0)
|
|
continue;
|
|
printf("\tHPC %d: ERR=0x%08x; DMA %s Memory, "
|
|
"Failing Address 0x%x\n",
|
|
i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" :
|
|
"read from", hpcs[i].addr & ~3);
|
|
if (hpcs[i].err & PCIA_ERR_SERR_L)
|
|
printf("\t PCI device asserted SERR_L\n");
|
|
if (hpcs[i].err & PCIA_ERR_ILAT)
|
|
printf("\t Incremental Latency Exceeded\n");
|
|
if (hpcs[i].err & PCIA_ERR_SGPRTY)
|
|
printf("\t CPU access of SG RAM Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_ILLCSR)
|
|
printf("\t Illegal CSR Address Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_PCINXM)
|
|
printf("\t Nonexistent PCI Address Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_DSCERR)
|
|
printf("\t PCI Target Disconnect Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_ABRT)
|
|
printf("\t PCI Target Abort Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_WPRTY)
|
|
printf("\t PCI Write Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_DPERR)
|
|
printf("\t PCI Data Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_APERR)
|
|
printf("\t PCI Address Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_DFLT)
|
|
printf("\t SG Map RAM Invalid Entry Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_DPRTY)
|
|
printf("\t DMA access of SG RAM Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_DRPERR)
|
|
printf("\t DMA Read Return Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_MABRT)
|
|
printf("\t PCI Master Abort Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_CPRTY)
|
|
printf("\t CSR Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_COVR)
|
|
printf("\t CSR Overrun Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_MBPERR)
|
|
printf("\t Mailbox Parity Error\n");
|
|
if (hpcs[i].err & PCIA_ERR_MBILI)
|
|
printf("\t Mailbox Illegal Length Error\n");
|
|
REGVAL(PCIA_ERR(i) + sc->sysbase) = hpcs[i].err;
|
|
}
|
|
}
|
|
|
|
static device_method_t dwlpx_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, dwlpx_probe),
|
|
DEVMETHOD(device_attach, dwlpx_attach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_read_ivar, dwlpx_read_ivar),
|
|
DEVMETHOD(bus_setup_intr, dwlpx_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, dwlpx_teardown_intr),
|
|
DEVMETHOD(bus_alloc_resource, alpha_pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, pci_release_resource),
|
|
DEVMETHOD(bus_activate_resource, pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
|
|
|
|
/* alphapci interface */
|
|
DEVMETHOD(alphapci_cvt_dense, dwlpx_cvt_dense),
|
|
DEVMETHOD(alphapci_get_bustag, dwlpx_get_bustag),
|
|
DEVMETHOD(alphapci_get_rman, dwlpx_get_rman),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, dwlpx_maxslots),
|
|
DEVMETHOD(pcib_read_config, dwlpx_read_config),
|
|
DEVMETHOD(pcib_write_config, dwlpx_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, alpha_pci_route_interrupt),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t dwlpx_driver = {
|
|
"pcib", dwlpx_methods, sizeof (struct dwlpx_softc)
|
|
};
|
|
|
|
DRIVER_MODULE(pcib, kft, dwlpx_driver, dwlpx_devclass, 0, 0);
|