fd036deac1
Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
181 lines
6.2 KiB
C
181 lines
6.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __X86_INTR_MACHDEP_H__
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#define __X86_INTR_MACHDEP_H__
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#ifdef _KERNEL
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/*
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* Values used in determining the allocation of IRQ values among
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* different types of I/O interrupts. These values are used as
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* indices into a interrupt source array to map I/O interrupts to a
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* device interrupt source whether it be a pin on an interrupt
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* controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
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* IDT vectors, but all other device interrupts allocate IDT vectors
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* on demand. Currently we have 191 IDT vectors available for device
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* interrupts on each CPU. On many systems with I/O APICs, a lot of
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* the IRQs are not used, so the total number of IRQ values reserved
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* can exceed the number of available IDT slots.
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*
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* The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
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* pins on I/O APICs for non-ISA interrupts use IRQ values starting at
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* IRQ 17. This layout matches the GSI numbering used by ACPI so that
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* IRQ values returned by ACPI methods such as _CRS can be used
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* directly by the ACPI bus driver.
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*
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* MSI interrupts allocate a block of interrupts starting at either
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* the end of the I/O APIC range or 256, whichever is higher. When
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* running under the Xen Hypervisor, an additional range of IRQ values
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* are available for binding to event channel events. We use 256 as
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* the minimum IRQ value for MSI interrupts to attempt to leave 255
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* unused since 255 is used in PCI to indicate an invalid INTx IRQ.
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*/
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#define NUM_MSI_INTS 512
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#define MINIMUM_MSI_INT 256
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extern u_int first_msi_irq;
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extern u_int num_io_irqs;
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/*
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* Default base address for MSI messages on x86 platforms.
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*/
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#define MSI_INTEL_ADDR_BASE 0xfee00000
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#ifndef LOCORE
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typedef void inthand_t(void);
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#define IDTVEC(name) __CONCAT(X,name)
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struct intsrc;
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/*
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* Methods that a PIC provides to mask/unmask a given interrupt source,
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* "turn on" the interrupt on the CPU side by setting up an IDT entry, and
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* return the vector associated with this source.
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*/
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struct pic {
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void (*pic_register_sources)(struct pic *);
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void (*pic_enable_source)(struct intsrc *);
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void (*pic_disable_source)(struct intsrc *, int);
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void (*pic_eoi_source)(struct intsrc *);
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void (*pic_enable_intr)(struct intsrc *);
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void (*pic_disable_intr)(struct intsrc *);
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int (*pic_vector)(struct intsrc *);
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int (*pic_source_pending)(struct intsrc *);
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void (*pic_suspend)(struct pic *);
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void (*pic_resume)(struct pic *, bool suspend_cancelled);
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int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
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enum intr_polarity);
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int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
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void (*pic_reprogram_pin)(struct intsrc *);
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TAILQ_ENTRY(pic) pics;
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};
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/* Flags for pic_disable_source() */
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enum {
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PIC_EOI,
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PIC_NO_EOI,
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};
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/*
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* An interrupt source. The upper-layer code uses the PIC methods to
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* control a given source. The lower-layer PIC drivers can store additional
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* private data in a given interrupt source such as an interrupt pin number
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* or an I/O APIC pointer.
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*/
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struct intsrc {
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struct pic *is_pic;
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struct intr_event *is_event;
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u_long *is_count;
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u_long *is_straycount;
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u_int is_index;
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u_int is_handlers;
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u_int is_domain;
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u_int is_cpu;
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};
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struct trapframe;
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#ifdef SMP
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extern cpuset_t intr_cpus;
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#endif
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extern struct mtx icu_lock;
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extern int elcr_found;
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#ifdef SMP
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extern int msix_disable_migration;
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#endif
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#ifndef DEV_ATPIC
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void atpic_reset(void);
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#endif
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/* XXX: The elcr_* prototypes probably belong somewhere else. */
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int elcr_probe(void);
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enum intr_trigger elcr_read_trigger(u_int irq);
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void elcr_resume(void);
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void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
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#ifdef SMP
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void intr_add_cpu(u_int cpu);
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#endif
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int intr_add_handler(const char *name, int vector, driver_filter_t filter,
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driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep,
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int domain);
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#ifdef SMP
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int intr_bind(u_int vector, u_char cpu);
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#endif
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int intr_config_intr(int vector, enum intr_trigger trig,
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enum intr_polarity pol);
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int intr_describe(u_int vector, void *ih, const char *descr);
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void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
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u_int intr_next_cpu(int domain);
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struct intsrc *intr_lookup_source(int vector);
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int intr_register_pic(struct pic *pic);
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int intr_register_source(struct intsrc *isrc);
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int intr_remove_handler(void *cookie);
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void intr_resume(bool suspend_cancelled);
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void intr_suspend(void);
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void intr_reprogram(void);
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void intrcnt_add(const char *name, u_long **countp);
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void nexus_add_irq(u_long irq);
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int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
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void msi_init(void);
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int msi_map(int irq, uint64_t *addr, uint32_t *data);
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int msi_release(int *irqs, int count);
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int msix_alloc(device_t dev, int *irq);
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int msix_release(int irq);
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#ifdef XENHVM
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void xen_intr_alloc_irqs(void);
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#endif
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#endif /* !LOCORE */
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#endif /* _KERNEL */
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#endif /* !__X86_INTR_MACHDEP_H__ */
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