318224bbe6
Make the amd64/pmap code aware of nested page table mappings used by bhyve guests. This allows bhyve to associate each guest with its own vmspace and deal with nested page faults in the context of that vmspace. This also enables features like accessed/dirty bit tracking, swapping to disk and transparent superpage promotions of guest memory. Guest vmspace: Each bhyve guest has a unique vmspace to represent the physical memory allocated to the guest. Each memory segment allocated by the guest is mapped into the guest's address space via the 'vmspace->vm_map' and is backed by an object of type OBJT_DEFAULT. pmap types: The amd64/pmap now understands two types of pmaps: PT_X86 and PT_EPT. The PT_X86 pmap type is used by the vmspace associated with the host kernel as well as user processes executing on the host. The PT_EPT pmap is used by the vmspace associated with a bhyve guest. Page Table Entries: The EPT page table entries as mostly similar in functionality to regular page table entries although there are some differences in terms of what bits are used to express that functionality. For e.g. the dirty bit is represented by bit 9 in the nested PTE as opposed to bit 6 in the regular x86 PTE. Therefore the bitmask representing the dirty bit is now computed at runtime based on the type of the pmap. Thus PG_M that was previously a macro now becomes a local variable that is initialized at runtime using 'pmap_modified_bit(pmap)'. An additional wrinkle associated with EPT mappings is that older Intel processors don't have hardware support for tracking accessed/dirty bits in the PTE. This means that the amd64/pmap code needs to emulate these bits to provide proper accounting to the VM subsystem. This is achieved by using the following mapping for EPT entries that need emulation of A/D bits: Bit Position Interpreted By PG_V 52 software (accessed bit emulation handler) PG_RW 53 software (dirty bit emulation handler) PG_A 0 hardware (aka EPT_PG_RD) PG_M 1 hardware (aka EPT_PG_WR) The idea to use the mapping listed above for A/D bit emulation came from Alan Cox (alc@). The final difference with respect to x86 PTEs is that some EPT implementations do not support superpage mappings. This is recorded in the 'pm_flags' field of the pmap. TLB invalidation: The amd64/pmap code has a number of ways to do invalidation of mappings that may be cached in the TLB: single page, multiple pages in a range or the entire TLB. All of these funnel into a single EPT invalidation routine called 'pmap_invalidate_ept()'. This routine bumps up the EPT generation number and sends an IPI to the host cpus that are executing the guest's vcpus. On a subsequent entry into the guest it will detect that the EPT has changed and invalidate the mappings from the TLB. Guest memory access: Since the guest memory is no longer wired we need to hold the host physical page that backs the guest physical page before we can access it. The helper functions 'vm_gpa_hold()/vm_gpa_release()' are available for this purpose. PCI passthru: Guest's with PCI passthru devices will wire the entire guest physical address space. The MMIO BAR associated with the passthru device is backed by a vm_object of type OBJT_SG. An IOMMU domain is created only for guest's that have one or more PCI passthru devices attached to them. Limitations: There isn't a way to map a guest physical page without execute permissions. This is because the amd64/pmap code interprets the guest physical mappings as user mappings since they are numerically below VM_MAXUSER_ADDRESS. Since PG_U shares the same bit position as EPT_PG_EXECUTE all guest mappings become automatically executable. Thanks to Alan Cox and Konstantin Belousov for their rigorous code reviews as well as their support and encouragement. Thanks for John Baldwin for reviewing the use of OBJT_SG as the backing object for pci passthru mmio regions. Special thanks to Peter Holm for testing the patch on short notice. Approved by: re Discussed with: grehan Reviewed by: alc, kib Tested by: pho
229 lines
5.5 KiB
C
229 lines
5.5 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VMM_DEV_H_
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#define _VMM_DEV_H_
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#ifdef _KERNEL
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void vmmdev_init(void);
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int vmmdev_cleanup(void);
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#endif
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struct vm_memory_segment {
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vm_paddr_t gpa; /* in */
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size_t len;
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int wired;
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};
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struct vm_register {
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int cpuid;
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int regnum; /* enum vm_reg_name */
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uint64_t regval;
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};
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struct vm_seg_desc { /* data or code segment */
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int cpuid;
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int regnum; /* enum vm_reg_name */
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struct seg_desc desc;
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};
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struct vm_run {
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int cpuid;
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uint64_t rip; /* start running here */
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struct vm_exit vm_exit;
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};
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struct vm_event {
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int cpuid;
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enum vm_event_type type;
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int vector;
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uint32_t error_code;
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int error_code_valid;
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};
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struct vm_lapic_irq {
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int cpuid;
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int vector;
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};
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struct vm_capability {
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int cpuid;
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enum vm_cap_type captype;
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int capval;
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int allcpus;
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};
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struct vm_pptdev {
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int bus;
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int slot;
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int func;
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};
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struct vm_pptdev_mmio {
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int bus;
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int slot;
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int func;
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vm_paddr_t gpa;
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vm_paddr_t hpa;
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size_t len;
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};
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struct vm_pptdev_msi {
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int vcpu;
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int bus;
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int slot;
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int func;
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int numvec; /* 0 means disabled */
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int vector;
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int destcpu;
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};
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struct vm_pptdev_msix {
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int vcpu;
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int bus;
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int slot;
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int func;
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int idx;
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uint32_t msg;
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uint32_t vector_control;
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uint64_t addr;
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};
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struct vm_nmi {
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int cpuid;
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};
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#define MAX_VM_STATS 64
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struct vm_stats {
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int cpuid; /* in */
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int num_entries; /* out */
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struct timeval tv;
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uint64_t statbuf[MAX_VM_STATS];
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};
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struct vm_stat_desc {
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int index; /* in */
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char desc[128]; /* out */
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};
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struct vm_x2apic {
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int cpuid;
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enum x2apic_state state;
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};
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struct vm_gpa_pte {
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uint64_t gpa; /* in */
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uint64_t pte[4]; /* out */
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int ptenum;
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};
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enum {
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/* general routines */
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IOCNUM_ABIVERS = 0,
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IOCNUM_RUN = 1,
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IOCNUM_SET_CAPABILITY = 2,
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IOCNUM_GET_CAPABILITY = 3,
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/* memory apis */
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IOCNUM_MAP_MEMORY = 10,
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IOCNUM_GET_MEMORY_SEG = 11,
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IOCNUM_GET_GPA_PMAP = 12,
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/* register/state accessors */
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IOCNUM_SET_REGISTER = 20,
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IOCNUM_GET_REGISTER = 21,
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IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
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IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
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/* interrupt injection */
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IOCNUM_INJECT_EVENT = 30,
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IOCNUM_LAPIC_IRQ = 31,
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IOCNUM_INJECT_NMI = 32,
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/* PCI pass-thru */
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IOCNUM_BIND_PPTDEV = 40,
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IOCNUM_UNBIND_PPTDEV = 41,
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IOCNUM_MAP_PPTDEV_MMIO = 42,
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IOCNUM_PPTDEV_MSI = 43,
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IOCNUM_PPTDEV_MSIX = 44,
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/* statistics */
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IOCNUM_VM_STATS = 50,
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IOCNUM_VM_STAT_DESC = 51,
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/* kernel device state */
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IOCNUM_SET_X2APIC_STATE = 60,
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IOCNUM_GET_X2APIC_STATE = 61,
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};
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#define VM_RUN \
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_IOWR('v', IOCNUM_RUN, struct vm_run)
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#define VM_MAP_MEMORY \
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_IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
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#define VM_GET_MEMORY_SEG \
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_IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
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#define VM_SET_REGISTER \
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_IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
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#define VM_GET_REGISTER \
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_IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
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#define VM_SET_SEGMENT_DESCRIPTOR \
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_IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
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#define VM_GET_SEGMENT_DESCRIPTOR \
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_IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
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#define VM_INJECT_EVENT \
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_IOW('v', IOCNUM_INJECT_EVENT, struct vm_event)
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#define VM_LAPIC_IRQ \
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_IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
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#define VM_SET_CAPABILITY \
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_IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
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#define VM_GET_CAPABILITY \
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_IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
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#define VM_BIND_PPTDEV \
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_IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
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#define VM_UNBIND_PPTDEV \
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_IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
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#define VM_MAP_PPTDEV_MMIO \
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_IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
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#define VM_PPTDEV_MSI \
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_IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
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#define VM_PPTDEV_MSIX \
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_IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
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#define VM_INJECT_NMI \
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_IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
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#define VM_STATS \
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_IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
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#define VM_STAT_DESC \
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_IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
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#define VM_SET_X2APIC_STATE \
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_IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
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#define VM_GET_X2APIC_STATE \
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_IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
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#define VM_GET_GPA_PMAP \
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_IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
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#endif
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