04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
249 lines
8.0 KiB
C
249 lines
8.0 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Utility functions for working with the CSR database
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*
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* <hr>$Revision: 49507 $<hr>
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*/
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#define PRINTF printk
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-csr-db.h>
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#else
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#define PRINTF printf
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#include "cvmx.h"
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#include "cvmx-csr-db.h"
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#endif
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/**
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* Figure out which database to use for this chip. The passed
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* identifier can be a processor ID or a PCI ID.
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*
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* @param identifier processor ID or a PCI ID
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*
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* @return index into the csr db
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*/
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int cvmx_db_get_chipindex(int identifier)
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{
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/* First try and see if the identifier is a Processor ID */
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switch (identifier & 0xffff00)
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{
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case 0x000d0600: /* CN50XX */
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return 8;
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case 0x000d0400: /* CN56XX */
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return 7;
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case 0x000d0300: /* CN58XX */
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return 5;
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case 0x000d0000: /* CN38XX */
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return 3;
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case 0x000d0100: /* CN31XX */
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return 1;
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case 0x000d0200: /* CN3010 */
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return 2;
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case 0x000d0700: /* CN52XX */
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return 10;
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case 0x000d9000: /* CN63XX */
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return 11;
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}
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/* Next try PCI device IDs */
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switch (identifier)
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{
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case 0x0003177d: /* CN38XX Pass 1 */
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return 0;
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case 0x0004177d: /* CN38XX Pass 2 */
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return 0;
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case 0x0005177d: /* CN38XX Pass 3 */
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return 3;
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case 0x1001177d: /* Thunder */
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return 3;
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case 0x0020177d: /* CN31XX Pass 1 */
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return 1;
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case 0x0030177d: /* CN30XX Pass 1 */
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return 2;
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case 0x0040177d: /* CN58XX Pass 2 */
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return 5;
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case 0x0050177d: /* CN56XX Pass 2 */
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return 7;
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case 0x0070177d: /* CN50XX Pass 1 */
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return 8;
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case 0x0080177d: /* CN52XX Pass 2 */
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return 10;
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case 0x0090177d: /* CN63XX Pass 1 */
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return 11;
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}
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/* Default to Pass 3 if we don't know */
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return 3;
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}
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#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
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/**
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* Get the CSR DB entry for the passed Octeon model and CSR name. The
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* model can either be specified as a processor id or PCI id.
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*
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* @param identifier Identifer to choose the CSR DB with
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* @param name CSR name to lookup
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*
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* @return CSR DB entry or NULL on failure
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*/
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const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_get(int identifier, const char *name)
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{
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int chip = cvmx_db_get_chipindex(identifier);
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int i=0;
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if (strncasecmp(name, "CVMX_", 5) == 0)
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name += 5;
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while (cvmx_csr_db_addresses[chip][i].name)
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{
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if (strcasecmp(name, cvmx_csr_db_addresses[chip][i].name) == 0)
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return &(cvmx_csr_db_addresses[chip][i]);
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i++;
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}
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return NULL;
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}
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#endif
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static void __cvmx_csr_db_decode_csr(int chip, int index, uint64_t value)
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{
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int field;
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int csr = cvmx_csr_db_addresses[chip][index].csroff;
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PRINTF("%s(0x%016llx) = 0x%016llx\n", cvmx_csr_db_addresses[chip][index].name, (unsigned long long)cvmx_csr_db_addresses[chip][index].address, (unsigned long long)value);
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for (field=cvmx_csr_db[chip][csr].fieldoff+cvmx_csr_db[chip][csr].numfields-1; field>=cvmx_csr_db[chip][csr].fieldoff; field--)
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{
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uint64_t v = (value >> cvmx_csr_db_fields[chip][field].startbit);
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if(cvmx_csr_db_fields[chip][field].sizebits < 64)
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v = v & ~((~0x0ull) << cvmx_csr_db_fields[chip][field].sizebits);
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if (cvmx_csr_db_fields[chip][field].sizebits == 1)
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PRINTF(" [ %2d] %-20s = %10llu (0x%llx)\n",
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cvmx_csr_db_fields[chip][field].startbit, cvmx_csr_db_fields[chip][field].name,
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(unsigned long long)v, (unsigned long long)v);
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else
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PRINTF(" [%2d:%2d] %-20s = %10llu (0x%llx)\n",
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cvmx_csr_db_fields[chip][field].startbit + cvmx_csr_db_fields[chip][field].sizebits - 1,
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cvmx_csr_db_fields[chip][field].startbit,
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cvmx_csr_db_fields[chip][field].name,
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(unsigned long long)v, (unsigned long long)v);
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}
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}
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/**
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* Decode a CSR value into named bitfields. The model can either
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* be specified as a processor id or PCI id.
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*
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* @param identifier Identifer to choose the CSR DB with
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* @param address CSR address being decoded
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* @param value Value to decode
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*/
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void cvmx_csr_db_decode(int identifier, uint64_t address, uint64_t value)
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{
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int chip = cvmx_db_get_chipindex(identifier);
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int index=0;
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/* Strip off the upper 8 bits since they are normally mips addressing
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modes */
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address &= (1ull<<56)-1;
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while (cvmx_csr_db_addresses[chip][index].name)
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{
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if (cvmx_csr_db_addresses[chip][index].address == address)
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__cvmx_csr_db_decode_csr(chip, index, value);
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index++;
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}
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}
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/**
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* Decode a CSR value into named bitfields. The model can either
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* be specified as a processor id or PCI id.
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*
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* @param identifier Identifer to choose the CSR DB with
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* @param name CSR name to decode
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* @param value Value to decode
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*/
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void cvmx_csr_db_decode_by_name(int identifier, const char *name, uint64_t value)
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{
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int chip = cvmx_db_get_chipindex(identifier);
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int index=0;
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while (cvmx_csr_db_addresses[chip][index].name)
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{
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if (strcasecmp(name, cvmx_csr_db_addresses[chip][index].name) == 0)
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{
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__cvmx_csr_db_decode_csr(chip, index, value);
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break;
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}
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index++;
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}
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}
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#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
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/**
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* Print a list of csrs begimning with a prefix. The
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* model can either be specified as a processor id or PCI id.
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*
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* @param identifier Identifer to choose the CSR DB with
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* @param prefix Beginning prefix to look for
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*/
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void cvmx_csr_db_display_list(int identifier, const char *prefix)
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{
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int i, len;
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int chip = cvmx_db_get_chipindex(identifier);
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if (prefix == NULL)
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prefix = "";
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if (strncasecmp(prefix, "CVMX_", 5) == 0)
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prefix += 5;
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len = strlen(prefix);
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i=0;
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while (cvmx_csr_db_addresses[chip][i].name)
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{
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if (strncasecmp(prefix, cvmx_csr_db_addresses[chip][i].name, len) == 0)
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PRINTF("%s\n", cvmx_csr_db_addresses[chip][i].name);
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i++;
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}
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}
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#endif
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